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[/] [structural_vhdl/] [tags/] [vlsi/] [main control/] [mux01.vst] - Blame information for rev 4

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-- VHDL structural description generated from `mux01`
--              date : Sat Sep  1 20:26:19 2001
 
 
-- Entity Declaration
 
ENTITY mux01 IS
  PORT (
  a : in BIT;   -- a
  b : in BIT;   -- b
  c : in BIT;   -- c
  d : in BIT;   -- d
  sel : in BIT_VECTOR (1 DOWNTO 0);     -- sel
  o : out BIT;  -- o
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END mux01;
 
-- Architecture Declaration
 
ARCHITECTURE VST OF mux01 IS
  COMPONENT o4_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    i3 : in BIT;        -- i3
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT no2_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT o2_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT no3_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT inv_x1
    port (
    i : in BIT; -- i
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  SIGNAL auxsc6 : BIT;  -- auxsc6
  SIGNAL auxsc9 : BIT;  -- auxsc9
  SIGNAL auxsc10 : BIT; -- auxsc10
  SIGNAL auxsc4 : BIT;  -- auxsc4
  SIGNAL auxsc11 : BIT; -- auxsc11
  SIGNAL auxsc12 : BIT; -- auxsc12
  SIGNAL auxsc13 : BIT; -- auxsc13
  SIGNAL auxsc14 : BIT; -- auxsc14
  SIGNAL auxsc15 : BIT; -- auxsc15
  SIGNAL auxsc16 : BIT; -- auxsc16
  SIGNAL auxsc17 : BIT; -- auxsc17
 
BEGIN
 
  o : o4_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => o,
    i3 => auxsc17,
    i2 => auxsc14,
    i1 => auxsc12,
    i0 => auxsc10);
  auxsc17 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc17,
    i1 => auxsc16,
    i0 => auxsc15);
  auxsc16 : o2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc16,
    i1 => sel(1),
    i0 => sel(0));
  auxsc15 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc15,
    i => a);
  auxsc14 : no3_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc14,
    i2 => auxsc13,
    i1 => auxsc4,
    i0 => auxsc6);
  auxsc13 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc13,
    i => d);
  auxsc12 : no3_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc12,
    i2 => auxsc11,
    i1 => auxsc4,
    i0 => sel(0));
  auxsc11 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc11,
    i => c);
  auxsc4 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc4,
    i => sel(1));
  auxsc10 : no3_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc10,
    i2 => auxsc9,
    i1 => auxsc6,
    i0 => sel(1));
  auxsc9 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc9,
    i => b);
  auxsc6 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc6,
    i => sel(0));
 
end VST;

Line No.	Rev	Author	Line
1	2	marta	-- VHDL structural description generated from `mux01`
2			`-- date : Sat Sep 1 20:26:19 2001`
3
4
5			`-- Entity Declaration`
6
7			`ENTITY mux01 IS`
8			`PORT (`
9			`a : in BIT; -- a`
10			`b : in BIT; -- b`
11			`c : in BIT; -- c`
12			`d : in BIT; -- d`
13			`sel : in BIT_VECTOR (1 DOWNTO 0); -- sel`
14			`o : out BIT; -- o`
15			`vdd : in BIT; -- vdd`
16			`vss : in BIT -- vss`
17			`);`
18			`END mux01;`
19
20			`-- Architecture Declaration`
21
22			`ARCHITECTURE VST OF mux01 IS`
23			`COMPONENT o4_x2`
24			`port (`
25			`i0 : in BIT; -- i0`
26			`i1 : in BIT; -- i1`
27			`i2 : in BIT; -- i2`
28			`i3 : in BIT; -- i3`
29			`q : out BIT; -- q`
30			`vdd : in BIT; -- vdd`
31			`vss : in BIT -- vss`
32			`);`
33			`END COMPONENT;`
34
35			`COMPONENT no2_x1`
36			`port (`
37			`i0 : in BIT; -- i0`
38			`i1 : in BIT; -- i1`
39			`nq : out BIT; -- nq`
40			`vdd : in BIT; -- vdd`
41			`vss : in BIT -- vss`
42			`);`
43			`END COMPONENT;`
44
45			`COMPONENT o2_x2`
46			`port (`
47			`i0 : in BIT; -- i0`
48			`i1 : in BIT; -- i1`
49			`q : out BIT; -- q`
50			`vdd : in BIT; -- vdd`
51			`vss : in BIT -- vss`
52			`);`
53			`END COMPONENT;`
54
55			`COMPONENT no3_x1`
56			`port (`
57			`i0 : in BIT; -- i0`
58			`i1 : in BIT; -- i1`
59			`i2 : in BIT; -- i2`
60			`nq : out BIT; -- nq`
61			`vdd : in BIT; -- vdd`
62			`vss : in BIT -- vss`
63			`);`
64			`END COMPONENT;`
65
66			`COMPONENT inv_x1`
67			`port (`
68			`i : in BIT; -- i`
69			`nq : out BIT; -- nq`
70			`vdd : in BIT; -- vdd`
71			`vss : in BIT -- vss`
72			`);`
73			`END COMPONENT;`
74
75			`SIGNAL auxsc6 : BIT; -- auxsc6`
76			`SIGNAL auxsc9 : BIT; -- auxsc9`
77			`SIGNAL auxsc10 : BIT; -- auxsc10`
78			`SIGNAL auxsc4 : BIT; -- auxsc4`
79			`SIGNAL auxsc11 : BIT; -- auxsc11`
80			`SIGNAL auxsc12 : BIT; -- auxsc12`
81			`SIGNAL auxsc13 : BIT; -- auxsc13`
82			`SIGNAL auxsc14 : BIT; -- auxsc14`
83			`SIGNAL auxsc15 : BIT; -- auxsc15`
84			`SIGNAL auxsc16 : BIT; -- auxsc16`
85			`SIGNAL auxsc17 : BIT; -- auxsc17`
86
87			`BEGIN`
88
89			`o : o4_x2`
90			`PORT MAP (`
91			`vss => vss,`
92			`vdd => vdd,`
93			`q => o,`
94			`i3 => auxsc17,`
95			`i2 => auxsc14,`
96			`i1 => auxsc12,`
97			`i0 => auxsc10);`
98			`auxsc17 : no2_x1`
99			`PORT MAP (`
100			`vss => vss,`
101			`vdd => vdd,`
102			`nq => auxsc17,`
103			`i1 => auxsc16,`
104			`i0 => auxsc15);`
105			`auxsc16 : o2_x2`
106			`PORT MAP (`
107			`vss => vss,`
108			`vdd => vdd,`
109			`q => auxsc16,`
110			`i1 => sel(1),`
111			`i0 => sel(0));`
112			`auxsc15 : inv_x1`
113			`PORT MAP (`
114			`vss => vss,`
115			`vdd => vdd,`
116			`nq => auxsc15,`
117			`i => a);`
118			`auxsc14 : no3_x1`
119			`PORT MAP (`
120			`vss => vss,`
121			`vdd => vdd,`
122			`nq => auxsc14,`
123			`i2 => auxsc13,`
124			`i1 => auxsc4,`
125			`i0 => auxsc6);`
126			`auxsc13 : inv_x1`
127			`PORT MAP (`
128			`vss => vss,`
129			`vdd => vdd,`
130			`nq => auxsc13,`
131			`i => d);`
132			`auxsc12 : no3_x1`
133			`PORT MAP (`
134			`vss => vss,`
135			`vdd => vdd,`
136			`nq => auxsc12,`
137			`i2 => auxsc11,`
138			`i1 => auxsc4,`
139			`i0 => sel(0));`
140			`auxsc11 : inv_x1`
141			`PORT MAP (`
142			`vss => vss,`
143			`vdd => vdd,`
144			`nq => auxsc11,`
145			`i => c);`
146			`auxsc4 : inv_x1`
147			`PORT MAP (`
148			`vss => vss,`
149			`vdd => vdd,`
150			`nq => auxsc4,`
151			`i => sel(1));`
152			`auxsc10 : no3_x1`
153			`PORT MAP (`
154			`vss => vss,`
155			`vdd => vdd,`
156			`nq => auxsc10,`
157			`i2 => auxsc9,`
158			`i1 => auxsc6,`
159			`i0 => sel(1));`
160			`auxsc9 : inv_x1`
161			`PORT MAP (`
162			`vss => vss,`
163			`vdd => vdd,`
164			`nq => auxsc9,`
165			`i => b);`
166			`auxsc6 : inv_x1`
167			`PORT MAP (`
168			`vss => vss,`
169			`vdd => vdd,`
170			`nq => auxsc6,`
171			`i => sel(0));`
172
173			`end VST;`

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[/] [structural_vhdl/] [tags/] [vlsi/] [main control/] [mux01.vst] - Blame information for rev 4