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[/] [structural_vhdl/] [trunk/] [idea_machine/] [comp1_glopg.vst] - Blame information for rev 4

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1 2 marta 
-- VHDL structural description generated from `comp1_glopg`
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--              date : Sat Sep  8 01:24:45 2001
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-- Entity Declaration
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ENTITY comp1_glopg IS
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  PORT (
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  kin : in BIT_VECTOR (15 DOWNTO 0);    -- kin
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  kout1 : out BIT_VECTOR (16 DOWNTO 0); -- kout1
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  vdd : in BIT; -- vdd
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  vss : in BIT  -- vss
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  );
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END comp1_glopg;
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-- Architecture Declaration
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ARCHITECTURE VST OF comp1_glopg IS
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  COMPONENT a4_x2
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    port (
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    i0 : in BIT;        -- i0
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    i1 : in BIT;        -- i1
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    i2 : in BIT;        -- i2
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    i3 : in BIT;        -- i3
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    q : out BIT;        -- q
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  COMPONENT no4_x1
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    port (
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    i0 : in BIT;        -- i0
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    i1 : in BIT;        -- i1
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    i2 : in BIT;        -- i2
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    i3 : in BIT;        -- i3
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    nq : out BIT;       -- nq
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  COMPONENT inv_x1
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    port (
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    i : in BIT; -- i
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    nq : out BIT;       -- nq
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  SIGNAL auxsc20 : BIT; -- auxsc20
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  SIGNAL auxsc19 : BIT; -- auxsc19
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  SIGNAL auxsc18 : BIT; -- auxsc18
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  SIGNAL auxsc17 : BIT; -- auxsc17
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  SIGNAL auxsc36 : BIT; -- auxsc36
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  SIGNAL auxsc35 : BIT; -- auxsc35
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  SIGNAL auxsc34 : BIT; -- auxsc34
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  SIGNAL auxsc33 : BIT; -- auxsc33
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  SIGNAL auxsc32 : BIT; -- auxsc32
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  SIGNAL auxsc31 : BIT; -- auxsc31
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  SIGNAL auxsc30 : BIT; -- auxsc30
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  SIGNAL auxsc29 : BIT; -- auxsc29
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  SIGNAL auxsc28 : BIT; -- auxsc28
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  SIGNAL auxsc27 : BIT; -- auxsc27
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  SIGNAL auxsc26 : BIT; -- auxsc26
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  SIGNAL auxsc25 : BIT; -- auxsc25
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  SIGNAL auxsc24 : BIT; -- auxsc24
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  SIGNAL auxsc23 : BIT; -- auxsc23
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  SIGNAL auxsc22 : BIT; -- auxsc22
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  SIGNAL auxsc21 : BIT; -- auxsc21
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BEGIN
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  kout1_0 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => kout1(0),
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    i => auxsc21);
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  kout1_1 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => kout1(1),
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    i => auxsc22);
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  kout1_2 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => kout1(2),
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    i => auxsc23);
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  kout1_3 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => kout1(3),
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    i => auxsc24);
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  kout1_4 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => kout1(4),
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    i => auxsc25);
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  kout1_5 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => kout1(5),
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    i => auxsc26);
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  kout1_6 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => kout1(6),
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    i => auxsc27);
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  kout1_7 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => kout1(7),
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    i => auxsc28);
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  kout1_8 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => kout1(8),
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    i => auxsc29);
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  kout1_9 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => kout1(9),
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    i => auxsc30);
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  kout1_10 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => kout1(10),
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    i => auxsc31);
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  kout1_11 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => kout1(11),
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    i => auxsc32);
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  kout1_12 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => kout1(12),
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    i => auxsc33);
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  kout1_13 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => kout1(13),
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    i => auxsc34);
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  kout1_14 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => kout1(14),
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    i => auxsc35);
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  kout1_15 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => kout1(15),
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    i => auxsc36);
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  kout1_16 : a4_x2
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => kout1(16),
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    i3 => auxsc20,
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    i2 => auxsc19,
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    i1 => auxsc18,
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    i0 => auxsc17);
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  auxsc20 : no4_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc20,
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    i3 => kin(15),
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    i2 => kin(14),
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    i1 => kin(13),
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    i0 => kin(12));
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  auxsc19 : no4_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc19,
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    i3 => kin(11),
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    i2 => kin(10),
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    i1 => kin(9),
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    i0 => kin(8));
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  auxsc18 : no4_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc18,
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    i3 => kin(7),
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    i2 => kin(6),
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    i1 => kin(5),
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    i0 => kin(4));
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  auxsc17 : no4_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc17,
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    i3 => kin(3),
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    i2 => kin(2),
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    i1 => kin(1),
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    i0 => kin(0));
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  auxsc36 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc36,
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    i => kin(15));
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  auxsc35 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc35,
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    i => kin(14));
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  auxsc34 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc34,
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    i => kin(13));
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  auxsc33 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc33,
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    i => kin(12));
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  auxsc32 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc32,
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    i => kin(11));
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  auxsc31 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc31,
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    i => kin(10));
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  auxsc30 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc30,
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    i => kin(9));
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  auxsc29 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc29,
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    i => kin(8));
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  auxsc28 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc28,
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    i => kin(7));
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  auxsc27 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc27,
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    i => kin(6));
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  auxsc26 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc26,
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    i => kin(5));
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  auxsc25 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc25,
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    i => kin(4));
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  auxsc24 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc24,
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    i => kin(3));
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  auxsc23 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc23,
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    i => kin(2));
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  auxsc22 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc22,
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    i => kin(1));
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  auxsc21 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc21,
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    i => kin(0));
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end VST;

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