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marta |
-- VHDL structural description generated from `idea_heart_test`
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-- date : Thu Sep 13 22:58:28 2001
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-- Entity Declaration
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ENTITY idea_heart_test IS
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PORT (
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en : in BIT_VECTOR (1 TO 7); -- en
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en_out : in BIT; -- en_out
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sel_in : in BIT; -- sel_in
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x1 : in BIT_VECTOR (0 TO 15); -- x1
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x2 : in BIT_VECTOR (0 TO 15); -- x2
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x3 : in BIT_VECTOR (0 TO 15); -- x3
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x4 : in BIT_VECTOR (0 TO 15); -- x4
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z1 : in BIT_VECTOR (0 TO 15); -- z1
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z2 : in BIT_VECTOR (0 TO 15); -- z2
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z3 : in BIT_VECTOR (0 TO 15); -- z3
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z4 : in BIT_VECTOR (0 TO 15); -- z4
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z5 : in BIT_VECTOR (0 TO 15); -- z5
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z6 : in BIT_VECTOR (0 TO 15); -- z6
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z19 : in BIT_VECTOR (0 TO 15); -- z19
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z29 : in BIT_VECTOR (0 TO 15); -- z29
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z39 : in BIT_VECTOR (0 TO 15); -- z39
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z49 : in BIT_VECTOR (0 TO 15); -- z49
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o_mux1 : inout BIT_VECTOR (0 TO 15); -- o_mux1
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o_mux2 : inout BIT_VECTOR (0 TO 15); -- o_mux2
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o_mux3 : inout BIT_VECTOR (0 TO 15); -- o_mux3
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o_mux4 : inout BIT_VECTOR (0 TO 15); -- o_mux4
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y1x : inout BIT_VECTOR (0 TO 15); -- y1x
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y2x : inout BIT_VECTOR (0 TO 15); -- y2x
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y3x : inout BIT_VECTOR (0 TO 15); -- y3x
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y4x : inout BIT_VECTOR (0 TO 15); -- y4x
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y1 : out BIT_VECTOR (0 TO 15); -- y1
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y2 : inout BIT_VECTOR (0 TO 15); -- y2
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y3 : inout BIT_VECTOR (0 TO 15); -- y3
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y4 : out BIT_VECTOR (0 TO 15); -- y4
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reset : in BIT; -- reset
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vdd : in BIT; -- vdd
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vss : in BIT -- vss
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);
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END idea_heart_test;
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-- Architecture Declaration
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ARCHITECTURE VST OF idea_heart_test IS
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COMPONENT mux64_glopg
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port (
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a : in BIT_VECTOR(63 DOWNTO 0); -- a
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b : in BIT_VECTOR(63 DOWNTO 0); -- b
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sel : in BIT; -- sel
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c : out BIT_VECTOR(63 DOWNTO 0); -- c
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vdd : in BIT; -- vdd
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vss : in BIT -- vss
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);
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END COMPONENT;
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COMPONENT idea_heart_1r_glopf
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port (
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en : in BIT_VECTOR(1 TO 7); -- en
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x1 : in BIT_VECTOR(0 TO 15); -- x1
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x2 : in BIT_VECTOR(0 TO 15); -- x2
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x3 : in BIT_VECTOR(0 TO 15); -- x3
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x4 : in BIT_VECTOR(0 TO 15); -- x4
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z1 : in BIT_VECTOR(0 TO 15); -- z1
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z2 : in BIT_VECTOR(0 TO 15); -- z2
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z3 : in BIT_VECTOR(0 TO 15); -- z3
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z4 : in BIT_VECTOR(0 TO 15); -- z4
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z5 : in BIT_VECTOR(0 TO 15); -- z5
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z6 : in BIT_VECTOR(0 TO 15); -- z6
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y1 : inout BIT_VECTOR(0 TO 15); -- y1
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y2 : inout BIT_VECTOR(0 TO 15); -- y2
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y3 : inout BIT_VECTOR(0 TO 15); -- y3
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y4 : inout BIT_VECTOR(0 TO 15); -- y4
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reset : in BIT; -- reset
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vdd : in BIT; -- vdd
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vss : in BIT -- vss
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);
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END COMPONENT;
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COMPONENT out_trans_glopf
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port (
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en : in BIT; -- en
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x1 : in BIT_VECTOR(0 TO 15); -- x1
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x2 : in BIT_VECTOR(0 TO 15); -- x2
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x3 : in BIT_VECTOR(0 TO 15); -- x3
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x4 : in BIT_VECTOR(0 TO 15); -- x4
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z1 : in BIT_VECTOR(0 TO 15); -- z1
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z2 : in BIT_VECTOR(0 TO 15); -- z2
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z3 : in BIT_VECTOR(0 TO 15); -- z3
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z4 : in BIT_VECTOR(0 TO 15); -- z4
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y1 : out BIT_VECTOR(0 TO 15); -- y1
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y2 : inout BIT_VECTOR(0 TO 15); -- y2
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y3 : inout BIT_VECTOR(0 TO 15); -- y3
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y4 : out BIT_VECTOR(0 TO 15); -- y4
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reset : in BIT; -- reset
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vdd : in BIT; -- vdd
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vss : in BIT -- vss
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);
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END COMPONENT;
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BEGIN
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mux1 : mux64_glopg
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PORT MAP (
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vss => vss,
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vdd => vdd,
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c => o_mux1(15)& o_mux1(14)& o_mux1(13)& o_mux1(12)& o_mux1(11)& o_mux1(10)& o_mux1(9)& o_mux1(8)& o_mux1(7)& o_mux1(6)& o_mux1(5)& o_mux1(4)& o_mux1(3)& o_mux1(2)& o_mux1(1)& o_mux1(0)& o_mux2(15)& o_mux2(14)& o_mux2(13)& o_mux2(12)& o_mux2(11)& o_mux2(10)& o_mux2(9)& o_mux2(8)& o_mux2(7)& o_mux2(6)& o_mux2(5)& o_mux2(4)& o_mux2(3)& o_mux2(2)& o_mux2(1)& o_mux2(0)& o_mux3(15)& o_mux3(14)& o_mux3(13)& o_mux3(12)& o_mux3(11)& o_mux3(10)& o_mux3(9)& o_mux3(8)& o_mux3(7)& o_mux3(6)& o_mux3(5)& o_mux3(4)& o_mux3(3)& o_mux3(2)& o_mux3(1)& o_mux3(0)& o_mux4(15)& o_mux4(14)& o_mux4(13)& o_mux4(12)& o_mux4(11)& o_mux4(10)& o_mux4(9)& o_mux4(8)& o_mux4(7)& o_mux4(6)& o_mux4(5)& o_mux4(4)& o_mux4(3)& o_mux4(2)& o_mux4(1)& o_mux4(0),
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sel => sel_in,
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b => y1x(15)& y1x(14)& y1x(13)& y1x(12)& y1x(11)& y1x(10)& y1x(9)& y1x(8)& y1x(7)& y1x(6)& y1x(5)& y1x(4)& y1x(3)& y1x(2)& y1x(1)& y1x(0)& y2x(15)& y2x(14)& y2x(13)& y2x(12)& y2x(11)& y2x(10)& y2x(9)& y2x(8)& y2x(7)& y2x(6)& y2x(5)& y2x(4)& y2x(3)& y2x(2)& y2x(1)& y2x(0)& y3x(15)& y3x(14)& y3x(13)& y3x(12)& y3x(11)& y3x(10)& y3x(9)& y3x(8)& y3x(7)& y3x(6)& y3x(5)& y3x(4)& y3x(3)& y3x(2)& y3x(1)& y3x(0)& y4x(15)& y4x(14)& y4x(13)& y4x(12)& y4x(11)& y4x(10)& y4x(9)& y4x(8)& y4x(7)& y4x(6)& y4x(5)& y4x(4)& y4x(3)& y4x(2)& y4x(1)& y4x(0),
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a => x1(15)& x1(14)& x1(13)& x1(12)& x1(11)& x1(10)& x1(9)& x1(8)& x1(7)& x1(6)& x1(5)& x1(4)& x1(3)& x1(2)& x1(1)& x1(0)& x2(15)& x2(14)& x2(13)& x2(12)& x2(11)& x2(10)& x2(9)& x2(8)& x2(7)& x2(6)& x2(5)& x2(4)& x2(3)& x2(2)& x2(1)& x2(0)& x3(15)& x3(14)& x3(13)& x3(12)& x3(11)& x3(10)& x3(9)& x3(8)& x3(7)& x3(6)& x3(5)& x3(4)& x3(3)& x3(2)& x3(1)& x3(0)& x4(15)& x4(14)& x4(13)& x4(12)& x4(11)& x4(10)& x4(9)& x4(8)& x4(7)& x4(6)& x4(5)& x4(4)& x4(3)& x4(2)& x4(1)& x4(0));
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idea_h_1r : idea_heart_1r_glopf
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PORT MAP (
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vss => vss,
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vdd => vdd,
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reset => reset,
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y4 => y4x(0)& y4x(1)& y4x(2)& y4x(3)& y4x(4)& y4x(5)& y4x(6)& y4x(7)& y4x(8)& y4x(9)& y4x(10)& y4x(11)& y4x(12)& y4x(13)& y4x(14)& y4x(15),
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y3 => y3x(0)& y3x(1)& y3x(2)& y3x(3)& y3x(4)& y3x(5)& y3x(6)& y3x(7)& y3x(8)& y3x(9)& y3x(10)& y3x(11)& y3x(12)& y3x(13)& y3x(14)& y3x(15),
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y2 => y2x(0)& y2x(1)& y2x(2)& y2x(3)& y2x(4)& y2x(5)& y2x(6)& y2x(7)& y2x(8)& y2x(9)& y2x(10)& y2x(11)& y2x(12)& y2x(13)& y2x(14)& y2x(15),
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y1 => y1x(0)& y1x(1)& y1x(2)& y1x(3)& y1x(4)& y1x(5)& y1x(6)& y1x(7)& y1x(8)& y1x(9)& y1x(10)& y1x(11)& y1x(12)& y1x(13)& y1x(14)& y1x(15),
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z6 => z6(0)& z6(1)& z6(2)& z6(3)& z6(4)& z6(5)& z6(6)& z6(7)& z6(8)& z6(9)& z6(10)& z6(11)& z6(12)& z6(13)& z6(14)& z6(15),
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z5 => z5(0)& z5(1)& z5(2)& z5(3)& z5(4)& z5(5)& z5(6)& z5(7)& z5(8)& z5(9)& z5(10)& z5(11)& z5(12)& z5(13)& z5(14)& z5(15),
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z4 => z4(0)& z4(1)& z4(2)& z4(3)& z4(4)& z4(5)& z4(6)& z4(7)& z4(8)& z4(9)& z4(10)& z4(11)& z4(12)& z4(13)& z4(14)& z4(15),
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z3 => z3(0)& z3(1)& z3(2)& z3(3)& z3(4)& z3(5)& z3(6)& z3(7)& z3(8)& z3(9)& z3(10)& z3(11)& z3(12)& z3(13)& z3(14)& z3(15),
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z2 => z2(0)& z2(1)& z2(2)& z2(3)& z2(4)& z2(5)& z2(6)& z2(7)& z2(8)& z2(9)& z2(10)& z2(11)& z2(12)& z2(13)& z2(14)& z2(15),
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z1 => z1(0)& z1(1)& z1(2)& z1(3)& z1(4)& z1(5)& z1(6)& z1(7)& z1(8)& z1(9)& z1(10)& z1(11)& z1(12)& z1(13)& z1(14)& z1(15),
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x4 => o_mux4(0)& o_mux4(1)& o_mux4(2)& o_mux4(3)& o_mux4(4)& o_mux4(5)& o_mux4(6)& o_mux4(7)& o_mux4(8)& o_mux4(9)& o_mux4(10)& o_mux4(11)& o_mux4(12)& o_mux4(13)& o_mux4(14)& o_mux4(15),
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x3 => o_mux3(0)& o_mux3(1)& o_mux3(2)& o_mux3(3)& o_mux3(4)& o_mux3(5)& o_mux3(6)& o_mux3(7)& o_mux3(8)& o_mux3(9)& o_mux3(10)& o_mux3(11)& o_mux3(12)& o_mux3(13)& o_mux3(14)& o_mux3(15),
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x2 => o_mux2(0)& o_mux2(1)& o_mux2(2)& o_mux2(3)& o_mux2(4)& o_mux2(5)& o_mux2(6)& o_mux2(7)& o_mux2(8)& o_mux2(9)& o_mux2(10)& o_mux2(11)& o_mux2(12)& o_mux2(13)& o_mux2(14)& o_mux2(15),
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x1 => o_mux1(0)& o_mux1(1)& o_mux1(2)& o_mux1(3)& o_mux1(4)& o_mux1(5)& o_mux1(6)& o_mux1(7)& o_mux1(8)& o_mux1(9)& o_mux1(10)& o_mux1(11)& o_mux1(12)& o_mux1(13)& o_mux1(14)& o_mux1(15),
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en => en(1)& en(2)& en(3)& en(4)& en(5)& en(6)& en(7));
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trans : out_trans_glopf
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PORT MAP (
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vss => vss,
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vdd => vdd,
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reset => reset,
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y4 => y4(0)& y4(1)& y4(2)& y4(3)& y4(4)& y4(5)& y4(6)& y4(7)& y4(8)& y4(9)& y4(10)& y4(11)& y4(12)& y4(13)& y4(14)& y4(15),
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y3 => y3(0)& y3(1)& y3(2)& y3(3)& y3(4)& y3(5)& y3(6)& y3(7)& y3(8)& y3(9)& y3(10)& y3(11)& y3(12)& y3(13)& y3(14)& y3(15),
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y2 => y2(0)& y2(1)& y2(2)& y2(3)& y2(4)& y2(5)& y2(6)& y2(7)& y2(8)& y2(9)& y2(10)& y2(11)& y2(12)& y2(13)& y2(14)& y2(15),
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y1 => y1(0)& y1(1)& y1(2)& y1(3)& y1(4)& y1(5)& y1(6)& y1(7)& y1(8)& y1(9)& y1(10)& y1(11)& y1(12)& y1(13)& y1(14)& y1(15),
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z4 => z49(0)& z49(1)& z49(2)& z49(3)& z49(4)& z49(5)& z49(6)& z49(7)& z49(8)& z49(9)& z49(10)& z49(11)& z49(12)& z49(13)& z49(14)& z49(15),
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z3 => z39(0)& z39(1)& z39(2)& z39(3)& z39(4)& z39(5)& z39(6)& z39(7)& z39(8)& z39(9)& z39(10)& z39(11)& z39(12)& z39(13)& z39(14)& z39(15),
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z2 => z29(0)& z29(1)& z29(2)& z29(3)& z29(4)& z29(5)& z29(6)& z29(7)& z29(8)& z29(9)& z29(10)& z29(11)& z29(12)& z29(13)& z29(14)& z29(15),
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z1 => z19(0)& z19(1)& z19(2)& z19(3)& z19(4)& z19(5)& z19(6)& z19(7)& z19(8)& z19(9)& z19(10)& z19(11)& z19(12)& z19(13)& z19(14)& z19(15),
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x4 => y4x(0)& y4x(1)& y4x(2)& y4x(3)& y4x(4)& y4x(5)& y4x(6)& y4x(7)& y4x(8)& y4x(9)& y4x(10)& y4x(11)& y4x(12)& y4x(13)& y4x(14)& y4x(15),
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x3 => y3x(0)& y3x(1)& y3x(2)& y3x(3)& y3x(4)& y3x(5)& y3x(6)& y3x(7)& y3x(8)& y3x(9)& y3x(10)& y3x(11)& y3x(12)& y3x(13)& y3x(14)& y3x(15),
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x2 => y2x(0)& y2x(1)& y2x(2)& y2x(3)& y2x(4)& y2x(5)& y2x(6)& y2x(7)& y2x(8)& y2x(9)& y2x(10)& y2x(11)& y2x(12)& y2x(13)& y2x(14)& y2x(15),
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x1 => y1x(0)& y1x(1)& y1x(2)& y1x(3)& y1x(4)& y1x(5)& y1x(6)& y1x(7)& y1x(8)& y1x(9)& y1x(10)& y1x(11)& y1x(12)& y1x(13)& y1x(14)& y1x(15),
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en => en_out);
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end VST;
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