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[/] [structural_vhdl/] [trunk/] [idea_machine/] [m16adder.vst] - Blame information for rev 2

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1 2 marta 
-- VHDL structural description generated from `m16adder`
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--              date : Sat Sep  8 00:50:46 2001
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-- Entity Declaration
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ENTITY m16adder IS
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  PORT (
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  a : in BIT_VECTOR (0 TO 15);  -- a
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  b : in BIT_VECTOR (0 TO 15);  -- b
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  s : out BIT_VECTOR (0 TO 15); -- s
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  vdd : in BIT; -- vdd
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  vss : in BIT  -- vss
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  );
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END m16adder;
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-- Architecture Declaration
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ARCHITECTURE VST OF m16adder IS
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  COMPONENT halfadder_glopf
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    port (
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    a : in BIT; -- a
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    b : in BIT; -- b
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    cout : out BIT;     -- cout
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    sout : out BIT;     -- sout
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  COMPONENT fulladder_glopg
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    port (
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    a : in BIT; -- a
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    b : in BIT; -- b
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    cin : in BIT;       -- cin
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    cout : out BIT;     -- cout
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    sout : out BIT;     -- sout
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  COMPONENT xr2_x1
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    port (
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    i0 : in BIT;        -- i0
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    i1 : in BIT;        -- i1
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    q : out BIT;        -- q
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  SIGNAL c_0 : BIT;     -- c 0
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  SIGNAL c_1 : BIT;     -- c 1
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  SIGNAL c_2 : BIT;     -- c 2
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  SIGNAL c_3 : BIT;     -- c 3
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  SIGNAL c_4 : BIT;     -- c 4
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  SIGNAL c_5 : BIT;     -- c 5
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  SIGNAL c_6 : BIT;     -- c 6
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  SIGNAL c_7 : BIT;     -- c 7
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  SIGNAL c_8 : BIT;     -- c 8
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  SIGNAL c_9 : BIT;     -- c 9
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  SIGNAL c_10 : BIT;    -- c 10
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  SIGNAL c_11 : BIT;    -- c 11
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  SIGNAL c_12 : BIT;    -- c 12
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  SIGNAL c_13 : BIT;    -- c 13
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  SIGNAL c_14 : BIT;    -- c 14
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  SIGNAL o_xr1 : BIT;   -- o_xr1
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BEGIN
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  ha : halfadder_glopf
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    sout => s(0),
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    cout => c_0,
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    b => b(0),
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    a => a(0));
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  fa1 : fulladder_glopg
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    sout => s(1),
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    cout => c_1,
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    cin => c_0,
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    b => b(1),
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    a => a(1));
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  fa2 : fulladder_glopg
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    sout => s(2),
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    cout => c_2,
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    cin => c_1,
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    b => b(2),
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    a => a(2));
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  fa3 : fulladder_glopg
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    sout => s(3),
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    cout => c_3,
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    cin => c_2,
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    b => b(3),
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    a => a(3));
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  fa4 : fulladder_glopg
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    sout => s(4),
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    cout => c_4,
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    cin => c_3,
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    b => b(4),
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    a => a(4));
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  fa5 : fulladder_glopg
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    sout => s(5),
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    cout => c_5,
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    cin => c_4,
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    b => b(5),
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    a => a(5));
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  fa6 : fulladder_glopg
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    sout => s(6),
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    cout => c_6,
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    cin => c_5,
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    b => b(6),
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    a => a(6));
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  fa7 : fulladder_glopg
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    sout => s(7),
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    cout => c_7,
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    cin => c_6,
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    b => b(7),
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    a => a(7));
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  fa8 : fulladder_glopg
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    sout => s(8),
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    cout => c_8,
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    cin => c_7,
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    b => b(8),
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    a => a(8));
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  fa9 : fulladder_glopg
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    sout => s(9),
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    cout => c_9,
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    cin => c_8,
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    b => b(9),
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    a => a(9));
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  fa10 : fulladder_glopg
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    sout => s(10),
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    cout => c_10,
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    cin => c_9,
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    b => b(10),
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    a => a(10));
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  fa11 : fulladder_glopg
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    sout => s(11),
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    cout => c_11,
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    cin => c_10,
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    b => b(11),
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    a => a(11));
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  fa12 : fulladder_glopg
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    sout => s(12),
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    cout => c_12,
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    cin => c_11,
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    b => b(12),
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    a => a(12));
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  fa13 : fulladder_glopg
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    sout => s(13),
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    cout => c_13,
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    cin => c_12,
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    b => b(13),
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    a => a(13));
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  fa14 : fulladder_glopg
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    sout => s(14),
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    cout => c_14,
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    cin => c_13,
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    b => b(14),
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    a => a(14));
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  xr1 : xr2_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => o_xr1,
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    i1 => b(15),
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    i0 => a(15));
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  xr2 : xr2_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => s(15),
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    i1 => c_14,
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    i0 => o_xr1);
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end VST;

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