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[/] [structural_vhdl/] [trunk/] [idea_machine/] [m16adder_glop.vst] - Blame information for rev 4

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Line No. Rev Author Line
1 2 marta 
-- VHDL structural description generated from `m16adder_glop`
2 
--              date : Tue Sep  4 19:54:37 2001
3 
 
4 
 
5 
-- Entity Declaration
6 
 
7 
ENTITY m16adder_glop IS
8 
  PORT (
9 
  a : in BIT_VECTOR (0 TO 15);  -- a
10 
  b : in BIT_VECTOR (0 TO 15);  -- b
11 
  s : out BIT_VECTOR (0 TO 15); -- s
12 
  vdd : in BIT; -- vdd
13 
  vss : in BIT  -- vss
14 
  );
15 
END m16adder_glop;
16 
 
17 
-- Architecture Declaration
18 
 
19 
ARCHITECTURE VST OF m16adder_glop IS
20 
  COMPONENT o2_x2
21 
    port (
22 
    i0 : in BIT;        -- i0
23 
    i1 : in BIT;        -- i1
24 
    q : out BIT;        -- q
25 
    vdd : in BIT;       -- vdd
26 
    vss : in BIT        -- vss
27 
    );
28 
  END COMPONENT;
29 
 
30 
  COMPONENT a2_x2
31 
    port (
32 
    i0 : in BIT;        -- i0
33 
    i1 : in BIT;        -- i1
34 
    q : out BIT;        -- q
35 
    vdd : in BIT;       -- vdd
36 
    vss : in BIT        -- vss
37 
    );
38 
  END COMPONENT;
39 
 
40 
  COMPONENT ao22_x2
41 
    port (
42 
    i0 : in BIT;        -- i0
43 
    i1 : in BIT;        -- i1
44 
    i2 : in BIT;        -- i2
45 
    q : out BIT;        -- q
46 
    vdd : in BIT;       -- vdd
47 
    vss : in BIT        -- vss
48 
    );
49 
  END COMPONENT;
50 
 
51 
  COMPONENT xr2_x1
52 
    port (
53 
    i0 : in BIT;        -- i0
54 
    i1 : in BIT;        -- i1
55 
    q : out BIT;        -- q
56 
    vdd : in BIT;       -- vdd
57 
    vss : in BIT        -- vss
58 
    );
59 
  END COMPONENT;
60 
 
61 
  SIGNAL c_0 : BIT;     -- c_0
62 
  SIGNAL c_1 : BIT;     -- c_1
63 
  SIGNAL fa1_auxsc1 : BIT;      -- fa1.auxsc1
64 
  SIGNAL fa1_auxsc4 : BIT;      -- fa1.auxsc4
65 
  SIGNAL fa1_auxsc2 : BIT;      -- fa1.auxsc2
66 
  SIGNAL c_2 : BIT;     -- c_2
67 
  SIGNAL fa2_auxsc1 : BIT;      -- fa2.auxsc1
68 
  SIGNAL fa2_auxsc4 : BIT;      -- fa2.auxsc4
69 
  SIGNAL fa2_auxsc2 : BIT;      -- fa2.auxsc2
70 
  SIGNAL c_3 : BIT;     -- c_3
71 
  SIGNAL fa3_auxsc1 : BIT;      -- fa3.auxsc1
72 
  SIGNAL fa3_auxsc4 : BIT;      -- fa3.auxsc4
73 
  SIGNAL fa3_auxsc2 : BIT;      -- fa3.auxsc2
74 
  SIGNAL c_4 : BIT;     -- c_4
75 
  SIGNAL fa4_auxsc1 : BIT;      -- fa4.auxsc1
76 
  SIGNAL fa4_auxsc4 : BIT;      -- fa4.auxsc4
77 
  SIGNAL fa4_auxsc2 : BIT;      -- fa4.auxsc2
78 
  SIGNAL c_5 : BIT;     -- c_5
79 
  SIGNAL fa5_auxsc1 : BIT;      -- fa5.auxsc1
80 
  SIGNAL fa5_auxsc4 : BIT;      -- fa5.auxsc4
81 
  SIGNAL fa5_auxsc2 : BIT;      -- fa5.auxsc2
82 
  SIGNAL c_6 : BIT;     -- c_6
83 
  SIGNAL fa6_auxsc1 : BIT;      -- fa6.auxsc1
84 
  SIGNAL fa6_auxsc4 : BIT;      -- fa6.auxsc4
85 
  SIGNAL fa6_auxsc2 : BIT;      -- fa6.auxsc2
86 
  SIGNAL c_7 : BIT;     -- c_7
87 
  SIGNAL fa7_auxsc1 : BIT;      -- fa7.auxsc1
88 
  SIGNAL fa7_auxsc4 : BIT;      -- fa7.auxsc4
89 
  SIGNAL fa7_auxsc2 : BIT;      -- fa7.auxsc2
90 
  SIGNAL c_8 : BIT;     -- c_8
91 
  SIGNAL fa8_auxsc1 : BIT;      -- fa8.auxsc1
92 
  SIGNAL fa8_auxsc4 : BIT;      -- fa8.auxsc4
93 
  SIGNAL fa8_auxsc2 : BIT;      -- fa8.auxsc2
94 
  SIGNAL c_9 : BIT;     -- c_9
95 
  SIGNAL fa9_auxsc1 : BIT;      -- fa9.auxsc1
96 
  SIGNAL fa9_auxsc4 : BIT;      -- fa9.auxsc4
97 
  SIGNAL fa9_auxsc2 : BIT;      -- fa9.auxsc2
98 
  SIGNAL c_10 : BIT;    -- c_10
99 
  SIGNAL fa10_auxsc1 : BIT;     -- fa10.auxsc1
100 
  SIGNAL fa10_auxsc4 : BIT;     -- fa10.auxsc4
101 
  SIGNAL fa10_auxsc2 : BIT;     -- fa10.auxsc2
102 
  SIGNAL c_11 : BIT;    -- c_11
103 
  SIGNAL fa11_auxsc1 : BIT;     -- fa11.auxsc1
104 
  SIGNAL fa11_auxsc4 : BIT;     -- fa11.auxsc4
105 
  SIGNAL fa11_auxsc2 : BIT;     -- fa11.auxsc2
106 
  SIGNAL c_12 : BIT;    -- c_12
107 
  SIGNAL fa12_auxsc1 : BIT;     -- fa12.auxsc1
108 
  SIGNAL fa12_auxsc4 : BIT;     -- fa12.auxsc4
109 
  SIGNAL fa12_auxsc2 : BIT;     -- fa12.auxsc2
110 
  SIGNAL c_13 : BIT;    -- c_13
111 
  SIGNAL fa13_auxsc1 : BIT;     -- fa13.auxsc1
112 
  SIGNAL fa13_auxsc4 : BIT;     -- fa13.auxsc4
113 
  SIGNAL fa13_auxsc2 : BIT;     -- fa13.auxsc2
114 
  SIGNAL c_14 : BIT;    -- c_14
115 
  SIGNAL fa14_auxsc1 : BIT;     -- fa14.auxsc1
116 
  SIGNAL fa14_auxsc4 : BIT;     -- fa14.auxsc4
117 
  SIGNAL fa14_auxsc2 : BIT;     -- fa14.auxsc2
118 
  SIGNAL o_xr1 : BIT;   -- o_xr1
119 
 
120 
BEGIN
121 
 
122 
  ha_sout : xr2_x1
123 
    PORT MAP (
124 
    vss => vss,
125 
    vdd => vdd,
126 
    q => s(0),
127 
    i1 => a(0),
128 
    i0 => b(0));
129 
  ha_cout : a2_x2
130 
    PORT MAP (
131 
    vss => vss,
132 
    vdd => vdd,
133 
    q => c_0,
134 
    i1 => a(0),
135 
    i0 => b(0));
136 
  fa1_sout : xr2_x1
137 
    PORT MAP (
138 
    vss => vss,
139 
    vdd => vdd,
140 
    q => s(1),
141 
    i1 => fa1_auxsc1,
142 
    i0 => c_0);
143 
  fa1_cout : o2_x2
144 
    PORT MAP (
145 
    vss => vss,
146 
    vdd => vdd,
147 
    q => c_1,
148 
    i1 => fa1_auxsc2,
149 
    i0 => fa1_auxsc4);
150 
  fa1_auxsc2 : a2_x2
151 
    PORT MAP (
152 
    vss => vss,
153 
    vdd => vdd,
154 
    q => fa1_auxsc2,
155 
    i1 => b(1),
156 
    i0 => c_0);
157 
  fa1_auxsc4 : ao22_x2
158 
    PORT MAP (
159 
    vss => vss,
160 
    vdd => vdd,
161 
    q => fa1_auxsc4,
162 
    i2 => a(1),
163 
    i1 => b(1),
164 
    i0 => c_0);
165 
  fa1_auxsc1 : xr2_x1
166 
    PORT MAP (
167 
    vss => vss,
168 
    vdd => vdd,
169 
    q => fa1_auxsc1,
170 
    i1 => a(1),
171 
    i0 => b(1));
172 
  fa2_sout : xr2_x1
173 
    PORT MAP (
174 
    vss => vss,
175 
    vdd => vdd,
176 
    q => s(2),
177 
    i1 => fa2_auxsc1,
178 
    i0 => c_1);
179 
  fa2_cout : o2_x2
180 
    PORT MAP (
181 
    vss => vss,
182 
    vdd => vdd,
183 
    q => c_2,
184 
    i1 => fa2_auxsc2,
185 
    i0 => fa2_auxsc4);
186 
  fa2_auxsc2 : a2_x2
187 
    PORT MAP (
188 
    vss => vss,
189 
    vdd => vdd,
190 
    q => fa2_auxsc2,
191 
    i1 => b(2),
192 
    i0 => c_1);
193 
  fa2_auxsc4 : ao22_x2
194 
    PORT MAP (
195 
    vss => vss,
196 
    vdd => vdd,
197 
    q => fa2_auxsc4,
198 
    i2 => a(2),
199 
    i1 => b(2),
200 
    i0 => c_1);
201 
  fa2_auxsc1 : xr2_x1
202 
    PORT MAP (
203 
    vss => vss,
204 
    vdd => vdd,
205 
    q => fa2_auxsc1,
206 
    i1 => a(2),
207 
    i0 => b(2));
208 
  fa3_sout : xr2_x1
209 
    PORT MAP (
210 
    vss => vss,
211 
    vdd => vdd,
212 
    q => s(3),
213 
    i1 => fa3_auxsc1,
214 
    i0 => c_2);
215 
  fa3_cout : o2_x2
216 
    PORT MAP (
217 
    vss => vss,
218 
    vdd => vdd,
219 
    q => c_3,
220 
    i1 => fa3_auxsc2,
221 
    i0 => fa3_auxsc4);
222 
  fa3_auxsc2 : a2_x2
223 
    PORT MAP (
224 
    vss => vss,
225 
    vdd => vdd,
226 
    q => fa3_auxsc2,
227 
    i1 => b(3),
228 
    i0 => c_2);
229 
  fa3_auxsc4 : ao22_x2
230 
    PORT MAP (
231 
    vss => vss,
232 
    vdd => vdd,
233 
    q => fa3_auxsc4,
234 
    i2 => a(3),
235 
    i1 => b(3),
236 
    i0 => c_2);
237 
  fa3_auxsc1 : xr2_x1
238 
    PORT MAP (
239 
    vss => vss,
240 
    vdd => vdd,
241 
    q => fa3_auxsc1,
242 
    i1 => a(3),
243 
    i0 => b(3));
244 
  fa4_sout : xr2_x1
245 
    PORT MAP (
246 
    vss => vss,
247 
    vdd => vdd,
248 
    q => s(4),
249 
    i1 => fa4_auxsc1,
250 
    i0 => c_3);
251 
  fa4_cout : o2_x2
252 
    PORT MAP (
253 
    vss => vss,
254 
    vdd => vdd,
255 
    q => c_4,
256 
    i1 => fa4_auxsc2,
257 
    i0 => fa4_auxsc4);
258 
  fa4_auxsc2 : a2_x2
259 
    PORT MAP (
260 
    vss => vss,
261 
    vdd => vdd,
262 
    q => fa4_auxsc2,
263 
    i1 => b(4),
264 
    i0 => c_3);
265 
  fa4_auxsc4 : ao22_x2
266 
    PORT MAP (
267 
    vss => vss,
268 
    vdd => vdd,
269 
    q => fa4_auxsc4,
270 
    i2 => a(4),
271 
    i1 => b(4),
272 
    i0 => c_3);
273 
  fa4_auxsc1 : xr2_x1
274 
    PORT MAP (
275 
    vss => vss,
276 
    vdd => vdd,
277 
    q => fa4_auxsc1,
278 
    i1 => a(4),
279 
    i0 => b(4));
280 
  fa5_sout : xr2_x1
281 
    PORT MAP (
282 
    vss => vss,
283 
    vdd => vdd,
284 
    q => s(5),
285 
    i1 => fa5_auxsc1,
286 
    i0 => c_4);
287 
  fa5_cout : o2_x2
288 
    PORT MAP (
289 
    vss => vss,
290 
    vdd => vdd,
291 
    q => c_5,
292 
    i1 => fa5_auxsc2,
293 
    i0 => fa5_auxsc4);
294 
  fa5_auxsc2 : a2_x2
295 
    PORT MAP (
296 
    vss => vss,
297 
    vdd => vdd,
298 
    q => fa5_auxsc2,
299 
    i1 => b(5),
300 
    i0 => c_4);
301 
  fa5_auxsc4 : ao22_x2
302 
    PORT MAP (
303 
    vss => vss,
304 
    vdd => vdd,
305 
    q => fa5_auxsc4,
306 
    i2 => a(5),
307 
    i1 => b(5),
308 
    i0 => c_4);
309 
  fa5_auxsc1 : xr2_x1
310 
    PORT MAP (
311 
    vss => vss,
312 
    vdd => vdd,
313 
    q => fa5_auxsc1,
314 
    i1 => a(5),
315 
    i0 => b(5));
316 
  fa6_sout : xr2_x1
317 
    PORT MAP (
318 
    vss => vss,
319 
    vdd => vdd,
320 
    q => s(6),
321 
    i1 => fa6_auxsc1,
322 
    i0 => c_5);
323 
  fa6_cout : o2_x2
324 
    PORT MAP (
325 
    vss => vss,
326 
    vdd => vdd,
327 
    q => c_6,
328 
    i1 => fa6_auxsc2,
329 
    i0 => fa6_auxsc4);
330 
  fa6_auxsc2 : a2_x2
331 
    PORT MAP (
332 
    vss => vss,
333 
    vdd => vdd,
334 
    q => fa6_auxsc2,
335 
    i1 => b(6),
336 
    i0 => c_5);
337 
  fa6_auxsc4 : ao22_x2
338 
    PORT MAP (
339 
    vss => vss,
340 
    vdd => vdd,
341 
    q => fa6_auxsc4,
342 
    i2 => a(6),
343 
    i1 => b(6),
344 
    i0 => c_5);
345 
  fa6_auxsc1 : xr2_x1
346 
    PORT MAP (
347 
    vss => vss,
348 
    vdd => vdd,
349 
    q => fa6_auxsc1,
350 
    i1 => a(6),
351 
    i0 => b(6));
352 
  fa7_sout : xr2_x1
353 
    PORT MAP (
354 
    vss => vss,
355 
    vdd => vdd,
356 
    q => s(7),
357 
    i1 => fa7_auxsc1,
358 
    i0 => c_6);
359 
  fa7_cout : o2_x2
360 
    PORT MAP (
361 
    vss => vss,
362 
    vdd => vdd,
363 
    q => c_7,
364 
    i1 => fa7_auxsc2,
365 
    i0 => fa7_auxsc4);
366 
  fa7_auxsc2 : a2_x2
367 
    PORT MAP (
368 
    vss => vss,
369 
    vdd => vdd,
370 
    q => fa7_auxsc2,
371 
    i1 => b(7),
372 
    i0 => c_6);
373 
  fa7_auxsc4 : ao22_x2
374 
    PORT MAP (
375 
    vss => vss,
376 
    vdd => vdd,
377 
    q => fa7_auxsc4,
378 
    i2 => a(7),
379 
    i1 => b(7),
380 
    i0 => c_6);
381 
  fa7_auxsc1 : xr2_x1
382 
    PORT MAP (
383 
    vss => vss,
384 
    vdd => vdd,
385 
    q => fa7_auxsc1,
386 
    i1 => a(7),
387 
    i0 => b(7));
388 
  fa8_sout : xr2_x1
389 
    PORT MAP (
390 
    vss => vss,
391 
    vdd => vdd,
392 
    q => s(8),
393 
    i1 => fa8_auxsc1,
394 
    i0 => c_7);
395 
  fa8_cout : o2_x2
396 
    PORT MAP (
397 
    vss => vss,
398 
    vdd => vdd,
399 
    q => c_8,
400 
    i1 => fa8_auxsc2,
401 
    i0 => fa8_auxsc4);
402 
  fa8_auxsc2 : a2_x2
403 
    PORT MAP (
404 
    vss => vss,
405 
    vdd => vdd,
406 
    q => fa8_auxsc2,
407 
    i1 => b(8),
408 
    i0 => c_7);
409 
  fa8_auxsc4 : ao22_x2
410 
    PORT MAP (
411 
    vss => vss,
412 
    vdd => vdd,
413 
    q => fa8_auxsc4,
414 
    i2 => a(8),
415 
    i1 => b(8),
416 
    i0 => c_7);
417 
  fa8_auxsc1 : xr2_x1
418 
    PORT MAP (
419 
    vss => vss,
420 
    vdd => vdd,
421 
    q => fa8_auxsc1,
422 
    i1 => a(8),
423 
    i0 => b(8));
424 
  fa9_sout : xr2_x1
425 
    PORT MAP (
426 
    vss => vss,
427 
    vdd => vdd,
428 
    q => s(9),
429 
    i1 => fa9_auxsc1,
430 
    i0 => c_8);
431 
  fa9_cout : o2_x2
432 
    PORT MAP (
433 
    vss => vss,
434 
    vdd => vdd,
435 
    q => c_9,
436 
    i1 => fa9_auxsc2,
437 
    i0 => fa9_auxsc4);
438 
  fa9_auxsc2 : a2_x2
439 
    PORT MAP (
440 
    vss => vss,
441 
    vdd => vdd,
442 
    q => fa9_auxsc2,
443 
    i1 => b(9),
444 
    i0 => c_8);
445 
  fa9_auxsc4 : ao22_x2
446 
    PORT MAP (
447 
    vss => vss,
448 
    vdd => vdd,
449 
    q => fa9_auxsc4,
450 
    i2 => a(9),
451 
    i1 => b(9),
452 
    i0 => c_8);
453 
  fa9_auxsc1 : xr2_x1
454 
    PORT MAP (
455 
    vss => vss,
456 
    vdd => vdd,
457 
    q => fa9_auxsc1,
458 
    i1 => a(9),
459 
    i0 => b(9));
460 
  fa10_sout : xr2_x1
461 
    PORT MAP (
462 
    vss => vss,
463 
    vdd => vdd,
464 
    q => s(10),
465 
    i1 => fa10_auxsc1,
466 
    i0 => c_9);
467 
  fa10_cout : o2_x2
468 
    PORT MAP (
469 
    vss => vss,
470 
    vdd => vdd,
471 
    q => c_10,
472 
    i1 => fa10_auxsc2,
473 
    i0 => fa10_auxsc4);
474 
  fa10_auxsc2 : a2_x2
475 
    PORT MAP (
476 
    vss => vss,
477 
    vdd => vdd,
478 
    q => fa10_auxsc2,
479 
    i1 => b(10),
480 
    i0 => c_9);
481 
  fa10_auxsc4 : ao22_x2
482 
    PORT MAP (
483 
    vss => vss,
484 
    vdd => vdd,
485 
    q => fa10_auxsc4,
486 
    i2 => a(10),
487 
    i1 => b(10),
488 
    i0 => c_9);
489 
  fa10_auxsc1 : xr2_x1
490 
    PORT MAP (
491 
    vss => vss,
492 
    vdd => vdd,
493 
    q => fa10_auxsc1,
494 
    i1 => a(10),
495 
    i0 => b(10));
496 
  fa11_sout : xr2_x1
497 
    PORT MAP (
498 
    vss => vss,
499 
    vdd => vdd,
500 
    q => s(11),
501 
    i1 => fa11_auxsc1,
502 
    i0 => c_10);
503 
  fa11_cout : o2_x2
504 
    PORT MAP (
505 
    vss => vss,
506 
    vdd => vdd,
507 
    q => c_11,
508 
    i1 => fa11_auxsc2,
509 
    i0 => fa11_auxsc4);
510 
  fa11_auxsc2 : a2_x2
511 
    PORT MAP (
512 
    vss => vss,
513 
    vdd => vdd,
514 
    q => fa11_auxsc2,
515 
    i1 => b(11),
516 
    i0 => c_10);
517 
  fa11_auxsc4 : ao22_x2
518 
    PORT MAP (
519 
    vss => vss,
520 
    vdd => vdd,
521 
    q => fa11_auxsc4,
522 
    i2 => a(11),
523 
    i1 => b(11),
524 
    i0 => c_10);
525 
  fa11_auxsc1 : xr2_x1
526 
    PORT MAP (
527 
    vss => vss,
528 
    vdd => vdd,
529 
    q => fa11_auxsc1,
530 
    i1 => a(11),
531 
    i0 => b(11));
532 
  fa12_sout : xr2_x1
533 
    PORT MAP (
534 
    vss => vss,
535 
    vdd => vdd,
536 
    q => s(12),
537 
    i1 => fa12_auxsc1,
538 
    i0 => c_11);
539 
  fa12_cout : o2_x2
540 
    PORT MAP (
541 
    vss => vss,
542 
    vdd => vdd,
543 
    q => c_12,
544 
    i1 => fa12_auxsc2,
545 
    i0 => fa12_auxsc4);
546 
  fa12_auxsc2 : a2_x2
547 
    PORT MAP (
548 
    vss => vss,
549 
    vdd => vdd,
550 
    q => fa12_auxsc2,
551 
    i1 => b(12),
552 
    i0 => c_11);
553 
  fa12_auxsc4 : ao22_x2
554 
    PORT MAP (
555 
    vss => vss,
556 
    vdd => vdd,
557 
    q => fa12_auxsc4,
558 
    i2 => a(12),
559 
    i1 => b(12),
560 
    i0 => c_11);
561 
  fa12_auxsc1 : xr2_x1
562 
    PORT MAP (
563 
    vss => vss,
564 
    vdd => vdd,
565 
    q => fa12_auxsc1,
566 
    i1 => a(12),
567 
    i0 => b(12));
568 
  fa13_sout : xr2_x1
569 
    PORT MAP (
570 
    vss => vss,
571 
    vdd => vdd,
572 
    q => s(13),
573 
    i1 => fa13_auxsc1,
574 
    i0 => c_12);
575 
  fa13_cout : o2_x2
576 
    PORT MAP (
577 
    vss => vss,
578 
    vdd => vdd,
579 
    q => c_13,
580 
    i1 => fa13_auxsc2,
581 
    i0 => fa13_auxsc4);
582 
  fa13_auxsc2 : a2_x2
583 
    PORT MAP (
584 
    vss => vss,
585 
    vdd => vdd,
586 
    q => fa13_auxsc2,
587 
    i1 => b(13),
588 
    i0 => c_12);
589 
  fa13_auxsc4 : ao22_x2
590 
    PORT MAP (
591 
    vss => vss,
592 
    vdd => vdd,
593 
    q => fa13_auxsc4,
594 
    i2 => a(13),
595 
    i1 => b(13),
596 
    i0 => c_12);
597 
  fa13_auxsc1 : xr2_x1
598 
    PORT MAP (
599 
    vss => vss,
600 
    vdd => vdd,
601 
    q => fa13_auxsc1,
602 
    i1 => a(13),
603 
    i0 => b(13));
604 
  fa14_sout : xr2_x1
605 
    PORT MAP (
606 
    vss => vss,
607 
    vdd => vdd,
608 
    q => s(14),
609 
    i1 => fa14_auxsc1,
610 
    i0 => c_13);
611 
  fa14_cout : o2_x2
612 
    PORT MAP (
613 
    vss => vss,
614 
    vdd => vdd,
615 
    q => c_14,
616 
    i1 => fa14_auxsc2,
617 
    i0 => fa14_auxsc4);
618 
  fa14_auxsc2 : a2_x2
619 
    PORT MAP (
620 
    vss => vss,
621 
    vdd => vdd,
622 
    q => fa14_auxsc2,
623 
    i1 => b(14),
624 
    i0 => c_13);
625 
  fa14_auxsc4 : ao22_x2
626 
    PORT MAP (
627 
    vss => vss,
628 
    vdd => vdd,
629 
    q => fa14_auxsc4,
630 
    i2 => a(14),
631 
    i1 => b(14),
632 
    i0 => c_13);
633 
  fa14_auxsc1 : xr2_x1
634 
    PORT MAP (
635 
    vss => vss,
636 
    vdd => vdd,
637 
    q => fa14_auxsc1,
638 
    i1 => a(14),
639 
    i0 => b(14));
640 
  xr1 : xr2_x1
641 
    PORT MAP (
642 
    vss => vss,
643 
    vdd => vdd,
644 
    q => o_xr1,
645 
    i1 => b(15),
646 
    i0 => a(15));
647 
  xr2 : xr2_x1
648 
    PORT MAP (
649 
    vss => vss,
650 
    vdd => vdd,
651 
    q => s(15),
652 
    i1 => c_14,
653 
    i0 => o_xr1);
654 
 
655 
end VST;

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