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[/] [structural_vhdl/] [trunk/] [idea_machine/] [m16adder_glopg.vst] - Blame information for rev 5

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Line No. Rev Author Line
1 2 marta 
-- VHDL structural description generated from `m16adder_glopg`
2 
--              date : Mon Sep 10 09:16:26 2001
3 
 
4 
 
5 
-- Entity Declaration
6 
 
7 
ENTITY m16adder_glopg IS
8 
  PORT (
9 
  a : in BIT_VECTOR (0 TO 15);  -- a
10 
  b : in BIT_VECTOR (0 TO 15);  -- b
11 
  s : out BIT_VECTOR (0 TO 15); -- s
12 
  vdd : in BIT; -- vdd
13 
  vss : in BIT  -- vss
14 
  );
15 
END m16adder_glopg;
16 
 
17 
-- Architecture Declaration
18 
 
19 
ARCHITECTURE VST OF m16adder_glopg IS
20 
  COMPONENT buf_x2
21 
    port (
22 
    i : in BIT; -- i
23 
    q : out BIT;        -- q
24 
    vdd : in BIT;       -- vdd
25 
    vss : in BIT        -- vss
26 
    );
27 
  END COMPONENT;
28 
 
29 
  COMPONENT o2_x2
30 
    port (
31 
    i0 : in BIT;        -- i0
32 
    i1 : in BIT;        -- i1
33 
    q : out BIT;        -- q
34 
    vdd : in BIT;       -- vdd
35 
    vss : in BIT        -- vss
36 
    );
37 
  END COMPONENT;
38 
 
39 
  COMPONENT a2_x2
40 
    port (
41 
    i0 : in BIT;        -- i0
42 
    i1 : in BIT;        -- i1
43 
    q : out BIT;        -- q
44 
    vdd : in BIT;       -- vdd
45 
    vss : in BIT        -- vss
46 
    );
47 
  END COMPONENT;
48 
 
49 
  COMPONENT ao22_x2
50 
    port (
51 
    i0 : in BIT;        -- i0
52 
    i1 : in BIT;        -- i1
53 
    i2 : in BIT;        -- i2
54 
    q : out BIT;        -- q
55 
    vdd : in BIT;       -- vdd
56 
    vss : in BIT        -- vss
57 
    );
58 
  END COMPONENT;
59 
 
60 
  COMPONENT xr2_x1
61 
    port (
62 
    i0 : in BIT;        -- i0
63 
    i1 : in BIT;        -- i1
64 
    q : out BIT;        -- q
65 
    vdd : in BIT;       -- vdd
66 
    vss : in BIT        -- vss
67 
    );
68 
  END COMPONENT;
69 
 
70 
  SIGNAL c_0 : BIT;     -- c_0
71 
  SIGNAL ha_netops8 : BIT;      -- ha.netops8
72 
  SIGNAL c_1 : BIT;     -- c_1
73 
  SIGNAL fa1_auxsc2 : BIT;      -- fa1.auxsc2
74 
  SIGNAL fa1_auxsc4 : BIT;      -- fa1.auxsc4
75 
  SIGNAL fa1_auxsc1 : BIT;      -- fa1.auxsc1
76 
  SIGNAL c_2 : BIT;     -- c_2
77 
  SIGNAL fa2_auxsc2 : BIT;      -- fa2.auxsc2
78 
  SIGNAL fa2_auxsc4 : BIT;      -- fa2.auxsc4
79 
  SIGNAL fa2_auxsc1 : BIT;      -- fa2.auxsc1
80 
  SIGNAL c_3 : BIT;     -- c_3
81 
  SIGNAL fa3_auxsc2 : BIT;      -- fa3.auxsc2
82 
  SIGNAL fa3_auxsc4 : BIT;      -- fa3.auxsc4
83 
  SIGNAL fa3_auxsc1 : BIT;      -- fa3.auxsc1
84 
  SIGNAL c_4 : BIT;     -- c_4
85 
  SIGNAL fa4_auxsc2 : BIT;      -- fa4.auxsc2
86 
  SIGNAL fa4_auxsc4 : BIT;      -- fa4.auxsc4
87 
  SIGNAL fa4_auxsc1 : BIT;      -- fa4.auxsc1
88 
  SIGNAL c_5 : BIT;     -- c_5
89 
  SIGNAL fa5_auxsc2 : BIT;      -- fa5.auxsc2
90 
  SIGNAL fa5_auxsc4 : BIT;      -- fa5.auxsc4
91 
  SIGNAL fa5_auxsc1 : BIT;      -- fa5.auxsc1
92 
  SIGNAL c_6 : BIT;     -- c_6
93 
  SIGNAL fa6_auxsc2 : BIT;      -- fa6.auxsc2
94 
  SIGNAL fa6_auxsc4 : BIT;      -- fa6.auxsc4
95 
  SIGNAL fa6_auxsc1 : BIT;      -- fa6.auxsc1
96 
  SIGNAL c_7 : BIT;     -- c_7
97 
  SIGNAL fa7_auxsc2 : BIT;      -- fa7.auxsc2
98 
  SIGNAL fa7_auxsc4 : BIT;      -- fa7.auxsc4
99 
  SIGNAL fa7_auxsc1 : BIT;      -- fa7.auxsc1
100 
  SIGNAL c_8 : BIT;     -- c_8
101 
  SIGNAL fa8_auxsc2 : BIT;      -- fa8.auxsc2
102 
  SIGNAL fa8_auxsc4 : BIT;      -- fa8.auxsc4
103 
  SIGNAL fa8_auxsc1 : BIT;      -- fa8.auxsc1
104 
  SIGNAL c_9 : BIT;     -- c_9
105 
  SIGNAL fa9_auxsc2 : BIT;      -- fa9.auxsc2
106 
  SIGNAL fa9_auxsc4 : BIT;      -- fa9.auxsc4
107 
  SIGNAL fa9_auxsc1 : BIT;      -- fa9.auxsc1
108 
  SIGNAL c_10 : BIT;    -- c_10
109 
  SIGNAL fa10_auxsc2 : BIT;     -- fa10.auxsc2
110 
  SIGNAL fa10_auxsc4 : BIT;     -- fa10.auxsc4
111 
  SIGNAL fa10_auxsc1 : BIT;     -- fa10.auxsc1
112 
  SIGNAL c_11 : BIT;    -- c_11
113 
  SIGNAL fa11_auxsc2 : BIT;     -- fa11.auxsc2
114 
  SIGNAL fa11_auxsc4 : BIT;     -- fa11.auxsc4
115 
  SIGNAL fa11_auxsc1 : BIT;     -- fa11.auxsc1
116 
  SIGNAL c_12 : BIT;    -- c_12
117 
  SIGNAL fa12_auxsc2 : BIT;     -- fa12.auxsc2
118 
  SIGNAL fa12_auxsc4 : BIT;     -- fa12.auxsc4
119 
  SIGNAL fa12_auxsc1 : BIT;     -- fa12.auxsc1
120 
  SIGNAL c_13 : BIT;    -- c_13
121 
  SIGNAL fa13_auxsc2 : BIT;     -- fa13.auxsc2
122 
  SIGNAL fa13_auxsc4 : BIT;     -- fa13.auxsc4
123 
  SIGNAL fa13_auxsc1 : BIT;     -- fa13.auxsc1
124 
  SIGNAL c_14 : BIT;    -- c_14
125 
  SIGNAL fa14_auxsc2 : BIT;     -- fa14.auxsc2
126 
  SIGNAL fa14_auxsc4 : BIT;     -- fa14.auxsc4
127 
  SIGNAL fa14_auxsc1 : BIT;     -- fa14.auxsc1
128 
  SIGNAL o_xr1 : BIT;   -- o_xr1
129 
 
130 
BEGIN
131 
 
132 
  ha_sout : xr2_x1
133 
    PORT MAP (
134 
    vss => vss,
135 
    vdd => vdd,
136 
    q => s(0),
137 
    i1 => ha_netops8,
138 
    i0 => b(0));
139 
  ha_cout : a2_x2
140 
    PORT MAP (
141 
    vss => vss,
142 
    vdd => vdd,
143 
    q => c_0,
144 
    i1 => ha_netops8,
145 
    i0 => b(0));
146 
  ha_netopi8 : buf_x2
147 
    PORT MAP (
148 
    vss => vss,
149 
    vdd => vdd,
150 
    q => ha_netops8,
151 
    i => a(0));
152 
  fa1_sout : xr2_x1
153 
    PORT MAP (
154 
    vss => vss,
155 
    vdd => vdd,
156 
    q => s(1),
157 
    i1 => fa1_auxsc1,
158 
    i0 => c_0);
159 
  fa1_cout : o2_x2
160 
    PORT MAP (
161 
    vss => vss,
162 
    vdd => vdd,
163 
    q => c_1,
164 
    i1 => fa1_auxsc2,
165 
    i0 => fa1_auxsc4);
166 
  fa1_auxsc2 : a2_x2
167 
    PORT MAP (
168 
    vss => vss,
169 
    vdd => vdd,
170 
    q => fa1_auxsc2,
171 
    i1 => a(1),
172 
    i0 => b(1));
173 
  fa1_auxsc4 : ao22_x2
174 
    PORT MAP (
175 
    vss => vss,
176 
    vdd => vdd,
177 
    q => fa1_auxsc4,
178 
    i2 => c_0,
179 
    i1 => a(1),
180 
    i0 => b(1));
181 
  fa1_auxsc1 : xr2_x1
182 
    PORT MAP (
183 
    vss => vss,
184 
    vdd => vdd,
185 
    q => fa1_auxsc1,
186 
    i1 => a(1),
187 
    i0 => b(1));
188 
  fa2_sout : xr2_x1
189 
    PORT MAP (
190 
    vss => vss,
191 
    vdd => vdd,
192 
    q => s(2),
193 
    i1 => fa2_auxsc1,
194 
    i0 => c_1);
195 
  fa2_cout : o2_x2
196 
    PORT MAP (
197 
    vss => vss,
198 
    vdd => vdd,
199 
    q => c_2,
200 
    i1 => fa2_auxsc2,
201 
    i0 => fa2_auxsc4);
202 
  fa2_auxsc2 : a2_x2
203 
    PORT MAP (
204 
    vss => vss,
205 
    vdd => vdd,
206 
    q => fa2_auxsc2,
207 
    i1 => a(2),
208 
    i0 => b(2));
209 
  fa2_auxsc4 : ao22_x2
210 
    PORT MAP (
211 
    vss => vss,
212 
    vdd => vdd,
213 
    q => fa2_auxsc4,
214 
    i2 => c_1,
215 
    i1 => a(2),
216 
    i0 => b(2));
217 
  fa2_auxsc1 : xr2_x1
218 
    PORT MAP (
219 
    vss => vss,
220 
    vdd => vdd,
221 
    q => fa2_auxsc1,
222 
    i1 => a(2),
223 
    i0 => b(2));
224 
  fa3_sout : xr2_x1
225 
    PORT MAP (
226 
    vss => vss,
227 
    vdd => vdd,
228 
    q => s(3),
229 
    i1 => fa3_auxsc1,
230 
    i0 => c_2);
231 
  fa3_cout : o2_x2
232 
    PORT MAP (
233 
    vss => vss,
234 
    vdd => vdd,
235 
    q => c_3,
236 
    i1 => fa3_auxsc2,
237 
    i0 => fa3_auxsc4);
238 
  fa3_auxsc2 : a2_x2
239 
    PORT MAP (
240 
    vss => vss,
241 
    vdd => vdd,
242 
    q => fa3_auxsc2,
243 
    i1 => a(3),
244 
    i0 => b(3));
245 
  fa3_auxsc4 : ao22_x2
246 
    PORT MAP (
247 
    vss => vss,
248 
    vdd => vdd,
249 
    q => fa3_auxsc4,
250 
    i2 => c_2,
251 
    i1 => a(3),
252 
    i0 => b(3));
253 
  fa3_auxsc1 : xr2_x1
254 
    PORT MAP (
255 
    vss => vss,
256 
    vdd => vdd,
257 
    q => fa3_auxsc1,
258 
    i1 => a(3),
259 
    i0 => b(3));
260 
  fa4_sout : xr2_x1
261 
    PORT MAP (
262 
    vss => vss,
263 
    vdd => vdd,
264 
    q => s(4),
265 
    i1 => fa4_auxsc1,
266 
    i0 => c_3);
267 
  fa4_cout : o2_x2
268 
    PORT MAP (
269 
    vss => vss,
270 
    vdd => vdd,
271 
    q => c_4,
272 
    i1 => fa4_auxsc2,
273 
    i0 => fa4_auxsc4);
274 
  fa4_auxsc2 : a2_x2
275 
    PORT MAP (
276 
    vss => vss,
277 
    vdd => vdd,
278 
    q => fa4_auxsc2,
279 
    i1 => a(4),
280 
    i0 => b(4));
281 
  fa4_auxsc4 : ao22_x2
282 
    PORT MAP (
283 
    vss => vss,
284 
    vdd => vdd,
285 
    q => fa4_auxsc4,
286 
    i2 => c_3,
287 
    i1 => a(4),
288 
    i0 => b(4));
289 
  fa4_auxsc1 : xr2_x1
290 
    PORT MAP (
291 
    vss => vss,
292 
    vdd => vdd,
293 
    q => fa4_auxsc1,
294 
    i1 => a(4),
295 
    i0 => b(4));
296 
  fa5_sout : xr2_x1
297 
    PORT MAP (
298 
    vss => vss,
299 
    vdd => vdd,
300 
    q => s(5),
301 
    i1 => fa5_auxsc1,
302 
    i0 => c_4);
303 
  fa5_cout : o2_x2
304 
    PORT MAP (
305 
    vss => vss,
306 
    vdd => vdd,
307 
    q => c_5,
308 
    i1 => fa5_auxsc2,
309 
    i0 => fa5_auxsc4);
310 
  fa5_auxsc2 : a2_x2
311 
    PORT MAP (
312 
    vss => vss,
313 
    vdd => vdd,
314 
    q => fa5_auxsc2,
315 
    i1 => a(5),
316 
    i0 => b(5));
317 
  fa5_auxsc4 : ao22_x2
318 
    PORT MAP (
319 
    vss => vss,
320 
    vdd => vdd,
321 
    q => fa5_auxsc4,
322 
    i2 => c_4,
323 
    i1 => a(5),
324 
    i0 => b(5));
325 
  fa5_auxsc1 : xr2_x1
326 
    PORT MAP (
327 
    vss => vss,
328 
    vdd => vdd,
329 
    q => fa5_auxsc1,
330 
    i1 => a(5),
331 
    i0 => b(5));
332 
  fa6_sout : xr2_x1
333 
    PORT MAP (
334 
    vss => vss,
335 
    vdd => vdd,
336 
    q => s(6),
337 
    i1 => fa6_auxsc1,
338 
    i0 => c_5);
339 
  fa6_cout : o2_x2
340 
    PORT MAP (
341 
    vss => vss,
342 
    vdd => vdd,
343 
    q => c_6,
344 
    i1 => fa6_auxsc2,
345 
    i0 => fa6_auxsc4);
346 
  fa6_auxsc2 : a2_x2
347 
    PORT MAP (
348 
    vss => vss,
349 
    vdd => vdd,
350 
    q => fa6_auxsc2,
351 
    i1 => a(6),
352 
    i0 => b(6));
353 
  fa6_auxsc4 : ao22_x2
354 
    PORT MAP (
355 
    vss => vss,
356 
    vdd => vdd,
357 
    q => fa6_auxsc4,
358 
    i2 => c_5,
359 
    i1 => a(6),
360 
    i0 => b(6));
361 
  fa6_auxsc1 : xr2_x1
362 
    PORT MAP (
363 
    vss => vss,
364 
    vdd => vdd,
365 
    q => fa6_auxsc1,
366 
    i1 => a(6),
367 
    i0 => b(6));
368 
  fa7_sout : xr2_x1
369 
    PORT MAP (
370 
    vss => vss,
371 
    vdd => vdd,
372 
    q => s(7),
373 
    i1 => fa7_auxsc1,
374 
    i0 => c_6);
375 
  fa7_cout : o2_x2
376 
    PORT MAP (
377 
    vss => vss,
378 
    vdd => vdd,
379 
    q => c_7,
380 
    i1 => fa7_auxsc2,
381 
    i0 => fa7_auxsc4);
382 
  fa7_auxsc2 : a2_x2
383 
    PORT MAP (
384 
    vss => vss,
385 
    vdd => vdd,
386 
    q => fa7_auxsc2,
387 
    i1 => a(7),
388 
    i0 => b(7));
389 
  fa7_auxsc4 : ao22_x2
390 
    PORT MAP (
391 
    vss => vss,
392 
    vdd => vdd,
393 
    q => fa7_auxsc4,
394 
    i2 => c_6,
395 
    i1 => a(7),
396 
    i0 => b(7));
397 
  fa7_auxsc1 : xr2_x1
398 
    PORT MAP (
399 
    vss => vss,
400 
    vdd => vdd,
401 
    q => fa7_auxsc1,
402 
    i1 => a(7),
403 
    i0 => b(7));
404 
  fa8_sout : xr2_x1
405 
    PORT MAP (
406 
    vss => vss,
407 
    vdd => vdd,
408 
    q => s(8),
409 
    i1 => fa8_auxsc1,
410 
    i0 => c_7);
411 
  fa8_cout : o2_x2
412 
    PORT MAP (
413 
    vss => vss,
414 
    vdd => vdd,
415 
    q => c_8,
416 
    i1 => fa8_auxsc2,
417 
    i0 => fa8_auxsc4);
418 
  fa8_auxsc2 : a2_x2
419 
    PORT MAP (
420 
    vss => vss,
421 
    vdd => vdd,
422 
    q => fa8_auxsc2,
423 
    i1 => a(8),
424 
    i0 => b(8));
425 
  fa8_auxsc4 : ao22_x2
426 
    PORT MAP (
427 
    vss => vss,
428 
    vdd => vdd,
429 
    q => fa8_auxsc4,
430 
    i2 => c_7,
431 
    i1 => a(8),
432 
    i0 => b(8));
433 
  fa8_auxsc1 : xr2_x1
434 
    PORT MAP (
435 
    vss => vss,
436 
    vdd => vdd,
437 
    q => fa8_auxsc1,
438 
    i1 => a(8),
439 
    i0 => b(8));
440 
  fa9_sout : xr2_x1
441 
    PORT MAP (
442 
    vss => vss,
443 
    vdd => vdd,
444 
    q => s(9),
445 
    i1 => fa9_auxsc1,
446 
    i0 => c_8);
447 
  fa9_cout : o2_x2
448 
    PORT MAP (
449 
    vss => vss,
450 
    vdd => vdd,
451 
    q => c_9,
452 
    i1 => fa9_auxsc2,
453 
    i0 => fa9_auxsc4);
454 
  fa9_auxsc2 : a2_x2
455 
    PORT MAP (
456 
    vss => vss,
457 
    vdd => vdd,
458 
    q => fa9_auxsc2,
459 
    i1 => a(9),
460 
    i0 => b(9));
461 
  fa9_auxsc4 : ao22_x2
462 
    PORT MAP (
463 
    vss => vss,
464 
    vdd => vdd,
465 
    q => fa9_auxsc4,
466 
    i2 => c_8,
467 
    i1 => a(9),
468 
    i0 => b(9));
469 
  fa9_auxsc1 : xr2_x1
470 
    PORT MAP (
471 
    vss => vss,
472 
    vdd => vdd,
473 
    q => fa9_auxsc1,
474 
    i1 => a(9),
475 
    i0 => b(9));
476 
  fa10_sout : xr2_x1
477 
    PORT MAP (
478 
    vss => vss,
479 
    vdd => vdd,
480 
    q => s(10),
481 
    i1 => fa10_auxsc1,
482 
    i0 => c_9);
483 
  fa10_cout : o2_x2
484 
    PORT MAP (
485 
    vss => vss,
486 
    vdd => vdd,
487 
    q => c_10,
488 
    i1 => fa10_auxsc2,
489 
    i0 => fa10_auxsc4);
490 
  fa10_auxsc2 : a2_x2
491 
    PORT MAP (
492 
    vss => vss,
493 
    vdd => vdd,
494 
    q => fa10_auxsc2,
495 
    i1 => a(10),
496 
    i0 => b(10));
497 
  fa10_auxsc4 : ao22_x2
498 
    PORT MAP (
499 
    vss => vss,
500 
    vdd => vdd,
501 
    q => fa10_auxsc4,
502 
    i2 => c_9,
503 
    i1 => a(10),
504 
    i0 => b(10));
505 
  fa10_auxsc1 : xr2_x1
506 
    PORT MAP (
507 
    vss => vss,
508 
    vdd => vdd,
509 
    q => fa10_auxsc1,
510 
    i1 => a(10),
511 
    i0 => b(10));
512 
  fa11_sout : xr2_x1
513 
    PORT MAP (
514 
    vss => vss,
515 
    vdd => vdd,
516 
    q => s(11),
517 
    i1 => fa11_auxsc1,
518 
    i0 => c_10);
519 
  fa11_cout : o2_x2
520 
    PORT MAP (
521 
    vss => vss,
522 
    vdd => vdd,
523 
    q => c_11,
524 
    i1 => fa11_auxsc2,
525 
    i0 => fa11_auxsc4);
526 
  fa11_auxsc2 : a2_x2
527 
    PORT MAP (
528 
    vss => vss,
529 
    vdd => vdd,
530 
    q => fa11_auxsc2,
531 
    i1 => a(11),
532 
    i0 => b(11));
533 
  fa11_auxsc4 : ao22_x2
534 
    PORT MAP (
535 
    vss => vss,
536 
    vdd => vdd,
537 
    q => fa11_auxsc4,
538 
    i2 => c_10,
539 
    i1 => a(11),
540 
    i0 => b(11));
541 
  fa11_auxsc1 : xr2_x1
542 
    PORT MAP (
543 
    vss => vss,
544 
    vdd => vdd,
545 
    q => fa11_auxsc1,
546 
    i1 => a(11),
547 
    i0 => b(11));
548 
  fa12_sout : xr2_x1
549 
    PORT MAP (
550 
    vss => vss,
551 
    vdd => vdd,
552 
    q => s(12),
553 
    i1 => fa12_auxsc1,
554 
    i0 => c_11);
555 
  fa12_cout : o2_x2
556 
    PORT MAP (
557 
    vss => vss,
558 
    vdd => vdd,
559 
    q => c_12,
560 
    i1 => fa12_auxsc2,
561 
    i0 => fa12_auxsc4);
562 
  fa12_auxsc2 : a2_x2
563 
    PORT MAP (
564 
    vss => vss,
565 
    vdd => vdd,
566 
    q => fa12_auxsc2,
567 
    i1 => a(12),
568 
    i0 => b(12));
569 
  fa12_auxsc4 : ao22_x2
570 
    PORT MAP (
571 
    vss => vss,
572 
    vdd => vdd,
573 
    q => fa12_auxsc4,
574 
    i2 => c_11,
575 
    i1 => a(12),
576 
    i0 => b(12));
577 
  fa12_auxsc1 : xr2_x1
578 
    PORT MAP (
579 
    vss => vss,
580 
    vdd => vdd,
581 
    q => fa12_auxsc1,
582 
    i1 => a(12),
583 
    i0 => b(12));
584 
  fa13_sout : xr2_x1
585 
    PORT MAP (
586 
    vss => vss,
587 
    vdd => vdd,
588 
    q => s(13),
589 
    i1 => fa13_auxsc1,
590 
    i0 => c_12);
591 
  fa13_cout : o2_x2
592 
    PORT MAP (
593 
    vss => vss,
594 
    vdd => vdd,
595 
    q => c_13,
596 
    i1 => fa13_auxsc2,
597 
    i0 => fa13_auxsc4);
598 
  fa13_auxsc2 : a2_x2
599 
    PORT MAP (
600 
    vss => vss,
601 
    vdd => vdd,
602 
    q => fa13_auxsc2,
603 
    i1 => a(13),
604 
    i0 => b(13));
605 
  fa13_auxsc4 : ao22_x2
606 
    PORT MAP (
607 
    vss => vss,
608 
    vdd => vdd,
609 
    q => fa13_auxsc4,
610 
    i2 => c_12,
611 
    i1 => a(13),
612 
    i0 => b(13));
613 
  fa13_auxsc1 : xr2_x1
614 
    PORT MAP (
615 
    vss => vss,
616 
    vdd => vdd,
617 
    q => fa13_auxsc1,
618 
    i1 => a(13),
619 
    i0 => b(13));
620 
  fa14_sout : xr2_x1
621 
    PORT MAP (
622 
    vss => vss,
623 
    vdd => vdd,
624 
    q => s(14),
625 
    i1 => fa14_auxsc1,
626 
    i0 => c_13);
627 
  fa14_cout : o2_x2
628 
    PORT MAP (
629 
    vss => vss,
630 
    vdd => vdd,
631 
    q => c_14,
632 
    i1 => fa14_auxsc2,
633 
    i0 => fa14_auxsc4);
634 
  fa14_auxsc2 : a2_x2
635 
    PORT MAP (
636 
    vss => vss,
637 
    vdd => vdd,
638 
    q => fa14_auxsc2,
639 
    i1 => a(14),
640 
    i0 => b(14));
641 
  fa14_auxsc4 : ao22_x2
642 
    PORT MAP (
643 
    vss => vss,
644 
    vdd => vdd,
645 
    q => fa14_auxsc4,
646 
    i2 => c_13,
647 
    i1 => a(14),
648 
    i0 => b(14));
649 
  fa14_auxsc1 : xr2_x1
650 
    PORT MAP (
651 
    vss => vss,
652 
    vdd => vdd,
653 
    q => fa14_auxsc1,
654 
    i1 => a(14),
655 
    i0 => b(14));
656 
  xr1 : xr2_x1
657 
    PORT MAP (
658 
    vss => vss,
659 
    vdd => vdd,
660 
    q => o_xr1,
661 
    i1 => b(15),
662 
    i0 => a(15));
663 
  xr2 : xr2_x1
664 
    PORT MAP (
665 
    vss => vss,
666 
    vdd => vdd,
667 
    q => s(15),
668 
    i1 => c_14,
669 
    i0 => o_xr1);
670 
 
671 
end VST;

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