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[/] [structural_vhdl/] [trunk/] [idea_machine/] [mux64_glopg.vst] - Blame information for rev 4

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1 2 marta 
-- VHDL structural description generated from `mux64_glopg`
2 
--              date : Sat Sep  8 00:12:22 2001
3 
 
4 
 
5 
-- Entity Declaration
6 
 
7 
ENTITY mux64_glopg IS
8 
  PORT (
9 
  a : in BIT_VECTOR (63 DOWNTO 0);      -- a
10 
  b : in BIT_VECTOR (63 DOWNTO 0);      -- b
11 
  sel : in BIT; -- sel
12 
  c : out BIT_VECTOR (63 DOWNTO 0);     -- c
13 
  vdd : in BIT; -- vdd
14 
  vss : in BIT  -- vss
15 
  );
16 
END mux64_glopg;
17 
 
18 
-- Architecture Declaration
19 
 
20 
ARCHITECTURE VST OF mux64_glopg IS
21 
  COMPONENT nao22_x1
22 
    port (
23 
    i0 : in BIT;        -- i0
24 
    i1 : in BIT;        -- i1
25 
    i2 : in BIT;        -- i2
26 
    nq : out BIT;       -- nq
27 
    vdd : in BIT;       -- vdd
28 
    vss : in BIT        -- vss
29 
    );
30 
  END COMPONENT;
31 
 
32 
  COMPONENT na2_x1
33 
    port (
34 
    i0 : in BIT;        -- i0
35 
    i1 : in BIT;        -- i1
36 
    nq : out BIT;       -- nq
37 
    vdd : in BIT;       -- vdd
38 
    vss : in BIT        -- vss
39 
    );
40 
  END COMPONENT;
41 
 
42 
  COMPONENT inv_x1
43 
    port (
44 
    i : in BIT; -- i
45 
    nq : out BIT;       -- nq
46 
    vdd : in BIT;       -- vdd
47 
    vss : in BIT        -- vss
48 
    );
49 
  END COMPONENT;
50 
 
51 
  SIGNAL auxsc320 : BIT;        -- auxsc320
52 
  SIGNAL auxsc319 : BIT;        -- auxsc319
53 
  SIGNAL auxsc315 : BIT;        -- auxsc315
54 
  SIGNAL auxsc314 : BIT;        -- auxsc314
55 
  SIGNAL auxsc310 : BIT;        -- auxsc310
56 
  SIGNAL auxsc309 : BIT;        -- auxsc309
57 
  SIGNAL auxsc305 : BIT;        -- auxsc305
58 
  SIGNAL auxsc304 : BIT;        -- auxsc304
59 
  SIGNAL auxsc300 : BIT;        -- auxsc300
60 
  SIGNAL auxsc299 : BIT;        -- auxsc299
61 
  SIGNAL auxsc295 : BIT;        -- auxsc295
62 
  SIGNAL auxsc294 : BIT;        -- auxsc294
63 
  SIGNAL auxsc290 : BIT;        -- auxsc290
64 
  SIGNAL auxsc289 : BIT;        -- auxsc289
65 
  SIGNAL auxsc285 : BIT;        -- auxsc285
66 
  SIGNAL auxsc284 : BIT;        -- auxsc284
67 
  SIGNAL auxsc280 : BIT;        -- auxsc280
68 
  SIGNAL auxsc279 : BIT;        -- auxsc279
69 
  SIGNAL auxsc275 : BIT;        -- auxsc275
70 
  SIGNAL auxsc274 : BIT;        -- auxsc274
71 
  SIGNAL auxsc270 : BIT;        -- auxsc270
72 
  SIGNAL auxsc269 : BIT;        -- auxsc269
73 
  SIGNAL auxsc265 : BIT;        -- auxsc265
74 
  SIGNAL auxsc264 : BIT;        -- auxsc264
75 
  SIGNAL auxsc260 : BIT;        -- auxsc260
76 
  SIGNAL auxsc259 : BIT;        -- auxsc259
77 
  SIGNAL auxsc255 : BIT;        -- auxsc255
78 
  SIGNAL auxsc254 : BIT;        -- auxsc254
79 
  SIGNAL auxsc250 : BIT;        -- auxsc250
80 
  SIGNAL auxsc249 : BIT;        -- auxsc249
81 
  SIGNAL auxsc245 : BIT;        -- auxsc245
82 
  SIGNAL auxsc244 : BIT;        -- auxsc244
83 
  SIGNAL auxsc240 : BIT;        -- auxsc240
84 
  SIGNAL auxsc239 : BIT;        -- auxsc239
85 
  SIGNAL auxsc235 : BIT;        -- auxsc235
86 
  SIGNAL auxsc234 : BIT;        -- auxsc234
87 
  SIGNAL auxsc230 : BIT;        -- auxsc230
88 
  SIGNAL auxsc229 : BIT;        -- auxsc229
89 
  SIGNAL auxsc225 : BIT;        -- auxsc225
90 
  SIGNAL auxsc224 : BIT;        -- auxsc224
91 
  SIGNAL auxsc220 : BIT;        -- auxsc220
92 
  SIGNAL auxsc219 : BIT;        -- auxsc219
93 
  SIGNAL auxsc215 : BIT;        -- auxsc215
94 
  SIGNAL auxsc214 : BIT;        -- auxsc214
95 
  SIGNAL auxsc210 : BIT;        -- auxsc210
96 
  SIGNAL auxsc209 : BIT;        -- auxsc209
97 
  SIGNAL auxsc205 : BIT;        -- auxsc205
98 
  SIGNAL auxsc204 : BIT;        -- auxsc204
99 
  SIGNAL auxsc200 : BIT;        -- auxsc200
100 
  SIGNAL auxsc199 : BIT;        -- auxsc199
101 
  SIGNAL auxsc195 : BIT;        -- auxsc195
102 
  SIGNAL auxsc194 : BIT;        -- auxsc194
103 
  SIGNAL auxsc190 : BIT;        -- auxsc190
104 
  SIGNAL auxsc189 : BIT;        -- auxsc189
105 
  SIGNAL auxsc185 : BIT;        -- auxsc185
106 
  SIGNAL auxsc184 : BIT;        -- auxsc184
107 
  SIGNAL auxsc180 : BIT;        -- auxsc180
108 
  SIGNAL auxsc179 : BIT;        -- auxsc179
109 
  SIGNAL auxsc175 : BIT;        -- auxsc175
110 
  SIGNAL auxsc174 : BIT;        -- auxsc174
111 
  SIGNAL auxsc170 : BIT;        -- auxsc170
112 
  SIGNAL auxsc169 : BIT;        -- auxsc169
113 
  SIGNAL auxsc165 : BIT;        -- auxsc165
114 
  SIGNAL auxsc164 : BIT;        -- auxsc164
115 
  SIGNAL auxsc160 : BIT;        -- auxsc160
116 
  SIGNAL auxsc159 : BIT;        -- auxsc159
117 
  SIGNAL auxsc155 : BIT;        -- auxsc155
118 
  SIGNAL auxsc154 : BIT;        -- auxsc154
119 
  SIGNAL auxsc150 : BIT;        -- auxsc150
120 
  SIGNAL auxsc149 : BIT;        -- auxsc149
121 
  SIGNAL auxsc145 : BIT;        -- auxsc145
122 
  SIGNAL auxsc144 : BIT;        -- auxsc144
123 
  SIGNAL auxsc140 : BIT;        -- auxsc140
124 
  SIGNAL auxsc139 : BIT;        -- auxsc139
125 
  SIGNAL auxsc135 : BIT;        -- auxsc135
126 
  SIGNAL auxsc134 : BIT;        -- auxsc134
127 
  SIGNAL auxsc130 : BIT;        -- auxsc130
128 
  SIGNAL auxsc129 : BIT;        -- auxsc129
129 
  SIGNAL auxsc125 : BIT;        -- auxsc125
130 
  SIGNAL auxsc124 : BIT;        -- auxsc124
131 
  SIGNAL auxsc120 : BIT;        -- auxsc120
132 
  SIGNAL auxsc119 : BIT;        -- auxsc119
133 
  SIGNAL auxsc115 : BIT;        -- auxsc115
134 
  SIGNAL auxsc114 : BIT;        -- auxsc114
135 
  SIGNAL auxsc110 : BIT;        -- auxsc110
136 
  SIGNAL auxsc109 : BIT;        -- auxsc109
137 
  SIGNAL auxsc105 : BIT;        -- auxsc105
138 
  SIGNAL auxsc104 : BIT;        -- auxsc104
139 
  SIGNAL auxsc100 : BIT;        -- auxsc100
140 
  SIGNAL auxsc99 : BIT; -- auxsc99
141 
  SIGNAL auxsc95 : BIT; -- auxsc95
142 
  SIGNAL auxsc94 : BIT; -- auxsc94
143 
  SIGNAL auxsc90 : BIT; -- auxsc90
144 
  SIGNAL auxsc89 : BIT; -- auxsc89
145 
  SIGNAL auxsc85 : BIT; -- auxsc85
146 
  SIGNAL auxsc84 : BIT; -- auxsc84
147 
  SIGNAL auxsc80 : BIT; -- auxsc80
148 
  SIGNAL auxsc79 : BIT; -- auxsc79
149 
  SIGNAL auxsc75 : BIT; -- auxsc75
150 
  SIGNAL auxsc74 : BIT; -- auxsc74
151 
  SIGNAL auxsc70 : BIT; -- auxsc70
152 
  SIGNAL auxsc69 : BIT; -- auxsc69
153 
  SIGNAL auxsc65 : BIT; -- auxsc65
154 
  SIGNAL auxsc64 : BIT; -- auxsc64
155 
  SIGNAL auxsc60 : BIT; -- auxsc60
156 
  SIGNAL auxsc59 : BIT; -- auxsc59
157 
  SIGNAL auxsc55 : BIT; -- auxsc55
158 
  SIGNAL auxsc54 : BIT; -- auxsc54
159 
  SIGNAL auxsc50 : BIT; -- auxsc50
160 
  SIGNAL auxsc49 : BIT; -- auxsc49
161 
  SIGNAL auxsc45 : BIT; -- auxsc45
162 
  SIGNAL auxsc44 : BIT; -- auxsc44
163 
  SIGNAL auxsc40 : BIT; -- auxsc40
164 
  SIGNAL auxsc39 : BIT; -- auxsc39
165 
  SIGNAL auxsc35 : BIT; -- auxsc35
166 
  SIGNAL auxsc34 : BIT; -- auxsc34
167 
  SIGNAL auxsc30 : BIT; -- auxsc30
168 
  SIGNAL auxsc29 : BIT; -- auxsc29
169 
  SIGNAL auxsc25 : BIT; -- auxsc25
170 
  SIGNAL auxsc24 : BIT; -- auxsc24
171 
  SIGNAL auxsc20 : BIT; -- auxsc20
172 
  SIGNAL auxsc19 : BIT; -- auxsc19
173 
  SIGNAL auxsc15 : BIT; -- auxsc15
174 
  SIGNAL auxsc14 : BIT; -- auxsc14
175 
  SIGNAL auxsc10 : BIT; -- auxsc10
176 
  SIGNAL auxsc9 : BIT;  -- auxsc9
177 
  SIGNAL auxsc5 : BIT;  -- auxsc5
178 
  SIGNAL auxsc4 : BIT;  -- auxsc4
179 
 
180 
BEGIN
181 
 
182 
  c_0 : nao22_x1
183 
    PORT MAP (
184 
    vss => vss,
185 
    vdd => vdd,
186 
    nq => c(0),
187 
    i2 => auxsc5,
188 
    i1 => auxsc4,
189 
    i0 => sel);
190 
  c_1 : nao22_x1
191 
    PORT MAP (
192 
    vss => vss,
193 
    vdd => vdd,
194 
    nq => c(1),
195 
    i2 => auxsc10,
196 
    i1 => auxsc9,
197 
    i0 => sel);
198 
  c_2 : nao22_x1
199 
    PORT MAP (
200 
    vss => vss,
201 
    vdd => vdd,
202 
    nq => c(2),
203 
    i2 => auxsc15,
204 
    i1 => auxsc14,
205 
    i0 => sel);
206 
  c_3 : nao22_x1
207 
    PORT MAP (
208 
    vss => vss,
209 
    vdd => vdd,
210 
    nq => c(3),
211 
    i2 => auxsc20,
212 
    i1 => auxsc19,
213 
    i0 => sel);
214 
  c_4 : nao22_x1
215 
    PORT MAP (
216 
    vss => vss,
217 
    vdd => vdd,
218 
    nq => c(4),
219 
    i2 => auxsc25,
220 
    i1 => auxsc24,
221 
    i0 => sel);
222 
  c_5 : nao22_x1
223 
    PORT MAP (
224 
    vss => vss,
225 
    vdd => vdd,
226 
    nq => c(5),
227 
    i2 => auxsc30,
228 
    i1 => auxsc29,
229 
    i0 => sel);
230 
  c_6 : nao22_x1
231 
    PORT MAP (
232 
    vss => vss,
233 
    vdd => vdd,
234 
    nq => c(6),
235 
    i2 => auxsc35,
236 
    i1 => auxsc34,
237 
    i0 => sel);
238 
  c_7 : nao22_x1
239 
    PORT MAP (
240 
    vss => vss,
241 
    vdd => vdd,
242 
    nq => c(7),
243 
    i2 => auxsc40,
244 
    i1 => auxsc39,
245 
    i0 => sel);
246 
  c_8 : nao22_x1
247 
    PORT MAP (
248 
    vss => vss,
249 
    vdd => vdd,
250 
    nq => c(8),
251 
    i2 => auxsc45,
252 
    i1 => auxsc44,
253 
    i0 => sel);
254 
  c_9 : nao22_x1
255 
    PORT MAP (
256 
    vss => vss,
257 
    vdd => vdd,
258 
    nq => c(9),
259 
    i2 => auxsc50,
260 
    i1 => auxsc49,
261 
    i0 => sel);
262 
  c_10 : nao22_x1
263 
    PORT MAP (
264 
    vss => vss,
265 
    vdd => vdd,
266 
    nq => c(10),
267 
    i2 => auxsc55,
268 
    i1 => auxsc54,
269 
    i0 => sel);
270 
  c_11 : nao22_x1
271 
    PORT MAP (
272 
    vss => vss,
273 
    vdd => vdd,
274 
    nq => c(11),
275 
    i2 => auxsc60,
276 
    i1 => auxsc59,
277 
    i0 => sel);
278 
  c_12 : nao22_x1
279 
    PORT MAP (
280 
    vss => vss,
281 
    vdd => vdd,
282 
    nq => c(12),
283 
    i2 => auxsc65,
284 
    i1 => auxsc64,
285 
    i0 => sel);
286 
  c_13 : nao22_x1
287 
    PORT MAP (
288 
    vss => vss,
289 
    vdd => vdd,
290 
    nq => c(13),
291 
    i2 => auxsc70,
292 
    i1 => auxsc69,
293 
    i0 => sel);
294 
  c_14 : nao22_x1
295 
    PORT MAP (
296 
    vss => vss,
297 
    vdd => vdd,
298 
    nq => c(14),
299 
    i2 => auxsc75,
300 
    i1 => auxsc74,
301 
    i0 => sel);
302 
  c_15 : nao22_x1
303 
    PORT MAP (
304 
    vss => vss,
305 
    vdd => vdd,
306 
    nq => c(15),
307 
    i2 => auxsc80,
308 
    i1 => auxsc79,
309 
    i0 => sel);
310 
  c_16 : nao22_x1
311 
    PORT MAP (
312 
    vss => vss,
313 
    vdd => vdd,
314 
    nq => c(16),
315 
    i2 => auxsc85,
316 
    i1 => auxsc84,
317 
    i0 => sel);
318 
  c_17 : nao22_x1
319 
    PORT MAP (
320 
    vss => vss,
321 
    vdd => vdd,
322 
    nq => c(17),
323 
    i2 => auxsc90,
324 
    i1 => auxsc89,
325 
    i0 => sel);
326 
  c_18 : nao22_x1
327 
    PORT MAP (
328 
    vss => vss,
329 
    vdd => vdd,
330 
    nq => c(18),
331 
    i2 => auxsc95,
332 
    i1 => auxsc94,
333 
    i0 => sel);
334 
  c_19 : nao22_x1
335 
    PORT MAP (
336 
    vss => vss,
337 
    vdd => vdd,
338 
    nq => c(19),
339 
    i2 => auxsc100,
340 
    i1 => auxsc99,
341 
    i0 => sel);
342 
  c_20 : nao22_x1
343 
    PORT MAP (
344 
    vss => vss,
345 
    vdd => vdd,
346 
    nq => c(20),
347 
    i2 => auxsc105,
348 
    i1 => auxsc104,
349 
    i0 => sel);
350 
  c_21 : nao22_x1
351 
    PORT MAP (
352 
    vss => vss,
353 
    vdd => vdd,
354 
    nq => c(21),
355 
    i2 => auxsc110,
356 
    i1 => auxsc109,
357 
    i0 => sel);
358 
  c_22 : nao22_x1
359 
    PORT MAP (
360 
    vss => vss,
361 
    vdd => vdd,
362 
    nq => c(22),
363 
    i2 => auxsc115,
364 
    i1 => auxsc114,
365 
    i0 => sel);
366 
  c_23 : nao22_x1
367 
    PORT MAP (
368 
    vss => vss,
369 
    vdd => vdd,
370 
    nq => c(23),
371 
    i2 => auxsc120,
372 
    i1 => auxsc119,
373 
    i0 => sel);
374 
  c_24 : nao22_x1
375 
    PORT MAP (
376 
    vss => vss,
377 
    vdd => vdd,
378 
    nq => c(24),
379 
    i2 => auxsc125,
380 
    i1 => auxsc124,
381 
    i0 => sel);
382 
  c_25 : nao22_x1
383 
    PORT MAP (
384 
    vss => vss,
385 
    vdd => vdd,
386 
    nq => c(25),
387 
    i2 => auxsc130,
388 
    i1 => auxsc129,
389 
    i0 => sel);
390 
  c_26 : nao22_x1
391 
    PORT MAP (
392 
    vss => vss,
393 
    vdd => vdd,
394 
    nq => c(26),
395 
    i2 => auxsc135,
396 
    i1 => auxsc134,
397 
    i0 => sel);
398 
  c_27 : nao22_x1
399 
    PORT MAP (
400 
    vss => vss,
401 
    vdd => vdd,
402 
    nq => c(27),
403 
    i2 => auxsc140,
404 
    i1 => auxsc139,
405 
    i0 => sel);
406 
  c_28 : nao22_x1
407 
    PORT MAP (
408 
    vss => vss,
409 
    vdd => vdd,
410 
    nq => c(28),
411 
    i2 => auxsc145,
412 
    i1 => auxsc144,
413 
    i0 => sel);
414 
  c_29 : nao22_x1
415 
    PORT MAP (
416 
    vss => vss,
417 
    vdd => vdd,
418 
    nq => c(29),
419 
    i2 => auxsc150,
420 
    i1 => auxsc149,
421 
    i0 => sel);
422 
  c_30 : nao22_x1
423 
    PORT MAP (
424 
    vss => vss,
425 
    vdd => vdd,
426 
    nq => c(30),
427 
    i2 => auxsc155,
428 
    i1 => auxsc154,
429 
    i0 => sel);
430 
  c_31 : nao22_x1
431 
    PORT MAP (
432 
    vss => vss,
433 
    vdd => vdd,
434 
    nq => c(31),
435 
    i2 => auxsc160,
436 
    i1 => auxsc159,
437 
    i0 => sel);
438 
  c_32 : nao22_x1
439 
    PORT MAP (
440 
    vss => vss,
441 
    vdd => vdd,
442 
    nq => c(32),
443 
    i2 => auxsc165,
444 
    i1 => auxsc164,
445 
    i0 => sel);
446 
  c_33 : nao22_x1
447 
    PORT MAP (
448 
    vss => vss,
449 
    vdd => vdd,
450 
    nq => c(33),
451 
    i2 => auxsc170,
452 
    i1 => auxsc169,
453 
    i0 => sel);
454 
  c_34 : nao22_x1
455 
    PORT MAP (
456 
    vss => vss,
457 
    vdd => vdd,
458 
    nq => c(34),
459 
    i2 => auxsc175,
460 
    i1 => auxsc174,
461 
    i0 => sel);
462 
  c_35 : nao22_x1
463 
    PORT MAP (
464 
    vss => vss,
465 
    vdd => vdd,
466 
    nq => c(35),
467 
    i2 => auxsc180,
468 
    i1 => auxsc179,
469 
    i0 => sel);
470 
  c_36 : nao22_x1
471 
    PORT MAP (
472 
    vss => vss,
473 
    vdd => vdd,
474 
    nq => c(36),
475 
    i2 => auxsc185,
476 
    i1 => auxsc184,
477 
    i0 => sel);
478 
  c_37 : nao22_x1
479 
    PORT MAP (
480 
    vss => vss,
481 
    vdd => vdd,
482 
    nq => c(37),
483 
    i2 => auxsc190,
484 
    i1 => auxsc189,
485 
    i0 => sel);
486 
  c_38 : nao22_x1
487 
    PORT MAP (
488 
    vss => vss,
489 
    vdd => vdd,
490 
    nq => c(38),
491 
    i2 => auxsc195,
492 
    i1 => auxsc194,
493 
    i0 => sel);
494 
  c_39 : nao22_x1
495 
    PORT MAP (
496 
    vss => vss,
497 
    vdd => vdd,
498 
    nq => c(39),
499 
    i2 => auxsc200,
500 
    i1 => auxsc199,
501 
    i0 => sel);
502 
  c_40 : nao22_x1
503 
    PORT MAP (
504 
    vss => vss,
505 
    vdd => vdd,
506 
    nq => c(40),
507 
    i2 => auxsc205,
508 
    i1 => auxsc204,
509 
    i0 => sel);
510 
  c_41 : nao22_x1
511 
    PORT MAP (
512 
    vss => vss,
513 
    vdd => vdd,
514 
    nq => c(41),
515 
    i2 => auxsc210,
516 
    i1 => auxsc209,
517 
    i0 => sel);
518 
  c_42 : nao22_x1
519 
    PORT MAP (
520 
    vss => vss,
521 
    vdd => vdd,
522 
    nq => c(42),
523 
    i2 => auxsc215,
524 
    i1 => auxsc214,
525 
    i0 => sel);
526 
  c_43 : nao22_x1
527 
    PORT MAP (
528 
    vss => vss,
529 
    vdd => vdd,
530 
    nq => c(43),
531 
    i2 => auxsc220,
532 
    i1 => auxsc219,
533 
    i0 => sel);
534 
  c_44 : nao22_x1
535 
    PORT MAP (
536 
    vss => vss,
537 
    vdd => vdd,
538 
    nq => c(44),
539 
    i2 => auxsc225,
540 
    i1 => auxsc224,
541 
    i0 => sel);
542 
  c_45 : nao22_x1
543 
    PORT MAP (
544 
    vss => vss,
545 
    vdd => vdd,
546 
    nq => c(45),
547 
    i2 => auxsc230,
548 
    i1 => auxsc229,
549 
    i0 => sel);
550 
  c_46 : nao22_x1
551 
    PORT MAP (
552 
    vss => vss,
553 
    vdd => vdd,
554 
    nq => c(46),
555 
    i2 => auxsc235,
556 
    i1 => auxsc234,
557 
    i0 => sel);
558 
  c_47 : nao22_x1
559 
    PORT MAP (
560 
    vss => vss,
561 
    vdd => vdd,
562 
    nq => c(47),
563 
    i2 => auxsc240,
564 
    i1 => auxsc239,
565 
    i0 => sel);
566 
  c_48 : nao22_x1
567 
    PORT MAP (
568 
    vss => vss,
569 
    vdd => vdd,
570 
    nq => c(48),
571 
    i2 => auxsc245,
572 
    i1 => auxsc244,
573 
    i0 => sel);
574 
  c_49 : nao22_x1
575 
    PORT MAP (
576 
    vss => vss,
577 
    vdd => vdd,
578 
    nq => c(49),
579 
    i2 => auxsc250,
580 
    i1 => auxsc249,
581 
    i0 => sel);
582 
  c_50 : nao22_x1
583 
    PORT MAP (
584 
    vss => vss,
585 
    vdd => vdd,
586 
    nq => c(50),
587 
    i2 => auxsc255,
588 
    i1 => auxsc254,
589 
    i0 => sel);
590 
  c_51 : nao22_x1
591 
    PORT MAP (
592 
    vss => vss,
593 
    vdd => vdd,
594 
    nq => c(51),
595 
    i2 => auxsc260,
596 
    i1 => auxsc259,
597 
    i0 => sel);
598 
  c_52 : nao22_x1
599 
    PORT MAP (
600 
    vss => vss,
601 
    vdd => vdd,
602 
    nq => c(52),
603 
    i2 => auxsc265,
604 
    i1 => auxsc264,
605 
    i0 => sel);
606 
  c_53 : nao22_x1
607 
    PORT MAP (
608 
    vss => vss,
609 
    vdd => vdd,
610 
    nq => c(53),
611 
    i2 => auxsc270,
612 
    i1 => auxsc269,
613 
    i0 => sel);
614 
  c_54 : nao22_x1
615 
    PORT MAP (
616 
    vss => vss,
617 
    vdd => vdd,
618 
    nq => c(54),
619 
    i2 => auxsc275,
620 
    i1 => auxsc274,
621 
    i0 => sel);
622 
  c_55 : nao22_x1
623 
    PORT MAP (
624 
    vss => vss,
625 
    vdd => vdd,
626 
    nq => c(55),
627 
    i2 => auxsc280,
628 
    i1 => auxsc279,
629 
    i0 => sel);
630 
  c_56 : nao22_x1
631 
    PORT MAP (
632 
    vss => vss,
633 
    vdd => vdd,
634 
    nq => c(56),
635 
    i2 => auxsc285,
636 
    i1 => auxsc284,
637 
    i0 => sel);
638 
  c_57 : nao22_x1
639 
    PORT MAP (
640 
    vss => vss,
641 
    vdd => vdd,
642 
    nq => c(57),
643 
    i2 => auxsc290,
644 
    i1 => auxsc289,
645 
    i0 => sel);
646 
  c_58 : nao22_x1
647 
    PORT MAP (
648 
    vss => vss,
649 
    vdd => vdd,
650 
    nq => c(58),
651 
    i2 => auxsc295,
652 
    i1 => auxsc294,
653 
    i0 => sel);
654 
  c_59 : nao22_x1
655 
    PORT MAP (
656 
    vss => vss,
657 
    vdd => vdd,
658 
    nq => c(59),
659 
    i2 => auxsc300,
660 
    i1 => auxsc299,
661 
    i0 => sel);
662 
  c_60 : nao22_x1
663 
    PORT MAP (
664 
    vss => vss,
665 
    vdd => vdd,
666 
    nq => c(60),
667 
    i2 => auxsc305,
668 
    i1 => auxsc304,
669 
    i0 => sel);
670 
  c_61 : nao22_x1
671 
    PORT MAP (
672 
    vss => vss,
673 
    vdd => vdd,
674 
    nq => c(61),
675 
    i2 => auxsc310,
676 
    i1 => auxsc309,
677 
    i0 => sel);
678 
  c_62 : nao22_x1
679 
    PORT MAP (
680 
    vss => vss,
681 
    vdd => vdd,
682 
    nq => c(62),
683 
    i2 => auxsc315,
684 
    i1 => auxsc314,
685 
    i0 => sel);
686 
  c_63 : nao22_x1
687 
    PORT MAP (
688 
    vss => vss,
689 
    vdd => vdd,
690 
    nq => c(63),
691 
    i2 => auxsc320,
692 
    i1 => auxsc319,
693 
    i0 => sel);
694 
  auxsc320 : na2_x1
695 
    PORT MAP (
696 
    vss => vss,
697 
    vdd => vdd,
698 
    nq => auxsc320,
699 
    i1 => b(63),
700 
    i0 => sel);
701 
  auxsc319 : inv_x1
702 
    PORT MAP (
703 
    vss => vss,
704 
    vdd => vdd,
705 
    nq => auxsc319,
706 
    i => a(63));
707 
  auxsc315 : na2_x1
708 
    PORT MAP (
709 
    vss => vss,
710 
    vdd => vdd,
711 
    nq => auxsc315,
712 
    i1 => b(62),
713 
    i0 => sel);
714 
  auxsc314 : inv_x1
715 
    PORT MAP (
716 
    vss => vss,
717 
    vdd => vdd,
718 
    nq => auxsc314,
719 
    i => a(62));
720 
  auxsc310 : na2_x1
721 
    PORT MAP (
722 
    vss => vss,
723 
    vdd => vdd,
724 
    nq => auxsc310,
725 
    i1 => b(61),
726 
    i0 => sel);
727 
  auxsc309 : inv_x1
728 
    PORT MAP (
729 
    vss => vss,
730 
    vdd => vdd,
731 
    nq => auxsc309,
732 
    i => a(61));
733 
  auxsc305 : na2_x1
734 
    PORT MAP (
735 
    vss => vss,
736 
    vdd => vdd,
737 
    nq => auxsc305,
738 
    i1 => b(60),
739 
    i0 => sel);
740 
  auxsc304 : inv_x1
741 
    PORT MAP (
742 
    vss => vss,
743 
    vdd => vdd,
744 
    nq => auxsc304,
745 
    i => a(60));
746 
  auxsc300 : na2_x1
747 
    PORT MAP (
748 
    vss => vss,
749 
    vdd => vdd,
750 
    nq => auxsc300,
751 
    i1 => b(59),
752 
    i0 => sel);
753 
  auxsc299 : inv_x1
754 
    PORT MAP (
755 
    vss => vss,
756 
    vdd => vdd,
757 
    nq => auxsc299,
758 
    i => a(59));
759 
  auxsc295 : na2_x1
760 
    PORT MAP (
761 
    vss => vss,
762 
    vdd => vdd,
763 
    nq => auxsc295,
764 
    i1 => b(58),
765 
    i0 => sel);
766 
  auxsc294 : inv_x1
767 
    PORT MAP (
768 
    vss => vss,
769 
    vdd => vdd,
770 
    nq => auxsc294,
771 
    i => a(58));
772 
  auxsc290 : na2_x1
773 
    PORT MAP (
774 
    vss => vss,
775 
    vdd => vdd,
776 
    nq => auxsc290,
777 
    i1 => b(57),
778 
    i0 => sel);
779 
  auxsc289 : inv_x1
780 
    PORT MAP (
781 
    vss => vss,
782 
    vdd => vdd,
783 
    nq => auxsc289,
784 
    i => a(57));
785 
  auxsc285 : na2_x1
786 
    PORT MAP (
787 
    vss => vss,
788 
    vdd => vdd,
789 
    nq => auxsc285,
790 
    i1 => b(56),
791 
    i0 => sel);
792 
  auxsc284 : inv_x1
793 
    PORT MAP (
794 
    vss => vss,
795 
    vdd => vdd,
796 
    nq => auxsc284,
797 
    i => a(56));
798 
  auxsc280 : na2_x1
799 
    PORT MAP (
800 
    vss => vss,
801 
    vdd => vdd,
802 
    nq => auxsc280,
803 
    i1 => b(55),
804 
    i0 => sel);
805 
  auxsc279 : inv_x1
806 
    PORT MAP (
807 
    vss => vss,
808 
    vdd => vdd,
809 
    nq => auxsc279,
810 
    i => a(55));
811 
  auxsc275 : na2_x1
812 
    PORT MAP (
813 
    vss => vss,
814 
    vdd => vdd,
815 
    nq => auxsc275,
816 
    i1 => b(54),
817 
    i0 => sel);
818 
  auxsc274 : inv_x1
819 
    PORT MAP (
820 
    vss => vss,
821 
    vdd => vdd,
822 
    nq => auxsc274,
823 
    i => a(54));
824 
  auxsc270 : na2_x1
825 
    PORT MAP (
826 
    vss => vss,
827 
    vdd => vdd,
828 
    nq => auxsc270,
829 
    i1 => b(53),
830 
    i0 => sel);
831 
  auxsc269 : inv_x1
832 
    PORT MAP (
833 
    vss => vss,
834 
    vdd => vdd,
835 
    nq => auxsc269,
836 
    i => a(53));
837 
  auxsc265 : na2_x1
838 
    PORT MAP (
839 
    vss => vss,
840 
    vdd => vdd,
841 
    nq => auxsc265,
842 
    i1 => b(52),
843 
    i0 => sel);
844 
  auxsc264 : inv_x1
845 
    PORT MAP (
846 
    vss => vss,
847 
    vdd => vdd,
848 
    nq => auxsc264,
849 
    i => a(52));
850 
  auxsc260 : na2_x1
851 
    PORT MAP (
852 
    vss => vss,
853 
    vdd => vdd,
854 
    nq => auxsc260,
855 
    i1 => b(51),
856 
    i0 => sel);
857 
  auxsc259 : inv_x1
858 
    PORT MAP (
859 
    vss => vss,
860 
    vdd => vdd,
861 
    nq => auxsc259,
862 
    i => a(51));
863 
  auxsc255 : na2_x1
864 
    PORT MAP (
865 
    vss => vss,
866 
    vdd => vdd,
867 
    nq => auxsc255,
868 
    i1 => b(50),
869 
    i0 => sel);
870 
  auxsc254 : inv_x1
871 
    PORT MAP (
872 
    vss => vss,
873 
    vdd => vdd,
874 
    nq => auxsc254,
875 
    i => a(50));
876 
  auxsc250 : na2_x1
877 
    PORT MAP (
878 
    vss => vss,
879 
    vdd => vdd,
880 
    nq => auxsc250,
881 
    i1 => b(49),
882 
    i0 => sel);
883 
  auxsc249 : inv_x1
884 
    PORT MAP (
885 
    vss => vss,
886 
    vdd => vdd,
887 
    nq => auxsc249,
888 
    i => a(49));
889 
  auxsc245 : na2_x1
890 
    PORT MAP (
891 
    vss => vss,
892 
    vdd => vdd,
893 
    nq => auxsc245,
894 
    i1 => b(48),
895 
    i0 => sel);
896 
  auxsc244 : inv_x1
897 
    PORT MAP (
898 
    vss => vss,
899 
    vdd => vdd,
900 
    nq => auxsc244,
901 
    i => a(48));
902 
  auxsc240 : na2_x1
903 
    PORT MAP (
904 
    vss => vss,
905 
    vdd => vdd,
906 
    nq => auxsc240,
907 
    i1 => b(47),
908 
    i0 => sel);
909 
  auxsc239 : inv_x1
910 
    PORT MAP (
911 
    vss => vss,
912 
    vdd => vdd,
913 
    nq => auxsc239,
914 
    i => a(47));
915 
  auxsc235 : na2_x1
916 
    PORT MAP (
917 
    vss => vss,
918 
    vdd => vdd,
919 
    nq => auxsc235,
920 
    i1 => b(46),
921 
    i0 => sel);
922 
  auxsc234 : inv_x1
923 
    PORT MAP (
924 
    vss => vss,
925 
    vdd => vdd,
926 
    nq => auxsc234,
927 
    i => a(46));
928 
  auxsc230 : na2_x1
929 
    PORT MAP (
930 
    vss => vss,
931 
    vdd => vdd,
932 
    nq => auxsc230,
933 
    i1 => b(45),
934 
    i0 => sel);
935 
  auxsc229 : inv_x1
936 
    PORT MAP (
937 
    vss => vss,
938 
    vdd => vdd,
939 
    nq => auxsc229,
940 
    i => a(45));
941 
  auxsc225 : na2_x1
942 
    PORT MAP (
943 
    vss => vss,
944 
    vdd => vdd,
945 
    nq => auxsc225,
946 
    i1 => b(44),
947 
    i0 => sel);
948 
  auxsc224 : inv_x1
949 
    PORT MAP (
950 
    vss => vss,
951 
    vdd => vdd,
952 
    nq => auxsc224,
953 
    i => a(44));
954 
  auxsc220 : na2_x1
955 
    PORT MAP (
956 
    vss => vss,
957 
    vdd => vdd,
958 
    nq => auxsc220,
959 
    i1 => b(43),
960 
    i0 => sel);
961 
  auxsc219 : inv_x1
962 
    PORT MAP (
963 
    vss => vss,
964 
    vdd => vdd,
965 
    nq => auxsc219,
966 
    i => a(43));
967 
  auxsc215 : na2_x1
968 
    PORT MAP (
969 
    vss => vss,
970 
    vdd => vdd,
971 
    nq => auxsc215,
972 
    i1 => b(42),
973 
    i0 => sel);
974 
  auxsc214 : inv_x1
975 
    PORT MAP (
976 
    vss => vss,
977 
    vdd => vdd,
978 
    nq => auxsc214,
979 
    i => a(42));
980 
  auxsc210 : na2_x1
981 
    PORT MAP (
982 
    vss => vss,
983 
    vdd => vdd,
984 
    nq => auxsc210,
985 
    i1 => b(41),
986 
    i0 => sel);
987 
  auxsc209 : inv_x1
988 
    PORT MAP (
989 
    vss => vss,
990 
    vdd => vdd,
991 
    nq => auxsc209,
992 
    i => a(41));
993 
  auxsc205 : na2_x1
994 
    PORT MAP (
995 
    vss => vss,
996 
    vdd => vdd,
997 
    nq => auxsc205,
998 
    i1 => b(40),
999 
    i0 => sel);
1000 
  auxsc204 : inv_x1
1001 
    PORT MAP (
1002 
    vss => vss,
1003 
    vdd => vdd,
1004 
    nq => auxsc204,
1005 
    i => a(40));
1006 
  auxsc200 : na2_x1
1007 
    PORT MAP (
1008 
    vss => vss,
1009 
    vdd => vdd,
1010 
    nq => auxsc200,
1011 
    i1 => b(39),
1012 
    i0 => sel);
1013 
  auxsc199 : inv_x1
1014 
    PORT MAP (
1015 
    vss => vss,
1016 
    vdd => vdd,
1017 
    nq => auxsc199,
1018 
    i => a(39));
1019 
  auxsc195 : na2_x1
1020 
    PORT MAP (
1021 
    vss => vss,
1022 
    vdd => vdd,
1023 
    nq => auxsc195,
1024 
    i1 => b(38),
1025 
    i0 => sel);
1026 
  auxsc194 : inv_x1
1027 
    PORT MAP (
1028 
    vss => vss,
1029 
    vdd => vdd,
1030 
    nq => auxsc194,
1031 
    i => a(38));
1032 
  auxsc190 : na2_x1
1033 
    PORT MAP (
1034 
    vss => vss,
1035 
    vdd => vdd,
1036 
    nq => auxsc190,
1037 
    i1 => b(37),
1038 
    i0 => sel);
1039 
  auxsc189 : inv_x1
1040 
    PORT MAP (
1041 
    vss => vss,
1042 
    vdd => vdd,
1043 
    nq => auxsc189,
1044 
    i => a(37));
1045 
  auxsc185 : na2_x1
1046 
    PORT MAP (
1047 
    vss => vss,
1048 
    vdd => vdd,
1049 
    nq => auxsc185,
1050 
    i1 => b(36),
1051 
    i0 => sel);
1052 
  auxsc184 : inv_x1
1053 
    PORT MAP (
1054 
    vss => vss,
1055 
    vdd => vdd,
1056 
    nq => auxsc184,
1057 
    i => a(36));
1058 
  auxsc180 : na2_x1
1059 
    PORT MAP (
1060 
    vss => vss,
1061 
    vdd => vdd,
1062 
    nq => auxsc180,
1063 
    i1 => b(35),
1064 
    i0 => sel);
1065 
  auxsc179 : inv_x1
1066 
    PORT MAP (
1067 
    vss => vss,
1068 
    vdd => vdd,
1069 
    nq => auxsc179,
1070 
    i => a(35));
1071 
  auxsc175 : na2_x1
1072 
    PORT MAP (
1073 
    vss => vss,
1074 
    vdd => vdd,
1075 
    nq => auxsc175,
1076 
    i1 => b(34),
1077 
    i0 => sel);
1078 
  auxsc174 : inv_x1
1079 
    PORT MAP (
1080 
    vss => vss,
1081 
    vdd => vdd,
1082 
    nq => auxsc174,
1083 
    i => a(34));
1084 
  auxsc170 : na2_x1
1085 
    PORT MAP (
1086 
    vss => vss,
1087 
    vdd => vdd,
1088 
    nq => auxsc170,
1089 
    i1 => b(33),
1090 
    i0 => sel);
1091 
  auxsc169 : inv_x1
1092 
    PORT MAP (
1093 
    vss => vss,
1094 
    vdd => vdd,
1095 
    nq => auxsc169,
1096 
    i => a(33));
1097 
  auxsc165 : na2_x1
1098 
    PORT MAP (
1099 
    vss => vss,
1100 
    vdd => vdd,
1101 
    nq => auxsc165,
1102 
    i1 => b(32),
1103 
    i0 => sel);
1104 
  auxsc164 : inv_x1
1105 
    PORT MAP (
1106 
    vss => vss,
1107 
    vdd => vdd,
1108 
    nq => auxsc164,
1109 
    i => a(32));
1110 
  auxsc160 : na2_x1
1111 
    PORT MAP (
1112 
    vss => vss,
1113 
    vdd => vdd,
1114 
    nq => auxsc160,
1115 
    i1 => b(31),
1116 
    i0 => sel);
1117 
  auxsc159 : inv_x1
1118 
    PORT MAP (
1119 
    vss => vss,
1120 
    vdd => vdd,
1121 
    nq => auxsc159,
1122 
    i => a(31));
1123 
  auxsc155 : na2_x1
1124 
    PORT MAP (
1125 
    vss => vss,
1126 
    vdd => vdd,
1127 
    nq => auxsc155,
1128 
    i1 => b(30),
1129 
    i0 => sel);
1130 
  auxsc154 : inv_x1
1131 
    PORT MAP (
1132 
    vss => vss,
1133 
    vdd => vdd,
1134 
    nq => auxsc154,
1135 
    i => a(30));
1136 
  auxsc150 : na2_x1
1137 
    PORT MAP (
1138 
    vss => vss,
1139 
    vdd => vdd,
1140 
    nq => auxsc150,
1141 
    i1 => b(29),
1142 
    i0 => sel);
1143 
  auxsc149 : inv_x1
1144 
    PORT MAP (
1145 
    vss => vss,
1146 
    vdd => vdd,
1147 
    nq => auxsc149,
1148 
    i => a(29));
1149 
  auxsc145 : na2_x1
1150 
    PORT MAP (
1151 
    vss => vss,
1152 
    vdd => vdd,
1153 
    nq => auxsc145,
1154 
    i1 => b(28),
1155 
    i0 => sel);
1156 
  auxsc144 : inv_x1
1157 
    PORT MAP (
1158 
    vss => vss,
1159 
    vdd => vdd,
1160 
    nq => auxsc144,
1161 
    i => a(28));
1162 
  auxsc140 : na2_x1
1163 
    PORT MAP (
1164 
    vss => vss,
1165 
    vdd => vdd,
1166 
    nq => auxsc140,
1167 
    i1 => b(27),
1168 
    i0 => sel);
1169 
  auxsc139 : inv_x1
1170 
    PORT MAP (
1171 
    vss => vss,
1172 
    vdd => vdd,
1173 
    nq => auxsc139,
1174 
    i => a(27));
1175 
  auxsc135 : na2_x1
1176 
    PORT MAP (
1177 
    vss => vss,
1178 
    vdd => vdd,
1179 
    nq => auxsc135,
1180 
    i1 => b(26),
1181 
    i0 => sel);
1182 
  auxsc134 : inv_x1
1183 
    PORT MAP (
1184 
    vss => vss,
1185 
    vdd => vdd,
1186 
    nq => auxsc134,
1187 
    i => a(26));
1188 
  auxsc130 : na2_x1
1189 
    PORT MAP (
1190 
    vss => vss,
1191 
    vdd => vdd,
1192 
    nq => auxsc130,
1193 
    i1 => b(25),
1194 
    i0 => sel);
1195 
  auxsc129 : inv_x1
1196 
    PORT MAP (
1197 
    vss => vss,
1198 
    vdd => vdd,
1199 
    nq => auxsc129,
1200 
    i => a(25));
1201 
  auxsc125 : na2_x1
1202 
    PORT MAP (
1203 
    vss => vss,
1204 
    vdd => vdd,
1205 
    nq => auxsc125,
1206 
    i1 => b(24),
1207 
    i0 => sel);
1208 
  auxsc124 : inv_x1
1209 
    PORT MAP (
1210 
    vss => vss,
1211 
    vdd => vdd,
1212 
    nq => auxsc124,
1213 
    i => a(24));
1214 
  auxsc120 : na2_x1
1215 
    PORT MAP (
1216 
    vss => vss,
1217 
    vdd => vdd,
1218 
    nq => auxsc120,
1219 
    i1 => b(23),
1220 
    i0 => sel);
1221 
  auxsc119 : inv_x1
1222 
    PORT MAP (
1223 
    vss => vss,
1224 
    vdd => vdd,
1225 
    nq => auxsc119,
1226 
    i => a(23));
1227 
  auxsc115 : na2_x1
1228 
    PORT MAP (
1229 
    vss => vss,
1230 
    vdd => vdd,
1231 
    nq => auxsc115,
1232 
    i1 => b(22),
1233 
    i0 => sel);
1234 
  auxsc114 : inv_x1
1235 
    PORT MAP (
1236 
    vss => vss,
1237 
    vdd => vdd,
1238 
    nq => auxsc114,
1239 
    i => a(22));
1240 
  auxsc110 : na2_x1
1241 
    PORT MAP (
1242 
    vss => vss,
1243 
    vdd => vdd,
1244 
    nq => auxsc110,
1245 
    i1 => b(21),
1246 
    i0 => sel);
1247 
  auxsc109 : inv_x1
1248 
    PORT MAP (
1249 
    vss => vss,
1250 
    vdd => vdd,
1251 
    nq => auxsc109,
1252 
    i => a(21));
1253 
  auxsc105 : na2_x1
1254 
    PORT MAP (
1255 
    vss => vss,
1256 
    vdd => vdd,
1257 
    nq => auxsc105,
1258 
    i1 => b(20),
1259 
    i0 => sel);
1260 
  auxsc104 : inv_x1
1261 
    PORT MAP (
1262 
    vss => vss,
1263 
    vdd => vdd,
1264 
    nq => auxsc104,
1265 
    i => a(20));
1266 
  auxsc100 : na2_x1
1267 
    PORT MAP (
1268 
    vss => vss,
1269 
    vdd => vdd,
1270 
    nq => auxsc100,
1271 
    i1 => b(19),
1272 
    i0 => sel);
1273 
  auxsc99 : inv_x1
1274 
    PORT MAP (
1275 
    vss => vss,
1276 
    vdd => vdd,
1277 
    nq => auxsc99,
1278 
    i => a(19));
1279 
  auxsc95 : na2_x1
1280 
    PORT MAP (
1281 
    vss => vss,
1282 
    vdd => vdd,
1283 
    nq => auxsc95,
1284 
    i1 => b(18),
1285 
    i0 => sel);
1286 
  auxsc94 : inv_x1
1287 
    PORT MAP (
1288 
    vss => vss,
1289 
    vdd => vdd,
1290 
    nq => auxsc94,
1291 
    i => a(18));
1292 
  auxsc90 : na2_x1
1293 
    PORT MAP (
1294 
    vss => vss,
1295 
    vdd => vdd,
1296 
    nq => auxsc90,
1297 
    i1 => b(17),
1298 
    i0 => sel);
1299 
  auxsc89 : inv_x1
1300 
    PORT MAP (
1301 
    vss => vss,
1302 
    vdd => vdd,
1303 
    nq => auxsc89,
1304 
    i => a(17));
1305 
  auxsc85 : na2_x1
1306 
    PORT MAP (
1307 
    vss => vss,
1308 
    vdd => vdd,
1309 
    nq => auxsc85,
1310 
    i1 => b(16),
1311 
    i0 => sel);
1312 
  auxsc84 : inv_x1
1313 
    PORT MAP (
1314 
    vss => vss,
1315 
    vdd => vdd,
1316 
    nq => auxsc84,
1317 
    i => a(16));
1318 
  auxsc80 : na2_x1
1319 
    PORT MAP (
1320 
    vss => vss,
1321 
    vdd => vdd,
1322 
    nq => auxsc80,
1323 
    i1 => b(15),
1324 
    i0 => sel);
1325 
  auxsc79 : inv_x1
1326 
    PORT MAP (
1327 
    vss => vss,
1328 
    vdd => vdd,
1329 
    nq => auxsc79,
1330 
    i => a(15));
1331 
  auxsc75 : na2_x1
1332 
    PORT MAP (
1333 
    vss => vss,
1334 
    vdd => vdd,
1335 
    nq => auxsc75,
1336 
    i1 => b(14),
1337 
    i0 => sel);
1338 
  auxsc74 : inv_x1
1339 
    PORT MAP (
1340 
    vss => vss,
1341 
    vdd => vdd,
1342 
    nq => auxsc74,
1343 
    i => a(14));
1344 
  auxsc70 : na2_x1
1345 
    PORT MAP (
1346 
    vss => vss,
1347 
    vdd => vdd,
1348 
    nq => auxsc70,
1349 
    i1 => b(13),
1350 
    i0 => sel);
1351 
  auxsc69 : inv_x1
1352 
    PORT MAP (
1353 
    vss => vss,
1354 
    vdd => vdd,
1355 
    nq => auxsc69,
1356 
    i => a(13));
1357 
  auxsc65 : na2_x1
1358 
    PORT MAP (
1359 
    vss => vss,
1360 
    vdd => vdd,
1361 
    nq => auxsc65,
1362 
    i1 => b(12),
1363 
    i0 => sel);
1364 
  auxsc64 : inv_x1
1365 
    PORT MAP (
1366 
    vss => vss,
1367 
    vdd => vdd,
1368 
    nq => auxsc64,
1369 
    i => a(12));
1370 
  auxsc60 : na2_x1
1371 
    PORT MAP (
1372 
    vss => vss,
1373 
    vdd => vdd,
1374 
    nq => auxsc60,
1375 
    i1 => b(11),
1376 
    i0 => sel);
1377 
  auxsc59 : inv_x1
1378 
    PORT MAP (
1379 
    vss => vss,
1380 
    vdd => vdd,
1381 
    nq => auxsc59,
1382 
    i => a(11));
1383 
  auxsc55 : na2_x1
1384 
    PORT MAP (
1385 
    vss => vss,
1386 
    vdd => vdd,
1387 
    nq => auxsc55,
1388 
    i1 => b(10),
1389 
    i0 => sel);
1390 
  auxsc54 : inv_x1
1391 
    PORT MAP (
1392 
    vss => vss,
1393 
    vdd => vdd,
1394 
    nq => auxsc54,
1395 
    i => a(10));
1396 
  auxsc50 : na2_x1
1397 
    PORT MAP (
1398 
    vss => vss,
1399 
    vdd => vdd,
1400 
    nq => auxsc50,
1401 
    i1 => b(9),
1402 
    i0 => sel);
1403 
  auxsc49 : inv_x1
1404 
    PORT MAP (
1405 
    vss => vss,
1406 
    vdd => vdd,
1407 
    nq => auxsc49,
1408 
    i => a(9));
1409 
  auxsc45 : na2_x1
1410 
    PORT MAP (
1411 
    vss => vss,
1412 
    vdd => vdd,
1413 
    nq => auxsc45,
1414 
    i1 => b(8),
1415 
    i0 => sel);
1416 
  auxsc44 : inv_x1
1417 
    PORT MAP (
1418 
    vss => vss,
1419 
    vdd => vdd,
1420 
    nq => auxsc44,
1421 
    i => a(8));
1422 
  auxsc40 : na2_x1
1423 
    PORT MAP (
1424 
    vss => vss,
1425 
    vdd => vdd,
1426 
    nq => auxsc40,
1427 
    i1 => b(7),
1428 
    i0 => sel);
1429 
  auxsc39 : inv_x1
1430 
    PORT MAP (
1431 
    vss => vss,
1432 
    vdd => vdd,
1433 
    nq => auxsc39,
1434 
    i => a(7));
1435 
  auxsc35 : na2_x1
1436 
    PORT MAP (
1437 
    vss => vss,
1438 
    vdd => vdd,
1439 
    nq => auxsc35,
1440 
    i1 => b(6),
1441 
    i0 => sel);
1442 
  auxsc34 : inv_x1
1443 
    PORT MAP (
1444 
    vss => vss,
1445 
    vdd => vdd,
1446 
    nq => auxsc34,
1447 
    i => a(6));
1448 
  auxsc30 : na2_x1
1449 
    PORT MAP (
1450 
    vss => vss,
1451 
    vdd => vdd,
1452 
    nq => auxsc30,
1453 
    i1 => b(5),
1454 
    i0 => sel);
1455 
  auxsc29 : inv_x1
1456 
    PORT MAP (
1457 
    vss => vss,
1458 
    vdd => vdd,
1459 
    nq => auxsc29,
1460 
    i => a(5));
1461 
  auxsc25 : na2_x1
1462 
    PORT MAP (
1463 
    vss => vss,
1464 
    vdd => vdd,
1465 
    nq => auxsc25,
1466 
    i1 => b(4),
1467 
    i0 => sel);
1468 
  auxsc24 : inv_x1
1469 
    PORT MAP (
1470 
    vss => vss,
1471 
    vdd => vdd,
1472 
    nq => auxsc24,
1473 
    i => a(4));
1474 
  auxsc20 : na2_x1
1475 
    PORT MAP (
1476 
    vss => vss,
1477 
    vdd => vdd,
1478 
    nq => auxsc20,
1479 
    i1 => b(3),
1480 
    i0 => sel);
1481 
  auxsc19 : inv_x1
1482 
    PORT MAP (
1483 
    vss => vss,
1484 
    vdd => vdd,
1485 
    nq => auxsc19,
1486 
    i => a(3));
1487 
  auxsc15 : na2_x1
1488 
    PORT MAP (
1489 
    vss => vss,
1490 
    vdd => vdd,
1491 
    nq => auxsc15,
1492 
    i1 => b(2),
1493 
    i0 => sel);
1494 
  auxsc14 : inv_x1
1495 
    PORT MAP (
1496 
    vss => vss,
1497 
    vdd => vdd,
1498 
    nq => auxsc14,
1499 
    i => a(2));
1500 
  auxsc10 : na2_x1
1501 
    PORT MAP (
1502 
    vss => vss,
1503 
    vdd => vdd,
1504 
    nq => auxsc10,
1505 
    i1 => b(1),
1506 
    i0 => sel);
1507 
  auxsc9 : inv_x1
1508 
    PORT MAP (
1509 
    vss => vss,
1510 
    vdd => vdd,
1511 
    nq => auxsc9,
1512 
    i => a(1));
1513 
  auxsc5 : na2_x1
1514 
    PORT MAP (
1515 
    vss => vss,
1516 
    vdd => vdd,
1517 
    nq => auxsc5,
1518 
    i1 => b(0),
1519 
    i0 => sel);
1520 
  auxsc4 : inv_x1
1521 
    PORT MAP (
1522 
    vss => vss,
1523 
    vdd => vdd,
1524 
    nq => auxsc4,
1525 
    i => a(0));
1526 
 
1527 
end VST;

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