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marta |
-- VHDL structural description generated from `out_trans`
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-- date : Mon Sep 10 03:00:16 2001
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-- Entity Declaration
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ENTITY out_trans IS
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PORT (
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en : in BIT; -- en
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x1 : in BIT_VECTOR (0 TO 15); -- x1
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x2 : in BIT_VECTOR (0 TO 15); -- x2
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x3 : in BIT_VECTOR (0 TO 15); -- x3
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x4 : in BIT_VECTOR (0 TO 15); -- x4
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z1 : in BIT_VECTOR (0 TO 15); -- z1
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z2 : in BIT_VECTOR (0 TO 15); -- z2
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z3 : in BIT_VECTOR (0 TO 15); -- z3
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z4 : in BIT_VECTOR (0 TO 15); -- z4
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y1 : out BIT_VECTOR (0 TO 15); -- y1
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y2 : inout BIT_VECTOR (0 TO 15); -- y2
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y3 : inout BIT_VECTOR (0 TO 15); -- y3
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y4 : out BIT_VECTOR (0 TO 15); -- y4
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reset : in BIT; -- reset
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vdd : in BIT; -- vdd
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vss : in BIT -- vss
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);
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END out_trans;
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-- Architecture Declaration
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ARCHITECTURE VST OF out_trans IS
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COMPONENT sm16adder_glopf
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port (
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a : in BIT_VECTOR(0 TO 15); -- a
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b : in BIT_VECTOR(0 TO 15); -- b
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en : in BIT; -- en
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clr : in BIT; -- clr
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s : inout BIT_VECTOR(0 TO 15); -- s
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vdd : in BIT; -- vdd
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vss : in BIT -- vss
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);
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END COMPONENT;
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COMPONENT sm16plus1mul_glopf
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port (
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in1 : in BIT_VECTOR(0 TO 15); -- in1
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in2 : in BIT_VECTOR(0 TO 15); -- in2
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en : in BIT; -- en
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clr : in BIT; -- clr
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mulout : out BIT_VECTOR(0 TO 15); -- mulout
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vdd : in BIT; -- vdd
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vss : in BIT -- vss
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);
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END COMPONENT;
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BEGIN
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trans1 : sm16plus1mul_glopf
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PORT MAP (
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vss => vss,
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vdd => vdd,
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mulout => y1(0)& y1(1)& y1(2)& y1(3)& y1(4)& y1(5)& y1(6)& y1(7)& y1(8)& y1(9)& y1(10)& y1(11)& y1(12)& y1(13)& y1(14)& y1(15),
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clr => reset,
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en => en,
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in2 => z1(0)& z1(1)& z1(2)& z1(3)& z1(4)& z1(5)& z1(6)& z1(7)& z1(8)& z1(9)& z1(10)& z1(11)& z1(12)& z1(13)& z1(14)& z1(15),
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in1 => x1(0)& x1(1)& x1(2)& x1(3)& x1(4)& x1(5)& x1(6)& x1(7)& x1(8)& x1(9)& x1(10)& x1(11)& x1(12)& x1(13)& x1(14)& x1(15));
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trans2 : sm16adder_glopf
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PORT MAP (
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vss => vss,
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vdd => vdd,
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s => y2(0)& y2(1)& y2(2)& y2(3)& y2(4)& y2(5)& y2(6)& y2(7)& y2(8)& y2(9)& y2(10)& y2(11)& y2(12)& y2(13)& y2(14)& y2(15),
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clr => reset,
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en => en,
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b => z2(0)& z2(1)& z2(2)& z2(3)& z2(4)& z2(5)& z2(6)& z2(7)& z2(8)& z2(9)& z2(10)& z2(11)& z2(12)& z2(13)& z2(14)& z2(15),
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a => x3(0)& x3(1)& x3(2)& x3(3)& x3(4)& x3(5)& x3(6)& x3(7)& x3(8)& x3(9)& x3(10)& x3(11)& x3(12)& x3(13)& x3(14)& x3(15));
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trans3 : sm16adder_glopf
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PORT MAP (
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vss => vss,
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vdd => vdd,
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s => y3(0)& y3(1)& y3(2)& y3(3)& y3(4)& y3(5)& y3(6)& y3(7)& y3(8)& y3(9)& y3(10)& y3(11)& y3(12)& y3(13)& y3(14)& y3(15),
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clr => reset,
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en => en,
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b => z3(0)& z3(1)& z3(2)& z3(3)& z3(4)& z3(5)& z3(6)& z3(7)& z3(8)& z3(9)& z3(10)& z3(11)& z3(12)& z3(13)& z3(14)& z3(15),
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a => x2(0)& x2(1)& x2(2)& x2(3)& x2(4)& x2(5)& x2(6)& x2(7)& x2(8)& x2(9)& x2(10)& x2(11)& x2(12)& x2(13)& x2(14)& x2(15));
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trans4 : sm16plus1mul_glopf
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PORT MAP (
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vss => vss,
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vdd => vdd,
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mulout => y4(0)& y4(1)& y4(2)& y4(3)& y4(4)& y4(5)& y4(6)& y4(7)& y4(8)& y4(9)& y4(10)& y4(11)& y4(12)& y4(13)& y4(14)& y4(15),
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clr => reset,
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en => en,
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in2 => z4(0)& z4(1)& z4(2)& z4(3)& z4(4)& z4(5)& z4(6)& z4(7)& z4(8)& z4(9)& z4(10)& z4(11)& z4(12)& z4(13)& z4(14)& z4(15),
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in1 => x4(0)& x4(1)& x4(2)& x4(3)& x4(4)& x4(5)& x4(6)& x4(7)& x4(8)& x4(9)& x4(10)& x4(11)& x4(12)& x4(13)& x4(14)& x4(15));
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end VST;
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