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[/] [structural_vhdl/] [trunk/] [idea_machine/] [reg16.vst] - Blame information for rev 4

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-- VHDL structural description generated from `reg16`
--              date : Sat Sep  8 03:14:30 2001
 
 
-- Entity Declaration
 
ENTITY reg16 IS
  PORT (
  d : in BIT_VECTOR (0 TO 15);  -- d
  en : in BIT;  -- en
  clr : in BIT; -- clr
  q : inout BIT_VECTOR (0 TO 15);       -- q
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END reg16;
 
-- Architecture Declaration
 
ARCHITECTURE VST OF reg16 IS
  COMPONENT d_latch_glopf
    port (
    d : in BIT; -- d
    ck : in BIT;        -- ck
    clr : in BIT;       -- clr
    q : inout BIT;      -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
 
BEGIN
 
  latch0 : d_latch_glopf
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => q(0),
    clr => clr,
    ck => en,
    d => d(0));
  latch1 : d_latch_glopf
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => q(1),
    clr => clr,
    ck => en,
    d => d(1));
  latch2 : d_latch_glopf
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => q(2),
    clr => clr,
    ck => en,
    d => d(2));
  latch3 : d_latch_glopf
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => q(3),
    clr => clr,
    ck => en,
    d => d(3));
  latch4 : d_latch_glopf
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => q(4),
    clr => clr,
    ck => en,
    d => d(4));
  latch5 : d_latch_glopf
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => q(5),
    clr => clr,
    ck => en,
    d => d(5));
  latch6 : d_latch_glopf
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => q(6),
    clr => clr,
    ck => en,
    d => d(6));
  latch7 : d_latch_glopf
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => q(7),
    clr => clr,
    ck => en,
    d => d(7));
  latch8 : d_latch_glopf
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => q(8),
    clr => clr,
    ck => en,
    d => d(8));
  latch9 : d_latch_glopf
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => q(9),
    clr => clr,
    ck => en,
    d => d(9));
  latch10 : d_latch_glopf
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => q(10),
    clr => clr,
    ck => en,
    d => d(10));
  latch11 : d_latch_glopf
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => q(11),
    clr => clr,
    ck => en,
    d => d(11));
  latch12 : d_latch_glopf
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => q(12),
    clr => clr,
    ck => en,
    d => d(12));
  latch13 : d_latch_glopf
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => q(13),
    clr => clr,
    ck => en,
    d => d(13));
  latch14 : d_latch_glopf
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => q(14),
    clr => clr,
    ck => en,
    d => d(14));
  latch15 : d_latch_glopf
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => q(15),
    clr => clr,
    ck => en,
    d => d(15));
 
end VST;

Line No.	Rev	Author	Line
1	2	marta	-- VHDL structural description generated from `reg16`
2			`-- date : Sat Sep 8 03:14:30 2001`
3
4
5			`-- Entity Declaration`
6
7			`ENTITY reg16 IS`
8			`PORT (`
9			`d : in BIT_VECTOR (0 TO 15); -- d`
10			`en : in BIT; -- en`
11			`clr : in BIT; -- clr`
12			`q : inout BIT_VECTOR (0 TO 15); -- q`
13			`vdd : in BIT; -- vdd`
14			`vss : in BIT -- vss`
15			`);`
16			`END reg16;`
17
18			`-- Architecture Declaration`
19
20			`ARCHITECTURE VST OF reg16 IS`
21			`COMPONENT d_latch_glopf`
22			`port (`
23			`d : in BIT; -- d`
24			`ck : in BIT; -- ck`
25			`clr : in BIT; -- clr`
26			`q : inout BIT; -- q`
27			`vdd : in BIT; -- vdd`
28			`vss : in BIT -- vss`
29			`);`
30			`END COMPONENT;`
31
32
33			`BEGIN`
34
35			`latch0 : d_latch_glopf`
36			`PORT MAP (`
37			`vss => vss,`
38			`vdd => vdd,`
39			`q => q(0),`
40			`clr => clr,`
41			`ck => en,`
42			`d => d(0));`
43			`latch1 : d_latch_glopf`
44			`PORT MAP (`
45			`vss => vss,`
46			`vdd => vdd,`
47			`q => q(1),`
48			`clr => clr,`
49			`ck => en,`
50			`d => d(1));`
51			`latch2 : d_latch_glopf`
52			`PORT MAP (`
53			`vss => vss,`
54			`vdd => vdd,`
55			`q => q(2),`
56			`clr => clr,`
57			`ck => en,`
58			`d => d(2));`
59			`latch3 : d_latch_glopf`
60			`PORT MAP (`
61			`vss => vss,`
62			`vdd => vdd,`
63			`q => q(3),`
64			`clr => clr,`
65			`ck => en,`
66			`d => d(3));`
67			`latch4 : d_latch_glopf`
68			`PORT MAP (`
69			`vss => vss,`
70			`vdd => vdd,`
71			`q => q(4),`
72			`clr => clr,`
73			`ck => en,`
74			`d => d(4));`
75			`latch5 : d_latch_glopf`
76			`PORT MAP (`
77			`vss => vss,`
78			`vdd => vdd,`
79			`q => q(5),`
80			`clr => clr,`
81			`ck => en,`
82			`d => d(5));`
83			`latch6 : d_latch_glopf`
84			`PORT MAP (`
85			`vss => vss,`
86			`vdd => vdd,`
87			`q => q(6),`
88			`clr => clr,`
89			`ck => en,`
90			`d => d(6));`
91			`latch7 : d_latch_glopf`
92			`PORT MAP (`
93			`vss => vss,`
94			`vdd => vdd,`
95			`q => q(7),`
96			`clr => clr,`
97			`ck => en,`
98			`d => d(7));`
99			`latch8 : d_latch_glopf`
100			`PORT MAP (`
101			`vss => vss,`
102			`vdd => vdd,`
103			`q => q(8),`
104			`clr => clr,`
105			`ck => en,`
106			`d => d(8));`
107			`latch9 : d_latch_glopf`
108			`PORT MAP (`
109			`vss => vss,`
110			`vdd => vdd,`
111			`q => q(9),`
112			`clr => clr,`
113			`ck => en,`
114			`d => d(9));`
115			`latch10 : d_latch_glopf`
116			`PORT MAP (`
117			`vss => vss,`
118			`vdd => vdd,`
119			`q => q(10),`
120			`clr => clr,`
121			`ck => en,`
122			`d => d(10));`
123			`latch11 : d_latch_glopf`
124			`PORT MAP (`
125			`vss => vss,`
126			`vdd => vdd,`
127			`q => q(11),`
128			`clr => clr,`
129			`ck => en,`
130			`d => d(11));`
131			`latch12 : d_latch_glopf`
132			`PORT MAP (`
133			`vss => vss,`
134			`vdd => vdd,`
135			`q => q(12),`
136			`clr => clr,`
137			`ck => en,`
138			`d => d(12));`
139			`latch13 : d_latch_glopf`
140			`PORT MAP (`
141			`vss => vss,`
142			`vdd => vdd,`
143			`q => q(13),`
144			`clr => clr,`
145			`ck => en,`
146			`d => d(13));`
147			`latch14 : d_latch_glopf`
148			`PORT MAP (`
149			`vss => vss,`
150			`vdd => vdd,`
151			`q => q(14),`
152			`clr => clr,`
153			`ck => en,`
154			`d => d(14));`
155			`latch15 : d_latch_glopf`
156			`PORT MAP (`
157			`vss => vss,`
158			`vdd => vdd,`
159			`q => q(15),`
160			`clr => clr,`
161			`ck => en,`
162			`d => d(15));`
163
164			`end VST;`

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[/] [structural_vhdl/] [trunk/] [idea_machine/] [reg16.vst] - Blame information for rev 4