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[/] [structural_vhdl/] [trunk/] [idea_machine/] [reg16_glopf.vst] - Blame information for rev 4

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1 2 marta 
-- VHDL structural description generated from `reg16_glopf`
2 
--              date : Sat Sep  8 03:16:51 2001
3 
 
4 
 
5 
-- Entity Declaration
6 
 
7 
ENTITY reg16_glopf IS
8 
  PORT (
9 
  d : in BIT_VECTOR (0 TO 15);  -- d
10 
  en : in BIT;  -- en
11 
  clr : in BIT; -- clr
12 
  q : inout BIT_VECTOR (0 TO 15);       -- q
13 
  vdd : in BIT; -- vdd
14 
  vss : in BIT  -- vss
15 
  );
16 
END reg16_glopf;
17 
 
18 
-- Architecture Declaration
19 
 
20 
ARCHITECTURE VST OF reg16_glopf IS
21 
  COMPONENT inv_x2
22 
    port (
23 
    i : in BIT; -- i
24 
    nq : out BIT;       -- nq
25 
    vdd : in BIT;       -- vdd
26 
    vss : in BIT        -- vss
27 
    );
28 
  END COMPONENT;
29 
 
30 
  COMPONENT a2_x2
31 
    port (
32 
    i0 : in BIT;        -- i0
33 
    i1 : in BIT;        -- i1
34 
    q : out BIT;        -- q
35 
    vdd : in BIT;       -- vdd
36 
    vss : in BIT        -- vss
37 
    );
38 
  END COMPONENT;
39 
 
40 
  COMPONENT no3_x4
41 
    port (
42 
    i0 : in BIT;        -- i0
43 
    i1 : in BIT;        -- i1
44 
    i2 : in BIT;        -- i2
45 
    nq : out BIT;       -- nq
46 
    vdd : in BIT;       -- vdd
47 
    vss : in BIT        -- vss
48 
    );
49 
  END COMPONENT;
50 
 
51 
  COMPONENT no2_x4
52 
    port (
53 
    i0 : in BIT;        -- i0
54 
    i1 : in BIT;        -- i1
55 
    nq : out BIT;       -- nq
56 
    vdd : in BIT;       -- vdd
57 
    vss : in BIT        -- vss
58 
    );
59 
  END COMPONENT;
60 
 
61 
  COMPONENT buf_x2
62 
    port (
63 
    i : in BIT; -- i
64 
    q : out BIT;        -- q
65 
    vdd : in BIT;       -- vdd
66 
    vss : in BIT        -- vss
67 
    );
68 
  END COMPONENT;
69 
 
70 
  SIGNAL netops256 : BIT;       -- netops256
71 
  SIGNAL netops255 : BIT;       -- netops255
72 
  SIGNAL latch0_o_nor2 : BIT;   -- latch0.o_nor2
73 
  SIGNAL latch0_o_inv : BIT;    -- latch0.o_inv
74 
  SIGNAL latch0_o_an2 : BIT;    -- latch0.o_an2
75 
  SIGNAL latch0_o_an1 : BIT;    -- latch0.o_an1
76 
  SIGNAL latch1_o_nor2 : BIT;   -- latch1.o_nor2
77 
  SIGNAL latch1_o_inv : BIT;    -- latch1.o_inv
78 
  SIGNAL latch1_o_an2 : BIT;    -- latch1.o_an2
79 
  SIGNAL latch1_o_an1 : BIT;    -- latch1.o_an1
80 
  SIGNAL latch2_o_nor2 : BIT;   -- latch2.o_nor2
81 
  SIGNAL latch2_o_inv : BIT;    -- latch2.o_inv
82 
  SIGNAL latch2_o_an2 : BIT;    -- latch2.o_an2
83 
  SIGNAL latch2_o_an1 : BIT;    -- latch2.o_an1
84 
  SIGNAL latch3_o_nor2 : BIT;   -- latch3.o_nor2
85 
  SIGNAL latch3_o_inv : BIT;    -- latch3.o_inv
86 
  SIGNAL latch3_o_an2 : BIT;    -- latch3.o_an2
87 
  SIGNAL latch3_o_an1 : BIT;    -- latch3.o_an1
88 
  SIGNAL latch4_o_nor2 : BIT;   -- latch4.o_nor2
89 
  SIGNAL latch4_o_inv : BIT;    -- latch4.o_inv
90 
  SIGNAL latch4_o_an2 : BIT;    -- latch4.o_an2
91 
  SIGNAL latch4_o_an1 : BIT;    -- latch4.o_an1
92 
  SIGNAL latch5_o_nor2 : BIT;   -- latch5.o_nor2
93 
  SIGNAL latch5_o_inv : BIT;    -- latch5.o_inv
94 
  SIGNAL latch5_o_an2 : BIT;    -- latch5.o_an2
95 
  SIGNAL latch5_o_an1 : BIT;    -- latch5.o_an1
96 
  SIGNAL latch6_o_nor2 : BIT;   -- latch6.o_nor2
97 
  SIGNAL latch6_o_inv : BIT;    -- latch6.o_inv
98 
  SIGNAL latch6_o_an2 : BIT;    -- latch6.o_an2
99 
  SIGNAL latch6_o_an1 : BIT;    -- latch6.o_an1
100 
  SIGNAL latch7_o_nor2 : BIT;   -- latch7.o_nor2
101 
  SIGNAL latch7_o_inv : BIT;    -- latch7.o_inv
102 
  SIGNAL latch7_o_an2 : BIT;    -- latch7.o_an2
103 
  SIGNAL latch7_o_an1 : BIT;    -- latch7.o_an1
104 
  SIGNAL latch8_o_nor2 : BIT;   -- latch8.o_nor2
105 
  SIGNAL latch8_o_inv : BIT;    -- latch8.o_inv
106 
  SIGNAL latch8_o_an2 : BIT;    -- latch8.o_an2
107 
  SIGNAL latch8_o_an1 : BIT;    -- latch8.o_an1
108 
  SIGNAL latch9_o_nor2 : BIT;   -- latch9.o_nor2
109 
  SIGNAL latch9_o_inv : BIT;    -- latch9.o_inv
110 
  SIGNAL latch9_o_an2 : BIT;    -- latch9.o_an2
111 
  SIGNAL latch9_o_an1 : BIT;    -- latch9.o_an1
112 
  SIGNAL latch10_o_nor2 : BIT;  -- latch10.o_nor2
113 
  SIGNAL latch10_o_inv : BIT;   -- latch10.o_inv
114 
  SIGNAL latch10_o_an2 : BIT;   -- latch10.o_an2
115 
  SIGNAL latch10_o_an1 : BIT;   -- latch10.o_an1
116 
  SIGNAL latch11_o_nor2 : BIT;  -- latch11.o_nor2
117 
  SIGNAL latch11_o_inv : BIT;   -- latch11.o_inv
118 
  SIGNAL latch11_o_an2 : BIT;   -- latch11.o_an2
119 
  SIGNAL latch11_o_an1 : BIT;   -- latch11.o_an1
120 
  SIGNAL latch12_o_nor2 : BIT;  -- latch12.o_nor2
121 
  SIGNAL latch12_o_inv : BIT;   -- latch12.o_inv
122 
  SIGNAL latch12_o_an2 : BIT;   -- latch12.o_an2
123 
  SIGNAL latch12_o_an1 : BIT;   -- latch12.o_an1
124 
  SIGNAL latch13_o_nor2 : BIT;  -- latch13.o_nor2
125 
  SIGNAL latch13_o_inv : BIT;   -- latch13.o_inv
126 
  SIGNAL latch13_o_an2 : BIT;   -- latch13.o_an2
127 
  SIGNAL latch13_o_an1 : BIT;   -- latch13.o_an1
128 
  SIGNAL latch14_o_nor2 : BIT;  -- latch14.o_nor2
129 
  SIGNAL latch14_o_inv : BIT;   -- latch14.o_inv
130 
  SIGNAL latch14_o_an2 : BIT;   -- latch14.o_an2
131 
  SIGNAL latch14_o_an1 : BIT;   -- latch14.o_an1
132 
  SIGNAL latch15_o_nor2 : BIT;  -- latch15.o_nor2
133 
  SIGNAL latch15_o_inv : BIT;   -- latch15.o_inv
134 
  SIGNAL latch15_o_an2 : BIT;   -- latch15.o_an2
135 
  SIGNAL latch15_o_an1 : BIT;   -- latch15.o_an1
136 
 
137 
BEGIN
138 
 
139 
  latch0_inv : inv_x2
140 
    PORT MAP (
141 
    vss => vss,
142 
    vdd => vdd,
143 
    nq => latch0_o_inv,
144 
    i => d(0));
145 
  latch0_an1 : a2_x2
146 
    PORT MAP (
147 
    vss => vss,
148 
    vdd => vdd,
149 
    q => latch0_o_an1,
150 
    i1 => netops256,
151 
    i0 => latch0_o_inv);
152 
  latch0_an2 : a2_x2
153 
    PORT MAP (
154 
    vss => vss,
155 
    vdd => vdd,
156 
    q => latch0_o_an2,
157 
    i1 => netops256,
158 
    i0 => d(0));
159 
  latch0_nor1 : no3_x4
160 
    PORT MAP (
161 
    vss => vss,
162 
    vdd => vdd,
163 
    nq => q(0),
164 
    i2 => latch0_o_nor2,
165 
    i1 => netops255,
166 
    i0 => latch0_o_an1);
167 
  latch0_nor2 : no2_x4
168 
    PORT MAP (
169 
    vss => vss,
170 
    vdd => vdd,
171 
    nq => latch0_o_nor2,
172 
    i1 => latch0_o_an2,
173 
    i0 => q(0));
174 
  latch1_inv : inv_x2
175 
    PORT MAP (
176 
    vss => vss,
177 
    vdd => vdd,
178 
    nq => latch1_o_inv,
179 
    i => d(1));
180 
  latch1_an1 : a2_x2
181 
    PORT MAP (
182 
    vss => vss,
183 
    vdd => vdd,
184 
    q => latch1_o_an1,
185 
    i1 => netops256,
186 
    i0 => latch1_o_inv);
187 
  latch1_an2 : a2_x2
188 
    PORT MAP (
189 
    vss => vss,
190 
    vdd => vdd,
191 
    q => latch1_o_an2,
192 
    i1 => netops256,
193 
    i0 => d(1));
194 
  latch1_nor1 : no3_x4
195 
    PORT MAP (
196 
    vss => vss,
197 
    vdd => vdd,
198 
    nq => q(1),
199 
    i2 => latch1_o_nor2,
200 
    i1 => netops255,
201 
    i0 => latch1_o_an1);
202 
  latch1_nor2 : no2_x4
203 
    PORT MAP (
204 
    vss => vss,
205 
    vdd => vdd,
206 
    nq => latch1_o_nor2,
207 
    i1 => latch1_o_an2,
208 
    i0 => q(1));
209 
  latch2_inv : inv_x2
210 
    PORT MAP (
211 
    vss => vss,
212 
    vdd => vdd,
213 
    nq => latch2_o_inv,
214 
    i => d(2));
215 
  latch2_an1 : a2_x2
216 
    PORT MAP (
217 
    vss => vss,
218 
    vdd => vdd,
219 
    q => latch2_o_an1,
220 
    i1 => netops256,
221 
    i0 => latch2_o_inv);
222 
  latch2_an2 : a2_x2
223 
    PORT MAP (
224 
    vss => vss,
225 
    vdd => vdd,
226 
    q => latch2_o_an2,
227 
    i1 => netops256,
228 
    i0 => d(2));
229 
  latch2_nor1 : no3_x4
230 
    PORT MAP (
231 
    vss => vss,
232 
    vdd => vdd,
233 
    nq => q(2),
234 
    i2 => latch2_o_nor2,
235 
    i1 => netops255,
236 
    i0 => latch2_o_an1);
237 
  latch2_nor2 : no2_x4
238 
    PORT MAP (
239 
    vss => vss,
240 
    vdd => vdd,
241 
    nq => latch2_o_nor2,
242 
    i1 => latch2_o_an2,
243 
    i0 => q(2));
244 
  latch3_inv : inv_x2
245 
    PORT MAP (
246 
    vss => vss,
247 
    vdd => vdd,
248 
    nq => latch3_o_inv,
249 
    i => d(3));
250 
  latch3_an1 : a2_x2
251 
    PORT MAP (
252 
    vss => vss,
253 
    vdd => vdd,
254 
    q => latch3_o_an1,
255 
    i1 => netops256,
256 
    i0 => latch3_o_inv);
257 
  latch3_an2 : a2_x2
258 
    PORT MAP (
259 
    vss => vss,
260 
    vdd => vdd,
261 
    q => latch3_o_an2,
262 
    i1 => netops256,
263 
    i0 => d(3));
264 
  latch3_nor1 : no3_x4
265 
    PORT MAP (
266 
    vss => vss,
267 
    vdd => vdd,
268 
    nq => q(3),
269 
    i2 => latch3_o_nor2,
270 
    i1 => netops255,
271 
    i0 => latch3_o_an1);
272 
  latch3_nor2 : no2_x4
273 
    PORT MAP (
274 
    vss => vss,
275 
    vdd => vdd,
276 
    nq => latch3_o_nor2,
277 
    i1 => latch3_o_an2,
278 
    i0 => q(3));
279 
  latch4_inv : inv_x2
280 
    PORT MAP (
281 
    vss => vss,
282 
    vdd => vdd,
283 
    nq => latch4_o_inv,
284 
    i => d(4));
285 
  latch4_an1 : a2_x2
286 
    PORT MAP (
287 
    vss => vss,
288 
    vdd => vdd,
289 
    q => latch4_o_an1,
290 
    i1 => netops256,
291 
    i0 => latch4_o_inv);
292 
  latch4_an2 : a2_x2
293 
    PORT MAP (
294 
    vss => vss,
295 
    vdd => vdd,
296 
    q => latch4_o_an2,
297 
    i1 => netops256,
298 
    i0 => d(4));
299 
  latch4_nor1 : no3_x4
300 
    PORT MAP (
301 
    vss => vss,
302 
    vdd => vdd,
303 
    nq => q(4),
304 
    i2 => latch4_o_nor2,
305 
    i1 => netops255,
306 
    i0 => latch4_o_an1);
307 
  latch4_nor2 : no2_x4
308 
    PORT MAP (
309 
    vss => vss,
310 
    vdd => vdd,
311 
    nq => latch4_o_nor2,
312 
    i1 => latch4_o_an2,
313 
    i0 => q(4));
314 
  latch5_inv : inv_x2
315 
    PORT MAP (
316 
    vss => vss,
317 
    vdd => vdd,
318 
    nq => latch5_o_inv,
319 
    i => d(5));
320 
  latch5_an1 : a2_x2
321 
    PORT MAP (
322 
    vss => vss,
323 
    vdd => vdd,
324 
    q => latch5_o_an1,
325 
    i1 => netops256,
326 
    i0 => latch5_o_inv);
327 
  latch5_an2 : a2_x2
328 
    PORT MAP (
329 
    vss => vss,
330 
    vdd => vdd,
331 
    q => latch5_o_an2,
332 
    i1 => netops256,
333 
    i0 => d(5));
334 
  latch5_nor1 : no3_x4
335 
    PORT MAP (
336 
    vss => vss,
337 
    vdd => vdd,
338 
    nq => q(5),
339 
    i2 => latch5_o_nor2,
340 
    i1 => netops255,
341 
    i0 => latch5_o_an1);
342 
  latch5_nor2 : no2_x4
343 
    PORT MAP (
344 
    vss => vss,
345 
    vdd => vdd,
346 
    nq => latch5_o_nor2,
347 
    i1 => latch5_o_an2,
348 
    i0 => q(5));
349 
  latch6_inv : inv_x2
350 
    PORT MAP (
351 
    vss => vss,
352 
    vdd => vdd,
353 
    nq => latch6_o_inv,
354 
    i => d(6));
355 
  latch6_an1 : a2_x2
356 
    PORT MAP (
357 
    vss => vss,
358 
    vdd => vdd,
359 
    q => latch6_o_an1,
360 
    i1 => netops256,
361 
    i0 => latch6_o_inv);
362 
  latch6_an2 : a2_x2
363 
    PORT MAP (
364 
    vss => vss,
365 
    vdd => vdd,
366 
    q => latch6_o_an2,
367 
    i1 => netops256,
368 
    i0 => d(6));
369 
  latch6_nor1 : no3_x4
370 
    PORT MAP (
371 
    vss => vss,
372 
    vdd => vdd,
373 
    nq => q(6),
374 
    i2 => latch6_o_nor2,
375 
    i1 => netops255,
376 
    i0 => latch6_o_an1);
377 
  latch6_nor2 : no2_x4
378 
    PORT MAP (
379 
    vss => vss,
380 
    vdd => vdd,
381 
    nq => latch6_o_nor2,
382 
    i1 => latch6_o_an2,
383 
    i0 => q(6));
384 
  latch7_inv : inv_x2
385 
    PORT MAP (
386 
    vss => vss,
387 
    vdd => vdd,
388 
    nq => latch7_o_inv,
389 
    i => d(7));
390 
  latch7_an1 : a2_x2
391 
    PORT MAP (
392 
    vss => vss,
393 
    vdd => vdd,
394 
    q => latch7_o_an1,
395 
    i1 => netops256,
396 
    i0 => latch7_o_inv);
397 
  latch7_an2 : a2_x2
398 
    PORT MAP (
399 
    vss => vss,
400 
    vdd => vdd,
401 
    q => latch7_o_an2,
402 
    i1 => netops256,
403 
    i0 => d(7));
404 
  latch7_nor1 : no3_x4
405 
    PORT MAP (
406 
    vss => vss,
407 
    vdd => vdd,
408 
    nq => q(7),
409 
    i2 => latch7_o_nor2,
410 
    i1 => netops255,
411 
    i0 => latch7_o_an1);
412 
  latch7_nor2 : no2_x4
413 
    PORT MAP (
414 
    vss => vss,
415 
    vdd => vdd,
416 
    nq => latch7_o_nor2,
417 
    i1 => latch7_o_an2,
418 
    i0 => q(7));
419 
  latch8_inv : inv_x2
420 
    PORT MAP (
421 
    vss => vss,
422 
    vdd => vdd,
423 
    nq => latch8_o_inv,
424 
    i => d(8));
425 
  latch8_an1 : a2_x2
426 
    PORT MAP (
427 
    vss => vss,
428 
    vdd => vdd,
429 
    q => latch8_o_an1,
430 
    i1 => netops256,
431 
    i0 => latch8_o_inv);
432 
  latch8_an2 : a2_x2
433 
    PORT MAP (
434 
    vss => vss,
435 
    vdd => vdd,
436 
    q => latch8_o_an2,
437 
    i1 => netops256,
438 
    i0 => d(8));
439 
  latch8_nor1 : no3_x4
440 
    PORT MAP (
441 
    vss => vss,
442 
    vdd => vdd,
443 
    nq => q(8),
444 
    i2 => latch8_o_nor2,
445 
    i1 => netops255,
446 
    i0 => latch8_o_an1);
447 
  latch8_nor2 : no2_x4
448 
    PORT MAP (
449 
    vss => vss,
450 
    vdd => vdd,
451 
    nq => latch8_o_nor2,
452 
    i1 => latch8_o_an2,
453 
    i0 => q(8));
454 
  latch9_inv : inv_x2
455 
    PORT MAP (
456 
    vss => vss,
457 
    vdd => vdd,
458 
    nq => latch9_o_inv,
459 
    i => d(9));
460 
  latch9_an1 : a2_x2
461 
    PORT MAP (
462 
    vss => vss,
463 
    vdd => vdd,
464 
    q => latch9_o_an1,
465 
    i1 => netops256,
466 
    i0 => latch9_o_inv);
467 
  latch9_an2 : a2_x2
468 
    PORT MAP (
469 
    vss => vss,
470 
    vdd => vdd,
471 
    q => latch9_o_an2,
472 
    i1 => netops256,
473 
    i0 => d(9));
474 
  latch9_nor1 : no3_x4
475 
    PORT MAP (
476 
    vss => vss,
477 
    vdd => vdd,
478 
    nq => q(9),
479 
    i2 => latch9_o_nor2,
480 
    i1 => netops255,
481 
    i0 => latch9_o_an1);
482 
  latch9_nor2 : no2_x4
483 
    PORT MAP (
484 
    vss => vss,
485 
    vdd => vdd,
486 
    nq => latch9_o_nor2,
487 
    i1 => latch9_o_an2,
488 
    i0 => q(9));
489 
  latch10_inv : inv_x2
490 
    PORT MAP (
491 
    vss => vss,
492 
    vdd => vdd,
493 
    nq => latch10_o_inv,
494 
    i => d(10));
495 
  latch10_an1 : a2_x2
496 
    PORT MAP (
497 
    vss => vss,
498 
    vdd => vdd,
499 
    q => latch10_o_an1,
500 
    i1 => netops256,
501 
    i0 => latch10_o_inv);
502 
  latch10_an2 : a2_x2
503 
    PORT MAP (
504 
    vss => vss,
505 
    vdd => vdd,
506 
    q => latch10_o_an2,
507 
    i1 => netops256,
508 
    i0 => d(10));
509 
  latch10_nor1 : no3_x4
510 
    PORT MAP (
511 
    vss => vss,
512 
    vdd => vdd,
513 
    nq => q(10),
514 
    i2 => latch10_o_nor2,
515 
    i1 => netops255,
516 
    i0 => latch10_o_an1);
517 
  latch10_nor2 : no2_x4
518 
    PORT MAP (
519 
    vss => vss,
520 
    vdd => vdd,
521 
    nq => latch10_o_nor2,
522 
    i1 => latch10_o_an2,
523 
    i0 => q(10));
524 
  latch11_inv : inv_x2
525 
    PORT MAP (
526 
    vss => vss,
527 
    vdd => vdd,
528 
    nq => latch11_o_inv,
529 
    i => d(11));
530 
  latch11_an1 : a2_x2
531 
    PORT MAP (
532 
    vss => vss,
533 
    vdd => vdd,
534 
    q => latch11_o_an1,
535 
    i1 => netops256,
536 
    i0 => latch11_o_inv);
537 
  latch11_an2 : a2_x2
538 
    PORT MAP (
539 
    vss => vss,
540 
    vdd => vdd,
541 
    q => latch11_o_an2,
542 
    i1 => netops256,
543 
    i0 => d(11));
544 
  latch11_nor1 : no3_x4
545 
    PORT MAP (
546 
    vss => vss,
547 
    vdd => vdd,
548 
    nq => q(11),
549 
    i2 => latch11_o_nor2,
550 
    i1 => netops255,
551 
    i0 => latch11_o_an1);
552 
  latch11_nor2 : no2_x4
553 
    PORT MAP (
554 
    vss => vss,
555 
    vdd => vdd,
556 
    nq => latch11_o_nor2,
557 
    i1 => latch11_o_an2,
558 
    i0 => q(11));
559 
  latch12_inv : inv_x2
560 
    PORT MAP (
561 
    vss => vss,
562 
    vdd => vdd,
563 
    nq => latch12_o_inv,
564 
    i => d(12));
565 
  latch12_an1 : a2_x2
566 
    PORT MAP (
567 
    vss => vss,
568 
    vdd => vdd,
569 
    q => latch12_o_an1,
570 
    i1 => netops256,
571 
    i0 => latch12_o_inv);
572 
  latch12_an2 : a2_x2
573 
    PORT MAP (
574 
    vss => vss,
575 
    vdd => vdd,
576 
    q => latch12_o_an2,
577 
    i1 => netops256,
578 
    i0 => d(12));
579 
  latch12_nor1 : no3_x4
580 
    PORT MAP (
581 
    vss => vss,
582 
    vdd => vdd,
583 
    nq => q(12),
584 
    i2 => latch12_o_nor2,
585 
    i1 => netops255,
586 
    i0 => latch12_o_an1);
587 
  latch12_nor2 : no2_x4
588 
    PORT MAP (
589 
    vss => vss,
590 
    vdd => vdd,
591 
    nq => latch12_o_nor2,
592 
    i1 => latch12_o_an2,
593 
    i0 => q(12));
594 
  latch13_inv : inv_x2
595 
    PORT MAP (
596 
    vss => vss,
597 
    vdd => vdd,
598 
    nq => latch13_o_inv,
599 
    i => d(13));
600 
  latch13_an1 : a2_x2
601 
    PORT MAP (
602 
    vss => vss,
603 
    vdd => vdd,
604 
    q => latch13_o_an1,
605 
    i1 => netops256,
606 
    i0 => latch13_o_inv);
607 
  latch13_an2 : a2_x2
608 
    PORT MAP (
609 
    vss => vss,
610 
    vdd => vdd,
611 
    q => latch13_o_an2,
612 
    i1 => netops256,
613 
    i0 => d(13));
614 
  latch13_nor1 : no3_x4
615 
    PORT MAP (
616 
    vss => vss,
617 
    vdd => vdd,
618 
    nq => q(13),
619 
    i2 => latch13_o_nor2,
620 
    i1 => netops255,
621 
    i0 => latch13_o_an1);
622 
  latch13_nor2 : no2_x4
623 
    PORT MAP (
624 
    vss => vss,
625 
    vdd => vdd,
626 
    nq => latch13_o_nor2,
627 
    i1 => latch13_o_an2,
628 
    i0 => q(13));
629 
  latch14_inv : inv_x2
630 
    PORT MAP (
631 
    vss => vss,
632 
    vdd => vdd,
633 
    nq => latch14_o_inv,
634 
    i => d(14));
635 
  latch14_an1 : a2_x2
636 
    PORT MAP (
637 
    vss => vss,
638 
    vdd => vdd,
639 
    q => latch14_o_an1,
640 
    i1 => netops256,
641 
    i0 => latch14_o_inv);
642 
  latch14_an2 : a2_x2
643 
    PORT MAP (
644 
    vss => vss,
645 
    vdd => vdd,
646 
    q => latch14_o_an2,
647 
    i1 => netops256,
648 
    i0 => d(14));
649 
  latch14_nor1 : no3_x4
650 
    PORT MAP (
651 
    vss => vss,
652 
    vdd => vdd,
653 
    nq => q(14),
654 
    i2 => latch14_o_nor2,
655 
    i1 => netops255,
656 
    i0 => latch14_o_an1);
657 
  latch14_nor2 : no2_x4
658 
    PORT MAP (
659 
    vss => vss,
660 
    vdd => vdd,
661 
    nq => latch14_o_nor2,
662 
    i1 => latch14_o_an2,
663 
    i0 => q(14));
664 
  latch15_inv : inv_x2
665 
    PORT MAP (
666 
    vss => vss,
667 
    vdd => vdd,
668 
    nq => latch15_o_inv,
669 
    i => d(15));
670 
  latch15_an1 : a2_x2
671 
    PORT MAP (
672 
    vss => vss,
673 
    vdd => vdd,
674 
    q => latch15_o_an1,
675 
    i1 => netops256,
676 
    i0 => latch15_o_inv);
677 
  latch15_an2 : a2_x2
678 
    PORT MAP (
679 
    vss => vss,
680 
    vdd => vdd,
681 
    q => latch15_o_an2,
682 
    i1 => netops256,
683 
    i0 => d(15));
684 
  latch15_nor1 : no3_x4
685 
    PORT MAP (
686 
    vss => vss,
687 
    vdd => vdd,
688 
    nq => q(15),
689 
    i2 => latch15_o_nor2,
690 
    i1 => netops255,
691 
    i0 => latch15_o_an1);
692 
  latch15_nor2 : no2_x4
693 
    PORT MAP (
694 
    vss => vss,
695 
    vdd => vdd,
696 
    nq => latch15_o_nor2,
697 
    i1 => latch15_o_an2,
698 
    i0 => q(15));
699 
  netopi255 : buf_x2
700 
    PORT MAP (
701 
    vss => vss,
702 
    vdd => vdd,
703 
    q => netops255,
704 
    i => clr);
705 
  netopi256 : buf_x2
706 
    PORT MAP (
707 
    vss => vss,
708 
    vdd => vdd,
709 
    q => netops256,
710 
    i => en);
711 
 
712 
end VST;

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