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[/] [structural_vhdl/] [trunk/] [idea_machine/] [sm16adder.vst] - Blame information for rev 4

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1 2 marta 
-- VHDL structural description generated from `sm16adder`
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--              date : Sat Sep  8 03:55:46 2001
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-- Entity Declaration
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ENTITY sm16adder IS
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  PORT (
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  a : in BIT_VECTOR (0 TO 15);  -- a
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  b : in BIT_VECTOR (0 TO 15);  -- b
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  en : in BIT;  -- en
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  clr : in BIT; -- clr
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  s : inout BIT_VECTOR (0 TO 15);       -- s
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  vdd : in BIT; -- vdd
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  vss : in BIT  -- vss
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  );
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END sm16adder;
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-- Architecture Declaration
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ARCHITECTURE VST OF sm16adder IS
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  COMPONENT m16adder_glopg
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    port (
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    a : in BIT_VECTOR(0 TO 15); -- a
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    b : in BIT_VECTOR(0 TO 15); -- b
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    s : out BIT_VECTOR(0 TO 15);        -- s
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  COMPONENT reg16_glopf
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    port (
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    d : in BIT_VECTOR(0 TO 15); -- d
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    en : in BIT;        -- en
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    clr : in BIT;       -- clr
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    q : inout BIT_VECTOR(0 TO 15);      -- q
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  SIGNAL ss_0 : BIT;    -- ss 0
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  SIGNAL ss_1 : BIT;    -- ss 1
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  SIGNAL ss_2 : BIT;    -- ss 2
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  SIGNAL ss_3 : BIT;    -- ss 3
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  SIGNAL ss_4 : BIT;    -- ss 4
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  SIGNAL ss_5 : BIT;    -- ss 5
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  SIGNAL ss_6 : BIT;    -- ss 6
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  SIGNAL ss_7 : BIT;    -- ss 7
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  SIGNAL ss_8 : BIT;    -- ss 8
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  SIGNAL ss_9 : BIT;    -- ss 9
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  SIGNAL ss_10 : BIT;   -- ss 10
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  SIGNAL ss_11 : BIT;   -- ss 11
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  SIGNAL ss_12 : BIT;   -- ss 12
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  SIGNAL ss_13 : BIT;   -- ss 13
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  SIGNAL ss_14 : BIT;   -- ss 14
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  SIGNAL ss_15 : BIT;   -- ss 15
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BEGIN
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  sm16a : m16adder_glopg
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    s => ss_0& ss_1& ss_2& ss_3& ss_4& ss_5& ss_6& ss_7& ss_8& ss_9& ss_10& ss_11& ss_12& ss_13& ss_14& ss_15,
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    b => b(0)& b(1)& b(2)& b(3)& b(4)& b(5)& b(6)& b(7)& b(8)& b(9)& b(10)& b(11)& b(12)& b(13)& b(14)& b(15),
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    a => a(0)& a(1)& a(2)& a(3)& a(4)& a(5)& a(6)& a(7)& a(8)& a(9)& a(10)& a(11)& a(12)& a(13)& a(14)& a(15));
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  rg16 : reg16_glopf
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => s(0)& s(1)& s(2)& s(3)& s(4)& s(5)& s(6)& s(7)& s(8)& s(9)& s(10)& s(11)& s(12)& s(13)& s(14)& s(15),
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    clr => clr,
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    en => en,
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    d => ss_0& ss_1& ss_2& ss_3& ss_4& ss_5& ss_6& ss_7& ss_8& ss_9& ss_10& ss_11& ss_12& ss_13& ss_14& ss_15);
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end VST;

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