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[/] [structural_vhdl/] [trunk/] [idea_machine/] [sm16adder_glopf.vst] - Blame information for rev 4

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1 2 marta 
-- VHDL structural description generated from `sm16adder_glopf`
2 
--              date : Sat Sep  8 03:56:51 2001
3 
 
4 
 
5 
-- Entity Declaration
6 
 
7 
ENTITY sm16adder_glopf IS
8 
  PORT (
9 
  a : in BIT_VECTOR (0 TO 15);  -- a
10 
  b : in BIT_VECTOR (0 TO 15);  -- b
11 
  en : in BIT;  -- en
12 
  clr : in BIT; -- clr
13 
  s : inout BIT_VECTOR (0 TO 15);       -- s
14 
  vdd : in BIT; -- vdd
15 
  vss : in BIT  -- vss
16 
  );
17 
END sm16adder_glopf;
18 
 
19 
-- Architecture Declaration
20 
 
21 
ARCHITECTURE VST OF sm16adder_glopf IS
22 
  COMPONENT o2_x2
23 
    port (
24 
    i0 : in BIT;        -- i0
25 
    i1 : in BIT;        -- i1
26 
    q : out BIT;        -- q
27 
    vdd : in BIT;       -- vdd
28 
    vss : in BIT        -- vss
29 
    );
30 
  END COMPONENT;
31 
 
32 
  COMPONENT ao22_x2
33 
    port (
34 
    i0 : in BIT;        -- i0
35 
    i1 : in BIT;        -- i1
36 
    i2 : in BIT;        -- i2
37 
    q : out BIT;        -- q
38 
    vdd : in BIT;       -- vdd
39 
    vss : in BIT        -- vss
40 
    );
41 
  END COMPONENT;
42 
 
43 
  COMPONENT xr2_x1
44 
    port (
45 
    i0 : in BIT;        -- i0
46 
    i1 : in BIT;        -- i1
47 
    q : out BIT;        -- q
48 
    vdd : in BIT;       -- vdd
49 
    vss : in BIT        -- vss
50 
    );
51 
  END COMPONENT;
52 
 
53 
  COMPONENT inv_x2
54 
    port (
55 
    i : in BIT; -- i
56 
    nq : out BIT;       -- nq
57 
    vdd : in BIT;       -- vdd
58 
    vss : in BIT        -- vss
59 
    );
60 
  END COMPONENT;
61 
 
62 
  COMPONENT a2_x2
63 
    port (
64 
    i0 : in BIT;        -- i0
65 
    i1 : in BIT;        -- i1
66 
    q : out BIT;        -- q
67 
    vdd : in BIT;       -- vdd
68 
    vss : in BIT        -- vss
69 
    );
70 
  END COMPONENT;
71 
 
72 
  COMPONENT no3_x4
73 
    port (
74 
    i0 : in BIT;        -- i0
75 
    i1 : in BIT;        -- i1
76 
    i2 : in BIT;        -- i2
77 
    nq : out BIT;       -- nq
78 
    vdd : in BIT;       -- vdd
79 
    vss : in BIT        -- vss
80 
    );
81 
  END COMPONENT;
82 
 
83 
  COMPONENT no2_x4
84 
    port (
85 
    i0 : in BIT;        -- i0
86 
    i1 : in BIT;        -- i1
87 
    nq : out BIT;       -- nq
88 
    vdd : in BIT;       -- vdd
89 
    vss : in BIT        -- vss
90 
    );
91 
  END COMPONENT;
92 
 
93 
  COMPONENT buf_x2
94 
    port (
95 
    i : in BIT; -- i
96 
    q : out BIT;        -- q
97 
    vdd : in BIT;       -- vdd
98 
    vss : in BIT        -- vss
99 
    );
100 
  END COMPONENT;
101 
 
102 
  SIGNAL netops390 : BIT;       -- netops390
103 
  SIGNAL netops389 : BIT;       -- netops389
104 
  SIGNAL netops388 : BIT;       -- netops388
105 
  SIGNAL netops387 : BIT;       -- netops387
106 
  SIGNAL netops386 : BIT;       -- netops386
107 
  SIGNAL netops385 : BIT;       -- netops385
108 
  SIGNAL netops384 : BIT;       -- netops384
109 
  SIGNAL netops383 : BIT;       -- netops383
110 
  SIGNAL netops382 : BIT;       -- netops382
111 
  SIGNAL netops381 : BIT;       -- netops381
112 
  SIGNAL netops380 : BIT;       -- netops380
113 
  SIGNAL netops379 : BIT;       -- netops379
114 
  SIGNAL netops378 : BIT;       -- netops378
115 
  SIGNAL netops377 : BIT;       -- netops377
116 
  SIGNAL netops376 : BIT;       -- netops376
117 
  SIGNAL netops375 : BIT;       -- netops375
118 
  SIGNAL netops374 : BIT;       -- netops374
119 
  SIGNAL netops373 : BIT;       -- netops373
120 
  SIGNAL netops372 : BIT;       -- netops372
121 
  SIGNAL netops371 : BIT;       -- netops371
122 
  SIGNAL netops370 : BIT;       -- netops370
123 
  SIGNAL netops369 : BIT;       -- netops369
124 
  SIGNAL netops368 : BIT;       -- netops368
125 
  SIGNAL netops367 : BIT;       -- netops367
126 
  SIGNAL netops366 : BIT;       -- netops366
127 
  SIGNAL netops365 : BIT;       -- netops365
128 
  SIGNAL netops364 : BIT;       -- netops364
129 
  SIGNAL netops363 : BIT;       -- netops363
130 
  SIGNAL ss_0 : BIT;    -- ss_0
131 
  SIGNAL ss_1 : BIT;    -- ss_1
132 
  SIGNAL ss_2 : BIT;    -- ss_2
133 
  SIGNAL ss_3 : BIT;    -- ss_3
134 
  SIGNAL ss_4 : BIT;    -- ss_4
135 
  SIGNAL ss_5 : BIT;    -- ss_5
136 
  SIGNAL ss_6 : BIT;    -- ss_6
137 
  SIGNAL ss_7 : BIT;    -- ss_7
138 
  SIGNAL ss_8 : BIT;    -- ss_8
139 
  SIGNAL ss_9 : BIT;    -- ss_9
140 
  SIGNAL ss_10 : BIT;   -- ss_10
141 
  SIGNAL ss_11 : BIT;   -- ss_11
142 
  SIGNAL ss_12 : BIT;   -- ss_12
143 
  SIGNAL ss_13 : BIT;   -- ss_13
144 
  SIGNAL ss_14 : BIT;   -- ss_14
145 
  SIGNAL ss_15 : BIT;   -- ss_15
146 
  SIGNAL sm16a_c_0 : BIT;       -- sm16a.c_0
147 
  SIGNAL sm16a_ha_netops8 : BIT;        -- sm16a.ha_netops8
148 
  SIGNAL sm16a_c_1 : BIT;       -- sm16a.c_1
149 
  SIGNAL sm16a_fa1_auxsc2 : BIT;        -- sm16a.fa1_auxsc2
150 
  SIGNAL sm16a_fa1_auxsc4 : BIT;        -- sm16a.fa1_auxsc4
151 
  SIGNAL sm16a_fa1_auxsc1 : BIT;        -- sm16a.fa1_auxsc1
152 
  SIGNAL sm16a_c_2 : BIT;       -- sm16a.c_2
153 
  SIGNAL sm16a_fa2_auxsc2 : BIT;        -- sm16a.fa2_auxsc2
154 
  SIGNAL sm16a_fa2_auxsc4 : BIT;        -- sm16a.fa2_auxsc4
155 
  SIGNAL sm16a_fa2_auxsc1 : BIT;        -- sm16a.fa2_auxsc1
156 
  SIGNAL sm16a_c_3 : BIT;       -- sm16a.c_3
157 
  SIGNAL sm16a_fa3_auxsc2 : BIT;        -- sm16a.fa3_auxsc2
158 
  SIGNAL sm16a_fa3_auxsc4 : BIT;        -- sm16a.fa3_auxsc4
159 
  SIGNAL sm16a_fa3_auxsc1 : BIT;        -- sm16a.fa3_auxsc1
160 
  SIGNAL sm16a_c_4 : BIT;       -- sm16a.c_4
161 
  SIGNAL sm16a_fa4_auxsc2 : BIT;        -- sm16a.fa4_auxsc2
162 
  SIGNAL sm16a_fa4_auxsc4 : BIT;        -- sm16a.fa4_auxsc4
163 
  SIGNAL sm16a_fa4_auxsc1 : BIT;        -- sm16a.fa4_auxsc1
164 
  SIGNAL sm16a_c_5 : BIT;       -- sm16a.c_5
165 
  SIGNAL sm16a_fa5_auxsc2 : BIT;        -- sm16a.fa5_auxsc2
166 
  SIGNAL sm16a_fa5_auxsc4 : BIT;        -- sm16a.fa5_auxsc4
167 
  SIGNAL sm16a_fa5_auxsc1 : BIT;        -- sm16a.fa5_auxsc1
168 
  SIGNAL sm16a_c_6 : BIT;       -- sm16a.c_6
169 
  SIGNAL sm16a_fa6_auxsc2 : BIT;        -- sm16a.fa6_auxsc2
170 
  SIGNAL sm16a_fa6_auxsc4 : BIT;        -- sm16a.fa6_auxsc4
171 
  SIGNAL sm16a_fa6_auxsc1 : BIT;        -- sm16a.fa6_auxsc1
172 
  SIGNAL sm16a_c_7 : BIT;       -- sm16a.c_7
173 
  SIGNAL sm16a_fa7_auxsc2 : BIT;        -- sm16a.fa7_auxsc2
174 
  SIGNAL sm16a_fa7_auxsc4 : BIT;        -- sm16a.fa7_auxsc4
175 
  SIGNAL sm16a_fa7_auxsc1 : BIT;        -- sm16a.fa7_auxsc1
176 
  SIGNAL sm16a_c_8 : BIT;       -- sm16a.c_8
177 
  SIGNAL sm16a_fa8_auxsc2 : BIT;        -- sm16a.fa8_auxsc2
178 
  SIGNAL sm16a_fa8_auxsc4 : BIT;        -- sm16a.fa8_auxsc4
179 
  SIGNAL sm16a_fa8_auxsc1 : BIT;        -- sm16a.fa8_auxsc1
180 
  SIGNAL sm16a_c_9 : BIT;       -- sm16a.c_9
181 
  SIGNAL sm16a_fa9_auxsc2 : BIT;        -- sm16a.fa9_auxsc2
182 
  SIGNAL sm16a_fa9_auxsc4 : BIT;        -- sm16a.fa9_auxsc4
183 
  SIGNAL sm16a_fa9_auxsc1 : BIT;        -- sm16a.fa9_auxsc1
184 
  SIGNAL sm16a_c_10 : BIT;      -- sm16a.c_10
185 
  SIGNAL sm16a_fa10_auxsc2 : BIT;       -- sm16a.fa10_auxsc2
186 
  SIGNAL sm16a_fa10_auxsc4 : BIT;       -- sm16a.fa10_auxsc4
187 
  SIGNAL sm16a_fa10_auxsc1 : BIT;       -- sm16a.fa10_auxsc1
188 
  SIGNAL sm16a_c_11 : BIT;      -- sm16a.c_11
189 
  SIGNAL sm16a_fa11_auxsc2 : BIT;       -- sm16a.fa11_auxsc2
190 
  SIGNAL sm16a_fa11_auxsc4 : BIT;       -- sm16a.fa11_auxsc4
191 
  SIGNAL sm16a_fa11_auxsc1 : BIT;       -- sm16a.fa11_auxsc1
192 
  SIGNAL sm16a_c_12 : BIT;      -- sm16a.c_12
193 
  SIGNAL sm16a_fa12_auxsc2 : BIT;       -- sm16a.fa12_auxsc2
194 
  SIGNAL sm16a_fa12_auxsc4 : BIT;       -- sm16a.fa12_auxsc4
195 
  SIGNAL sm16a_fa12_auxsc1 : BIT;       -- sm16a.fa12_auxsc1
196 
  SIGNAL sm16a_c_13 : BIT;      -- sm16a.c_13
197 
  SIGNAL sm16a_fa13_auxsc2 : BIT;       -- sm16a.fa13_auxsc2
198 
  SIGNAL sm16a_fa13_auxsc4 : BIT;       -- sm16a.fa13_auxsc4
199 
  SIGNAL sm16a_fa13_auxsc1 : BIT;       -- sm16a.fa13_auxsc1
200 
  SIGNAL sm16a_c_14 : BIT;      -- sm16a.c_14
201 
  SIGNAL sm16a_fa14_auxsc2 : BIT;       -- sm16a.fa14_auxsc2
202 
  SIGNAL sm16a_fa14_auxsc4 : BIT;       -- sm16a.fa14_auxsc4
203 
  SIGNAL sm16a_fa14_auxsc1 : BIT;       -- sm16a.fa14_auxsc1
204 
  SIGNAL sm16a_o_xr1 : BIT;     -- sm16a.o_xr1
205 
  SIGNAL rg16_netops256 : BIT;  -- rg16.netops256
206 
  SIGNAL rg16_netops255 : BIT;  -- rg16.netops255
207 
  SIGNAL rg16_latch0_o_nor2 : BIT;      -- rg16.latch0_o_nor2
208 
  SIGNAL rg16_latch0_o_inv : BIT;       -- rg16.latch0_o_inv
209 
  SIGNAL rg16_latch0_o_an2 : BIT;       -- rg16.latch0_o_an2
210 
  SIGNAL rg16_latch0_o_an1 : BIT;       -- rg16.latch0_o_an1
211 
  SIGNAL rg16_latch1_o_nor2 : BIT;      -- rg16.latch1_o_nor2
212 
  SIGNAL rg16_latch1_o_inv : BIT;       -- rg16.latch1_o_inv
213 
  SIGNAL rg16_latch1_o_an2 : BIT;       -- rg16.latch1_o_an2
214 
  SIGNAL rg16_latch1_o_an1 : BIT;       -- rg16.latch1_o_an1
215 
  SIGNAL rg16_latch2_o_nor2 : BIT;      -- rg16.latch2_o_nor2
216 
  SIGNAL rg16_latch2_o_inv : BIT;       -- rg16.latch2_o_inv
217 
  SIGNAL rg16_latch2_o_an2 : BIT;       -- rg16.latch2_o_an2
218 
  SIGNAL rg16_latch2_o_an1 : BIT;       -- rg16.latch2_o_an1
219 
  SIGNAL rg16_latch3_o_nor2 : BIT;      -- rg16.latch3_o_nor2
220 
  SIGNAL rg16_latch3_o_inv : BIT;       -- rg16.latch3_o_inv
221 
  SIGNAL rg16_latch3_o_an2 : BIT;       -- rg16.latch3_o_an2
222 
  SIGNAL rg16_latch3_o_an1 : BIT;       -- rg16.latch3_o_an1
223 
  SIGNAL rg16_latch4_o_nor2 : BIT;      -- rg16.latch4_o_nor2
224 
  SIGNAL rg16_latch4_o_inv : BIT;       -- rg16.latch4_o_inv
225 
  SIGNAL rg16_latch4_o_an2 : BIT;       -- rg16.latch4_o_an2
226 
  SIGNAL rg16_latch4_o_an1 : BIT;       -- rg16.latch4_o_an1
227 
  SIGNAL rg16_latch5_o_nor2 : BIT;      -- rg16.latch5_o_nor2
228 
  SIGNAL rg16_latch5_o_inv : BIT;       -- rg16.latch5_o_inv
229 
  SIGNAL rg16_latch5_o_an2 : BIT;       -- rg16.latch5_o_an2
230 
  SIGNAL rg16_latch5_o_an1 : BIT;       -- rg16.latch5_o_an1
231 
  SIGNAL rg16_latch6_o_nor2 : BIT;      -- rg16.latch6_o_nor2
232 
  SIGNAL rg16_latch6_o_inv : BIT;       -- rg16.latch6_o_inv
233 
  SIGNAL rg16_latch6_o_an2 : BIT;       -- rg16.latch6_o_an2
234 
  SIGNAL rg16_latch6_o_an1 : BIT;       -- rg16.latch6_o_an1
235 
  SIGNAL rg16_latch7_o_nor2 : BIT;      -- rg16.latch7_o_nor2
236 
  SIGNAL rg16_latch7_o_inv : BIT;       -- rg16.latch7_o_inv
237 
  SIGNAL rg16_latch7_o_an2 : BIT;       -- rg16.latch7_o_an2
238 
  SIGNAL rg16_latch7_o_an1 : BIT;       -- rg16.latch7_o_an1
239 
  SIGNAL rg16_latch8_o_nor2 : BIT;      -- rg16.latch8_o_nor2
240 
  SIGNAL rg16_latch8_o_inv : BIT;       -- rg16.latch8_o_inv
241 
  SIGNAL rg16_latch8_o_an2 : BIT;       -- rg16.latch8_o_an2
242 
  SIGNAL rg16_latch8_o_an1 : BIT;       -- rg16.latch8_o_an1
243 
  SIGNAL rg16_latch9_o_nor2 : BIT;      -- rg16.latch9_o_nor2
244 
  SIGNAL rg16_latch9_o_inv : BIT;       -- rg16.latch9_o_inv
245 
  SIGNAL rg16_latch9_o_an2 : BIT;       -- rg16.latch9_o_an2
246 
  SIGNAL rg16_latch9_o_an1 : BIT;       -- rg16.latch9_o_an1
247 
  SIGNAL rg16_latch10_o_nor2 : BIT;     -- rg16.latch10_o_nor2
248 
  SIGNAL rg16_latch10_o_inv : BIT;      -- rg16.latch10_o_inv
249 
  SIGNAL rg16_latch10_o_an2 : BIT;      -- rg16.latch10_o_an2
250 
  SIGNAL rg16_latch10_o_an1 : BIT;      -- rg16.latch10_o_an1
251 
  SIGNAL rg16_latch11_o_nor2 : BIT;     -- rg16.latch11_o_nor2
252 
  SIGNAL rg16_latch11_o_inv : BIT;      -- rg16.latch11_o_inv
253 
  SIGNAL rg16_latch11_o_an2 : BIT;      -- rg16.latch11_o_an2
254 
  SIGNAL rg16_latch11_o_an1 : BIT;      -- rg16.latch11_o_an1
255 
  SIGNAL rg16_latch12_o_nor2 : BIT;     -- rg16.latch12_o_nor2
256 
  SIGNAL rg16_latch12_o_inv : BIT;      -- rg16.latch12_o_inv
257 
  SIGNAL rg16_latch12_o_an2 : BIT;      -- rg16.latch12_o_an2
258 
  SIGNAL rg16_latch12_o_an1 : BIT;      -- rg16.latch12_o_an1
259 
  SIGNAL rg16_latch13_o_nor2 : BIT;     -- rg16.latch13_o_nor2
260 
  SIGNAL rg16_latch13_o_inv : BIT;      -- rg16.latch13_o_inv
261 
  SIGNAL rg16_latch13_o_an2 : BIT;      -- rg16.latch13_o_an2
262 
  SIGNAL rg16_latch13_o_an1 : BIT;      -- rg16.latch13_o_an1
263 
  SIGNAL rg16_latch14_o_nor2 : BIT;     -- rg16.latch14_o_nor2
264 
  SIGNAL rg16_latch14_o_inv : BIT;      -- rg16.latch14_o_inv
265 
  SIGNAL rg16_latch14_o_an2 : BIT;      -- rg16.latch14_o_an2
266 
  SIGNAL rg16_latch14_o_an1 : BIT;      -- rg16.latch14_o_an1
267 
  SIGNAL rg16_latch15_o_nor2 : BIT;     -- rg16.latch15_o_nor2
268 
  SIGNAL rg16_latch15_o_inv : BIT;      -- rg16.latch15_o_inv
269 
  SIGNAL rg16_latch15_o_an2 : BIT;      -- rg16.latch15_o_an2
270 
  SIGNAL rg16_latch15_o_an1 : BIT;      -- rg16.latch15_o_an1
271 
 
272 
BEGIN
273 
 
274 
  sm16a_ha_sout : xr2_x1
275 
    PORT MAP (
276 
    vss => vss,
277 
    vdd => vdd,
278 
    q => ss_0,
279 
    i1 => sm16a_ha_netops8,
280 
    i0 => b(0));
281 
  sm16a_ha_cout : a2_x2
282 
    PORT MAP (
283 
    vss => vss,
284 
    vdd => vdd,
285 
    q => sm16a_c_0,
286 
    i1 => sm16a_ha_netops8,
287 
    i0 => b(0));
288 
  sm16a_ha_netopi8 : buf_x2
289 
    PORT MAP (
290 
    vss => vss,
291 
    vdd => vdd,
292 
    q => sm16a_ha_netops8,
293 
    i => a(0));
294 
  sm16a_fa1_sout : xr2_x1
295 
    PORT MAP (
296 
    vss => vss,
297 
    vdd => vdd,
298 
    q => ss_1,
299 
    i1 => sm16a_fa1_auxsc1,
300 
    i0 => sm16a_c_0);
301 
  sm16a_fa1_cout : o2_x2
302 
    PORT MAP (
303 
    vss => vss,
304 
    vdd => vdd,
305 
    q => sm16a_c_1,
306 
    i1 => sm16a_fa1_auxsc2,
307 
    i0 => sm16a_fa1_auxsc4);
308 
  sm16a_fa1_auxsc2 : a2_x2
309 
    PORT MAP (
310 
    vss => vss,
311 
    vdd => vdd,
312 
    q => sm16a_fa1_auxsc2,
313 
    i1 => netops390,
314 
    i0 => netops376);
315 
  sm16a_fa1_auxsc4 : ao22_x2
316 
    PORT MAP (
317 
    vss => vss,
318 
    vdd => vdd,
319 
    q => sm16a_fa1_auxsc4,
320 
    i2 => sm16a_c_0,
321 
    i1 => netops390,
322 
    i0 => netops376);
323 
  sm16a_fa1_auxsc1 : xr2_x1
324 
    PORT MAP (
325 
    vss => vss,
326 
    vdd => vdd,
327 
    q => sm16a_fa1_auxsc1,
328 
    i1 => netops390,
329 
    i0 => netops376);
330 
  sm16a_fa2_sout : xr2_x1
331 
    PORT MAP (
332 
    vss => vss,
333 
    vdd => vdd,
334 
    q => ss_2,
335 
    i1 => sm16a_fa2_auxsc1,
336 
    i0 => sm16a_c_1);
337 
  sm16a_fa2_cout : o2_x2
338 
    PORT MAP (
339 
    vss => vss,
340 
    vdd => vdd,
341 
    q => sm16a_c_2,
342 
    i1 => sm16a_fa2_auxsc2,
343 
    i0 => sm16a_fa2_auxsc4);
344 
  sm16a_fa2_auxsc2 : a2_x2
345 
    PORT MAP (
346 
    vss => vss,
347 
    vdd => vdd,
348 
    q => sm16a_fa2_auxsc2,
349 
    i1 => netops389,
350 
    i0 => netops375);
351 
  sm16a_fa2_auxsc4 : ao22_x2
352 
    PORT MAP (
353 
    vss => vss,
354 
    vdd => vdd,
355 
    q => sm16a_fa2_auxsc4,
356 
    i2 => sm16a_c_1,
357 
    i1 => netops389,
358 
    i0 => netops375);
359 
  sm16a_fa2_auxsc1 : xr2_x1
360 
    PORT MAP (
361 
    vss => vss,
362 
    vdd => vdd,
363 
    q => sm16a_fa2_auxsc1,
364 
    i1 => netops389,
365 
    i0 => netops375);
366 
  sm16a_fa3_sout : xr2_x1
367 
    PORT MAP (
368 
    vss => vss,
369 
    vdd => vdd,
370 
    q => ss_3,
371 
    i1 => sm16a_fa3_auxsc1,
372 
    i0 => sm16a_c_2);
373 
  sm16a_fa3_cout : o2_x2
374 
    PORT MAP (
375 
    vss => vss,
376 
    vdd => vdd,
377 
    q => sm16a_c_3,
378 
    i1 => sm16a_fa3_auxsc2,
379 
    i0 => sm16a_fa3_auxsc4);
380 
  sm16a_fa3_auxsc2 : a2_x2
381 
    PORT MAP (
382 
    vss => vss,
383 
    vdd => vdd,
384 
    q => sm16a_fa3_auxsc2,
385 
    i1 => netops388,
386 
    i0 => netops374);
387 
  sm16a_fa3_auxsc4 : ao22_x2
388 
    PORT MAP (
389 
    vss => vss,
390 
    vdd => vdd,
391 
    q => sm16a_fa3_auxsc4,
392 
    i2 => sm16a_c_2,
393 
    i1 => netops388,
394 
    i0 => netops374);
395 
  sm16a_fa3_auxsc1 : xr2_x1
396 
    PORT MAP (
397 
    vss => vss,
398 
    vdd => vdd,
399 
    q => sm16a_fa3_auxsc1,
400 
    i1 => netops388,
401 
    i0 => netops374);
402 
  sm16a_fa4_sout : xr2_x1
403 
    PORT MAP (
404 
    vss => vss,
405 
    vdd => vdd,
406 
    q => ss_4,
407 
    i1 => sm16a_fa4_auxsc1,
408 
    i0 => sm16a_c_3);
409 
  sm16a_fa4_cout : o2_x2
410 
    PORT MAP (
411 
    vss => vss,
412 
    vdd => vdd,
413 
    q => sm16a_c_4,
414 
    i1 => sm16a_fa4_auxsc2,
415 
    i0 => sm16a_fa4_auxsc4);
416 
  sm16a_fa4_auxsc2 : a2_x2
417 
    PORT MAP (
418 
    vss => vss,
419 
    vdd => vdd,
420 
    q => sm16a_fa4_auxsc2,
421 
    i1 => netops387,
422 
    i0 => netops373);
423 
  sm16a_fa4_auxsc4 : ao22_x2
424 
    PORT MAP (
425 
    vss => vss,
426 
    vdd => vdd,
427 
    q => sm16a_fa4_auxsc4,
428 
    i2 => sm16a_c_3,
429 
    i1 => netops387,
430 
    i0 => netops373);
431 
  sm16a_fa4_auxsc1 : xr2_x1
432 
    PORT MAP (
433 
    vss => vss,
434 
    vdd => vdd,
435 
    q => sm16a_fa4_auxsc1,
436 
    i1 => netops387,
437 
    i0 => netops373);
438 
  sm16a_fa5_sout : xr2_x1
439 
    PORT MAP (
440 
    vss => vss,
441 
    vdd => vdd,
442 
    q => ss_5,
443 
    i1 => sm16a_fa5_auxsc1,
444 
    i0 => sm16a_c_4);
445 
  sm16a_fa5_cout : o2_x2
446 
    PORT MAP (
447 
    vss => vss,
448 
    vdd => vdd,
449 
    q => sm16a_c_5,
450 
    i1 => sm16a_fa5_auxsc2,
451 
    i0 => sm16a_fa5_auxsc4);
452 
  sm16a_fa5_auxsc2 : a2_x2
453 
    PORT MAP (
454 
    vss => vss,
455 
    vdd => vdd,
456 
    q => sm16a_fa5_auxsc2,
457 
    i1 => netops386,
458 
    i0 => netops372);
459 
  sm16a_fa5_auxsc4 : ao22_x2
460 
    PORT MAP (
461 
    vss => vss,
462 
    vdd => vdd,
463 
    q => sm16a_fa5_auxsc4,
464 
    i2 => sm16a_c_4,
465 
    i1 => netops386,
466 
    i0 => netops372);
467 
  sm16a_fa5_auxsc1 : xr2_x1
468 
    PORT MAP (
469 
    vss => vss,
470 
    vdd => vdd,
471 
    q => sm16a_fa5_auxsc1,
472 
    i1 => netops386,
473 
    i0 => netops372);
474 
  sm16a_fa6_sout : xr2_x1
475 
    PORT MAP (
476 
    vss => vss,
477 
    vdd => vdd,
478 
    q => ss_6,
479 
    i1 => sm16a_fa6_auxsc1,
480 
    i0 => sm16a_c_5);
481 
  sm16a_fa6_cout : o2_x2
482 
    PORT MAP (
483 
    vss => vss,
484 
    vdd => vdd,
485 
    q => sm16a_c_6,
486 
    i1 => sm16a_fa6_auxsc2,
487 
    i0 => sm16a_fa6_auxsc4);
488 
  sm16a_fa6_auxsc2 : a2_x2
489 
    PORT MAP (
490 
    vss => vss,
491 
    vdd => vdd,
492 
    q => sm16a_fa6_auxsc2,
493 
    i1 => netops385,
494 
    i0 => netops371);
495 
  sm16a_fa6_auxsc4 : ao22_x2
496 
    PORT MAP (
497 
    vss => vss,
498 
    vdd => vdd,
499 
    q => sm16a_fa6_auxsc4,
500 
    i2 => sm16a_c_5,
501 
    i1 => netops385,
502 
    i0 => netops371);
503 
  sm16a_fa6_auxsc1 : xr2_x1
504 
    PORT MAP (
505 
    vss => vss,
506 
    vdd => vdd,
507 
    q => sm16a_fa6_auxsc1,
508 
    i1 => netops385,
509 
    i0 => netops371);
510 
  sm16a_fa7_sout : xr2_x1
511 
    PORT MAP (
512 
    vss => vss,
513 
    vdd => vdd,
514 
    q => ss_7,
515 
    i1 => sm16a_fa7_auxsc1,
516 
    i0 => sm16a_c_6);
517 
  sm16a_fa7_cout : o2_x2
518 
    PORT MAP (
519 
    vss => vss,
520 
    vdd => vdd,
521 
    q => sm16a_c_7,
522 
    i1 => sm16a_fa7_auxsc2,
523 
    i0 => sm16a_fa7_auxsc4);
524 
  sm16a_fa7_auxsc2 : a2_x2
525 
    PORT MAP (
526 
    vss => vss,
527 
    vdd => vdd,
528 
    q => sm16a_fa7_auxsc2,
529 
    i1 => netops384,
530 
    i0 => netops370);
531 
  sm16a_fa7_auxsc4 : ao22_x2
532 
    PORT MAP (
533 
    vss => vss,
534 
    vdd => vdd,
535 
    q => sm16a_fa7_auxsc4,
536 
    i2 => sm16a_c_6,
537 
    i1 => netops384,
538 
    i0 => netops370);
539 
  sm16a_fa7_auxsc1 : xr2_x1
540 
    PORT MAP (
541 
    vss => vss,
542 
    vdd => vdd,
543 
    q => sm16a_fa7_auxsc1,
544 
    i1 => netops384,
545 
    i0 => netops370);
546 
  sm16a_fa8_sout : xr2_x1
547 
    PORT MAP (
548 
    vss => vss,
549 
    vdd => vdd,
550 
    q => ss_8,
551 
    i1 => sm16a_fa8_auxsc1,
552 
    i0 => sm16a_c_7);
553 
  sm16a_fa8_cout : o2_x2
554 
    PORT MAP (
555 
    vss => vss,
556 
    vdd => vdd,
557 
    q => sm16a_c_8,
558 
    i1 => sm16a_fa8_auxsc2,
559 
    i0 => sm16a_fa8_auxsc4);
560 
  sm16a_fa8_auxsc2 : a2_x2
561 
    PORT MAP (
562 
    vss => vss,
563 
    vdd => vdd,
564 
    q => sm16a_fa8_auxsc2,
565 
    i1 => netops383,
566 
    i0 => netops369);
567 
  sm16a_fa8_auxsc4 : ao22_x2
568 
    PORT MAP (
569 
    vss => vss,
570 
    vdd => vdd,
571 
    q => sm16a_fa8_auxsc4,
572 
    i2 => sm16a_c_7,
573 
    i1 => netops383,
574 
    i0 => netops369);
575 
  sm16a_fa8_auxsc1 : xr2_x1
576 
    PORT MAP (
577 
    vss => vss,
578 
    vdd => vdd,
579 
    q => sm16a_fa8_auxsc1,
580 
    i1 => netops383,
581 
    i0 => netops369);
582 
  sm16a_fa9_sout : xr2_x1
583 
    PORT MAP (
584 
    vss => vss,
585 
    vdd => vdd,
586 
    q => ss_9,
587 
    i1 => sm16a_fa9_auxsc1,
588 
    i0 => sm16a_c_8);
589 
  sm16a_fa9_cout : o2_x2
590 
    PORT MAP (
591 
    vss => vss,
592 
    vdd => vdd,
593 
    q => sm16a_c_9,
594 
    i1 => sm16a_fa9_auxsc2,
595 
    i0 => sm16a_fa9_auxsc4);
596 
  sm16a_fa9_auxsc2 : a2_x2
597 
    PORT MAP (
598 
    vss => vss,
599 
    vdd => vdd,
600 
    q => sm16a_fa9_auxsc2,
601 
    i1 => netops382,
602 
    i0 => netops368);
603 
  sm16a_fa9_auxsc4 : ao22_x2
604 
    PORT MAP (
605 
    vss => vss,
606 
    vdd => vdd,
607 
    q => sm16a_fa9_auxsc4,
608 
    i2 => sm16a_c_8,
609 
    i1 => netops382,
610 
    i0 => netops368);
611 
  sm16a_fa9_auxsc1 : xr2_x1
612 
    PORT MAP (
613 
    vss => vss,
614 
    vdd => vdd,
615 
    q => sm16a_fa9_auxsc1,
616 
    i1 => netops382,
617 
    i0 => netops368);
618 
  sm16a_fa10_sout : xr2_x1
619 
    PORT MAP (
620 
    vss => vss,
621 
    vdd => vdd,
622 
    q => ss_10,
623 
    i1 => sm16a_fa10_auxsc1,
624 
    i0 => sm16a_c_9);
625 
  sm16a_fa10_cout : o2_x2
626 
    PORT MAP (
627 
    vss => vss,
628 
    vdd => vdd,
629 
    q => sm16a_c_10,
630 
    i1 => sm16a_fa10_auxsc2,
631 
    i0 => sm16a_fa10_auxsc4);
632 
  sm16a_fa10_auxsc2 : a2_x2
633 
    PORT MAP (
634 
    vss => vss,
635 
    vdd => vdd,
636 
    q => sm16a_fa10_auxsc2,
637 
    i1 => netops381,
638 
    i0 => netops367);
639 
  sm16a_fa10_auxsc4 : ao22_x2
640 
    PORT MAP (
641 
    vss => vss,
642 
    vdd => vdd,
643 
    q => sm16a_fa10_auxsc4,
644 
    i2 => sm16a_c_9,
645 
    i1 => netops381,
646 
    i0 => netops367);
647 
  sm16a_fa10_auxsc1 : xr2_x1
648 
    PORT MAP (
649 
    vss => vss,
650 
    vdd => vdd,
651 
    q => sm16a_fa10_auxsc1,
652 
    i1 => netops381,
653 
    i0 => netops367);
654 
  sm16a_fa11_sout : xr2_x1
655 
    PORT MAP (
656 
    vss => vss,
657 
    vdd => vdd,
658 
    q => ss_11,
659 
    i1 => sm16a_fa11_auxsc1,
660 
    i0 => sm16a_c_10);
661 
  sm16a_fa11_cout : o2_x2
662 
    PORT MAP (
663 
    vss => vss,
664 
    vdd => vdd,
665 
    q => sm16a_c_11,
666 
    i1 => sm16a_fa11_auxsc2,
667 
    i0 => sm16a_fa11_auxsc4);
668 
  sm16a_fa11_auxsc2 : a2_x2
669 
    PORT MAP (
670 
    vss => vss,
671 
    vdd => vdd,
672 
    q => sm16a_fa11_auxsc2,
673 
    i1 => netops380,
674 
    i0 => netops366);
675 
  sm16a_fa11_auxsc4 : ao22_x2
676 
    PORT MAP (
677 
    vss => vss,
678 
    vdd => vdd,
679 
    q => sm16a_fa11_auxsc4,
680 
    i2 => sm16a_c_10,
681 
    i1 => netops380,
682 
    i0 => netops366);
683 
  sm16a_fa11_auxsc1 : xr2_x1
684 
    PORT MAP (
685 
    vss => vss,
686 
    vdd => vdd,
687 
    q => sm16a_fa11_auxsc1,
688 
    i1 => netops380,
689 
    i0 => netops366);
690 
  sm16a_fa12_sout : xr2_x1
691 
    PORT MAP (
692 
    vss => vss,
693 
    vdd => vdd,
694 
    q => ss_12,
695 
    i1 => sm16a_fa12_auxsc1,
696 
    i0 => sm16a_c_11);
697 
  sm16a_fa12_cout : o2_x2
698 
    PORT MAP (
699 
    vss => vss,
700 
    vdd => vdd,
701 
    q => sm16a_c_12,
702 
    i1 => sm16a_fa12_auxsc2,
703 
    i0 => sm16a_fa12_auxsc4);
704 
  sm16a_fa12_auxsc2 : a2_x2
705 
    PORT MAP (
706 
    vss => vss,
707 
    vdd => vdd,
708 
    q => sm16a_fa12_auxsc2,
709 
    i1 => netops379,
710 
    i0 => netops365);
711 
  sm16a_fa12_auxsc4 : ao22_x2
712 
    PORT MAP (
713 
    vss => vss,
714 
    vdd => vdd,
715 
    q => sm16a_fa12_auxsc4,
716 
    i2 => sm16a_c_11,
717 
    i1 => netops379,
718 
    i0 => netops365);
719 
  sm16a_fa12_auxsc1 : xr2_x1
720 
    PORT MAP (
721 
    vss => vss,
722 
    vdd => vdd,
723 
    q => sm16a_fa12_auxsc1,
724 
    i1 => netops379,
725 
    i0 => netops365);
726 
  sm16a_fa13_sout : xr2_x1
727 
    PORT MAP (
728 
    vss => vss,
729 
    vdd => vdd,
730 
    q => ss_13,
731 
    i1 => sm16a_fa13_auxsc1,
732 
    i0 => sm16a_c_12);
733 
  sm16a_fa13_cout : o2_x2
734 
    PORT MAP (
735 
    vss => vss,
736 
    vdd => vdd,
737 
    q => sm16a_c_13,
738 
    i1 => sm16a_fa13_auxsc2,
739 
    i0 => sm16a_fa13_auxsc4);
740 
  sm16a_fa13_auxsc2 : a2_x2
741 
    PORT MAP (
742 
    vss => vss,
743 
    vdd => vdd,
744 
    q => sm16a_fa13_auxsc2,
745 
    i1 => netops378,
746 
    i0 => netops364);
747 
  sm16a_fa13_auxsc4 : ao22_x2
748 
    PORT MAP (
749 
    vss => vss,
750 
    vdd => vdd,
751 
    q => sm16a_fa13_auxsc4,
752 
    i2 => sm16a_c_12,
753 
    i1 => netops378,
754 
    i0 => netops364);
755 
  sm16a_fa13_auxsc1 : xr2_x1
756 
    PORT MAP (
757 
    vss => vss,
758 
    vdd => vdd,
759 
    q => sm16a_fa13_auxsc1,
760 
    i1 => netops378,
761 
    i0 => netops364);
762 
  sm16a_fa14_sout : xr2_x1
763 
    PORT MAP (
764 
    vss => vss,
765 
    vdd => vdd,
766 
    q => ss_14,
767 
    i1 => sm16a_fa14_auxsc1,
768 
    i0 => sm16a_c_13);
769 
  sm16a_fa14_cout : o2_x2
770 
    PORT MAP (
771 
    vss => vss,
772 
    vdd => vdd,
773 
    q => sm16a_c_14,
774 
    i1 => sm16a_fa14_auxsc2,
775 
    i0 => sm16a_fa14_auxsc4);
776 
  sm16a_fa14_auxsc2 : a2_x2
777 
    PORT MAP (
778 
    vss => vss,
779 
    vdd => vdd,
780 
    q => sm16a_fa14_auxsc2,
781 
    i1 => netops377,
782 
    i0 => netops363);
783 
  sm16a_fa14_auxsc4 : ao22_x2
784 
    PORT MAP (
785 
    vss => vss,
786 
    vdd => vdd,
787 
    q => sm16a_fa14_auxsc4,
788 
    i2 => sm16a_c_13,
789 
    i1 => netops377,
790 
    i0 => netops363);
791 
  sm16a_fa14_auxsc1 : xr2_x1
792 
    PORT MAP (
793 
    vss => vss,
794 
    vdd => vdd,
795 
    q => sm16a_fa14_auxsc1,
796 
    i1 => netops377,
797 
    i0 => netops363);
798 
  sm16a_xr1 : xr2_x1
799 
    PORT MAP (
800 
    vss => vss,
801 
    vdd => vdd,
802 
    q => sm16a_o_xr1,
803 
    i1 => b(15),
804 
    i0 => a(15));
805 
  sm16a_xr2 : xr2_x1
806 
    PORT MAP (
807 
    vss => vss,
808 
    vdd => vdd,
809 
    q => ss_15,
810 
    i1 => sm16a_c_14,
811 
    i0 => sm16a_o_xr1);
812 
  rg16_latch0_inv : inv_x2
813 
    PORT MAP (
814 
    vss => vss,
815 
    vdd => vdd,
816 
    nq => rg16_latch0_o_inv,
817 
    i => ss_0);
818 
  rg16_latch0_an1 : a2_x2
819 
    PORT MAP (
820 
    vss => vss,
821 
    vdd => vdd,
822 
    q => rg16_latch0_o_an1,
823 
    i1 => rg16_netops256,
824 
    i0 => rg16_latch0_o_inv);
825 
  rg16_latch0_an2 : a2_x2
826 
    PORT MAP (
827 
    vss => vss,
828 
    vdd => vdd,
829 
    q => rg16_latch0_o_an2,
830 
    i1 => rg16_netops256,
831 
    i0 => ss_0);
832 
  rg16_latch0_nor1 : no3_x4
833 
    PORT MAP (
834 
    vss => vss,
835 
    vdd => vdd,
836 
    nq => s(0),
837 
    i2 => rg16_latch0_o_nor2,
838 
    i1 => rg16_netops255,
839 
    i0 => rg16_latch0_o_an1);
840 
  rg16_latch0_nor2 : no2_x4
841 
    PORT MAP (
842 
    vss => vss,
843 
    vdd => vdd,
844 
    nq => rg16_latch0_o_nor2,
845 
    i1 => rg16_latch0_o_an2,
846 
    i0 => s(0));
847 
  rg16_latch1_inv : inv_x2
848 
    PORT MAP (
849 
    vss => vss,
850 
    vdd => vdd,
851 
    nq => rg16_latch1_o_inv,
852 
    i => ss_1);
853 
  rg16_latch1_an1 : a2_x2
854 
    PORT MAP (
855 
    vss => vss,
856 
    vdd => vdd,
857 
    q => rg16_latch1_o_an1,
858 
    i1 => rg16_netops256,
859 
    i0 => rg16_latch1_o_inv);
860 
  rg16_latch1_an2 : a2_x2
861 
    PORT MAP (
862 
    vss => vss,
863 
    vdd => vdd,
864 
    q => rg16_latch1_o_an2,
865 
    i1 => rg16_netops256,
866 
    i0 => ss_1);
867 
  rg16_latch1_nor1 : no3_x4
868 
    PORT MAP (
869 
    vss => vss,
870 
    vdd => vdd,
871 
    nq => s(1),
872 
    i2 => rg16_latch1_o_nor2,
873 
    i1 => rg16_netops255,
874 
    i0 => rg16_latch1_o_an1);
875 
  rg16_latch1_nor2 : no2_x4
876 
    PORT MAP (
877 
    vss => vss,
878 
    vdd => vdd,
879 
    nq => rg16_latch1_o_nor2,
880 
    i1 => rg16_latch1_o_an2,
881 
    i0 => s(1));
882 
  rg16_latch2_inv : inv_x2
883 
    PORT MAP (
884 
    vss => vss,
885 
    vdd => vdd,
886 
    nq => rg16_latch2_o_inv,
887 
    i => ss_2);
888 
  rg16_latch2_an1 : a2_x2
889 
    PORT MAP (
890 
    vss => vss,
891 
    vdd => vdd,
892 
    q => rg16_latch2_o_an1,
893 
    i1 => rg16_netops256,
894 
    i0 => rg16_latch2_o_inv);
895 
  rg16_latch2_an2 : a2_x2
896 
    PORT MAP (
897 
    vss => vss,
898 
    vdd => vdd,
899 
    q => rg16_latch2_o_an2,
900 
    i1 => rg16_netops256,
901 
    i0 => ss_2);
902 
  rg16_latch2_nor1 : no3_x4
903 
    PORT MAP (
904 
    vss => vss,
905 
    vdd => vdd,
906 
    nq => s(2),
907 
    i2 => rg16_latch2_o_nor2,
908 
    i1 => rg16_netops255,
909 
    i0 => rg16_latch2_o_an1);
910 
  rg16_latch2_nor2 : no2_x4
911 
    PORT MAP (
912 
    vss => vss,
913 
    vdd => vdd,
914 
    nq => rg16_latch2_o_nor2,
915 
    i1 => rg16_latch2_o_an2,
916 
    i0 => s(2));
917 
  rg16_latch3_inv : inv_x2
918 
    PORT MAP (
919 
    vss => vss,
920 
    vdd => vdd,
921 
    nq => rg16_latch3_o_inv,
922 
    i => ss_3);
923 
  rg16_latch3_an1 : a2_x2
924 
    PORT MAP (
925 
    vss => vss,
926 
    vdd => vdd,
927 
    q => rg16_latch3_o_an1,
928 
    i1 => rg16_netops256,
929 
    i0 => rg16_latch3_o_inv);
930 
  rg16_latch3_an2 : a2_x2
931 
    PORT MAP (
932 
    vss => vss,
933 
    vdd => vdd,
934 
    q => rg16_latch3_o_an2,
935 
    i1 => rg16_netops256,
936 
    i0 => ss_3);
937 
  rg16_latch3_nor1 : no3_x4
938 
    PORT MAP (
939 
    vss => vss,
940 
    vdd => vdd,
941 
    nq => s(3),
942 
    i2 => rg16_latch3_o_nor2,
943 
    i1 => rg16_netops255,
944 
    i0 => rg16_latch3_o_an1);
945 
  rg16_latch3_nor2 : no2_x4
946 
    PORT MAP (
947 
    vss => vss,
948 
    vdd => vdd,
949 
    nq => rg16_latch3_o_nor2,
950 
    i1 => rg16_latch3_o_an2,
951 
    i0 => s(3));
952 
  rg16_latch4_inv : inv_x2
953 
    PORT MAP (
954 
    vss => vss,
955 
    vdd => vdd,
956 
    nq => rg16_latch4_o_inv,
957 
    i => ss_4);
958 
  rg16_latch4_an1 : a2_x2
959 
    PORT MAP (
960 
    vss => vss,
961 
    vdd => vdd,
962 
    q => rg16_latch4_o_an1,
963 
    i1 => rg16_netops256,
964 
    i0 => rg16_latch4_o_inv);
965 
  rg16_latch4_an2 : a2_x2
966 
    PORT MAP (
967 
    vss => vss,
968 
    vdd => vdd,
969 
    q => rg16_latch4_o_an2,
970 
    i1 => rg16_netops256,
971 
    i0 => ss_4);
972 
  rg16_latch4_nor1 : no3_x4
973 
    PORT MAP (
974 
    vss => vss,
975 
    vdd => vdd,
976 
    nq => s(4),
977 
    i2 => rg16_latch4_o_nor2,
978 
    i1 => rg16_netops255,
979 
    i0 => rg16_latch4_o_an1);
980 
  rg16_latch4_nor2 : no2_x4
981 
    PORT MAP (
982 
    vss => vss,
983 
    vdd => vdd,
984 
    nq => rg16_latch4_o_nor2,
985 
    i1 => rg16_latch4_o_an2,
986 
    i0 => s(4));
987 
  rg16_latch5_inv : inv_x2
988 
    PORT MAP (
989 
    vss => vss,
990 
    vdd => vdd,
991 
    nq => rg16_latch5_o_inv,
992 
    i => ss_5);
993 
  rg16_latch5_an1 : a2_x2
994 
    PORT MAP (
995 
    vss => vss,
996 
    vdd => vdd,
997 
    q => rg16_latch5_o_an1,
998 
    i1 => rg16_netops256,
999 
    i0 => rg16_latch5_o_inv);
1000 
  rg16_latch5_an2 : a2_x2
1001 
    PORT MAP (
1002 
    vss => vss,
1003 
    vdd => vdd,
1004 
    q => rg16_latch5_o_an2,
1005 
    i1 => rg16_netops256,
1006 
    i0 => ss_5);
1007 
  rg16_latch5_nor1 : no3_x4
1008 
    PORT MAP (
1009 
    vss => vss,
1010 
    vdd => vdd,
1011 
    nq => s(5),
1012 
    i2 => rg16_latch5_o_nor2,
1013 
    i1 => rg16_netops255,
1014 
    i0 => rg16_latch5_o_an1);
1015 
  rg16_latch5_nor2 : no2_x4
1016 
    PORT MAP (
1017 
    vss => vss,
1018 
    vdd => vdd,
1019 
    nq => rg16_latch5_o_nor2,
1020 
    i1 => rg16_latch5_o_an2,
1021 
    i0 => s(5));
1022 
  rg16_latch6_inv : inv_x2
1023 
    PORT MAP (
1024 
    vss => vss,
1025 
    vdd => vdd,
1026 
    nq => rg16_latch6_o_inv,
1027 
    i => ss_6);
1028 
  rg16_latch6_an1 : a2_x2
1029 
    PORT MAP (
1030 
    vss => vss,
1031 
    vdd => vdd,
1032 
    q => rg16_latch6_o_an1,
1033 
    i1 => rg16_netops256,
1034 
    i0 => rg16_latch6_o_inv);
1035 
  rg16_latch6_an2 : a2_x2
1036 
    PORT MAP (
1037 
    vss => vss,
1038 
    vdd => vdd,
1039 
    q => rg16_latch6_o_an2,
1040 
    i1 => rg16_netops256,
1041 
    i0 => ss_6);
1042 
  rg16_latch6_nor1 : no3_x4
1043 
    PORT MAP (
1044 
    vss => vss,
1045 
    vdd => vdd,
1046 
    nq => s(6),
1047 
    i2 => rg16_latch6_o_nor2,
1048 
    i1 => rg16_netops255,
1049 
    i0 => rg16_latch6_o_an1);
1050 
  rg16_latch6_nor2 : no2_x4
1051 
    PORT MAP (
1052 
    vss => vss,
1053 
    vdd => vdd,
1054 
    nq => rg16_latch6_o_nor2,
1055 
    i1 => rg16_latch6_o_an2,
1056 
    i0 => s(6));
1057 
  rg16_latch7_inv : inv_x2
1058 
    PORT MAP (
1059 
    vss => vss,
1060 
    vdd => vdd,
1061 
    nq => rg16_latch7_o_inv,
1062 
    i => ss_7);
1063 
  rg16_latch7_an1 : a2_x2
1064 
    PORT MAP (
1065 
    vss => vss,
1066 
    vdd => vdd,
1067 
    q => rg16_latch7_o_an1,
1068 
    i1 => rg16_netops256,
1069 
    i0 => rg16_latch7_o_inv);
1070 
  rg16_latch7_an2 : a2_x2
1071 
    PORT MAP (
1072 
    vss => vss,
1073 
    vdd => vdd,
1074 
    q => rg16_latch7_o_an2,
1075 
    i1 => rg16_netops256,
1076 
    i0 => ss_7);
1077 
  rg16_latch7_nor1 : no3_x4
1078 
    PORT MAP (
1079 
    vss => vss,
1080 
    vdd => vdd,
1081 
    nq => s(7),
1082 
    i2 => rg16_latch7_o_nor2,
1083 
    i1 => rg16_netops255,
1084 
    i0 => rg16_latch7_o_an1);
1085 
  rg16_latch7_nor2 : no2_x4
1086 
    PORT MAP (
1087 
    vss => vss,
1088 
    vdd => vdd,
1089 
    nq => rg16_latch7_o_nor2,
1090 
    i1 => rg16_latch7_o_an2,
1091 
    i0 => s(7));
1092 
  rg16_latch8_inv : inv_x2
1093 
    PORT MAP (
1094 
    vss => vss,
1095 
    vdd => vdd,
1096 
    nq => rg16_latch8_o_inv,
1097 
    i => ss_8);
1098 
  rg16_latch8_an1 : a2_x2
1099 
    PORT MAP (
1100 
    vss => vss,
1101 
    vdd => vdd,
1102 
    q => rg16_latch8_o_an1,
1103 
    i1 => rg16_netops256,
1104 
    i0 => rg16_latch8_o_inv);
1105 
  rg16_latch8_an2 : a2_x2
1106 
    PORT MAP (
1107 
    vss => vss,
1108 
    vdd => vdd,
1109 
    q => rg16_latch8_o_an2,
1110 
    i1 => rg16_netops256,
1111 
    i0 => ss_8);
1112 
  rg16_latch8_nor1 : no3_x4
1113 
    PORT MAP (
1114 
    vss => vss,
1115 
    vdd => vdd,
1116 
    nq => s(8),
1117 
    i2 => rg16_latch8_o_nor2,
1118 
    i1 => rg16_netops255,
1119 
    i0 => rg16_latch8_o_an1);
1120 
  rg16_latch8_nor2 : no2_x4
1121 
    PORT MAP (
1122 
    vss => vss,
1123 
    vdd => vdd,
1124 
    nq => rg16_latch8_o_nor2,
1125 
    i1 => rg16_latch8_o_an2,
1126 
    i0 => s(8));
1127 
  rg16_latch9_inv : inv_x2
1128 
    PORT MAP (
1129 
    vss => vss,
1130 
    vdd => vdd,
1131 
    nq => rg16_latch9_o_inv,
1132 
    i => ss_9);
1133 
  rg16_latch9_an1 : a2_x2
1134 
    PORT MAP (
1135 
    vss => vss,
1136 
    vdd => vdd,
1137 
    q => rg16_latch9_o_an1,
1138 
    i1 => rg16_netops256,
1139 
    i0 => rg16_latch9_o_inv);
1140 
  rg16_latch9_an2 : a2_x2
1141 
    PORT MAP (
1142 
    vss => vss,
1143 
    vdd => vdd,
1144 
    q => rg16_latch9_o_an2,
1145 
    i1 => rg16_netops256,
1146 
    i0 => ss_9);
1147 
  rg16_latch9_nor1 : no3_x4
1148 
    PORT MAP (
1149 
    vss => vss,
1150 
    vdd => vdd,
1151 
    nq => s(9),
1152 
    i2 => rg16_latch9_o_nor2,
1153 
    i1 => rg16_netops255,
1154 
    i0 => rg16_latch9_o_an1);
1155 
  rg16_latch9_nor2 : no2_x4
1156 
    PORT MAP (
1157 
    vss => vss,
1158 
    vdd => vdd,
1159 
    nq => rg16_latch9_o_nor2,
1160 
    i1 => rg16_latch9_o_an2,
1161 
    i0 => s(9));
1162 
  rg16_latch10_inv : inv_x2
1163 
    PORT MAP (
1164 
    vss => vss,
1165 
    vdd => vdd,
1166 
    nq => rg16_latch10_o_inv,
1167 
    i => ss_10);
1168 
  rg16_latch10_an1 : a2_x2
1169 
    PORT MAP (
1170 
    vss => vss,
1171 
    vdd => vdd,
1172 
    q => rg16_latch10_o_an1,
1173 
    i1 => rg16_netops256,
1174 
    i0 => rg16_latch10_o_inv);
1175 
  rg16_latch10_an2 : a2_x2
1176 
    PORT MAP (
1177 
    vss => vss,
1178 
    vdd => vdd,
1179 
    q => rg16_latch10_o_an2,
1180 
    i1 => rg16_netops256,
1181 
    i0 => ss_10);
1182 
  rg16_latch10_nor1 : no3_x4
1183 
    PORT MAP (
1184 
    vss => vss,
1185 
    vdd => vdd,
1186 
    nq => s(10),
1187 
    i2 => rg16_latch10_o_nor2,
1188 
    i1 => rg16_netops255,
1189 
    i0 => rg16_latch10_o_an1);
1190 
  rg16_latch10_nor2 : no2_x4
1191 
    PORT MAP (
1192 
    vss => vss,
1193 
    vdd => vdd,
1194 
    nq => rg16_latch10_o_nor2,
1195 
    i1 => rg16_latch10_o_an2,
1196 
    i0 => s(10));
1197 
  rg16_latch11_inv : inv_x2
1198 
    PORT MAP (
1199 
    vss => vss,
1200 
    vdd => vdd,
1201 
    nq => rg16_latch11_o_inv,
1202 
    i => ss_11);
1203 
  rg16_latch11_an1 : a2_x2
1204 
    PORT MAP (
1205 
    vss => vss,
1206 
    vdd => vdd,
1207 
    q => rg16_latch11_o_an1,
1208 
    i1 => rg16_netops256,
1209 
    i0 => rg16_latch11_o_inv);
1210 
  rg16_latch11_an2 : a2_x2
1211 
    PORT MAP (
1212 
    vss => vss,
1213 
    vdd => vdd,
1214 
    q => rg16_latch11_o_an2,
1215 
    i1 => rg16_netops256,
1216 
    i0 => ss_11);
1217 
  rg16_latch11_nor1 : no3_x4
1218 
    PORT MAP (
1219 
    vss => vss,
1220 
    vdd => vdd,
1221 
    nq => s(11),
1222 
    i2 => rg16_latch11_o_nor2,
1223 
    i1 => rg16_netops255,
1224 
    i0 => rg16_latch11_o_an1);
1225 
  rg16_latch11_nor2 : no2_x4
1226 
    PORT MAP (
1227 
    vss => vss,
1228 
    vdd => vdd,
1229 
    nq => rg16_latch11_o_nor2,
1230 
    i1 => rg16_latch11_o_an2,
1231 
    i0 => s(11));
1232 
  rg16_latch12_inv : inv_x2
1233 
    PORT MAP (
1234 
    vss => vss,
1235 
    vdd => vdd,
1236 
    nq => rg16_latch12_o_inv,
1237 
    i => ss_12);
1238 
  rg16_latch12_an1 : a2_x2
1239 
    PORT MAP (
1240 
    vss => vss,
1241 
    vdd => vdd,
1242 
    q => rg16_latch12_o_an1,
1243 
    i1 => rg16_netops256,
1244 
    i0 => rg16_latch12_o_inv);
1245 
  rg16_latch12_an2 : a2_x2
1246 
    PORT MAP (
1247 
    vss => vss,
1248 
    vdd => vdd,
1249 
    q => rg16_latch12_o_an2,
1250 
    i1 => rg16_netops256,
1251 
    i0 => ss_12);
1252 
  rg16_latch12_nor1 : no3_x4
1253 
    PORT MAP (
1254 
    vss => vss,
1255 
    vdd => vdd,
1256 
    nq => s(12),
1257 
    i2 => rg16_latch12_o_nor2,
1258 
    i1 => rg16_netops255,
1259 
    i0 => rg16_latch12_o_an1);
1260 
  rg16_latch12_nor2 : no2_x4
1261 
    PORT MAP (
1262 
    vss => vss,
1263 
    vdd => vdd,
1264 
    nq => rg16_latch12_o_nor2,
1265 
    i1 => rg16_latch12_o_an2,
1266 
    i0 => s(12));
1267 
  rg16_latch13_inv : inv_x2
1268 
    PORT MAP (
1269 
    vss => vss,
1270 
    vdd => vdd,
1271 
    nq => rg16_latch13_o_inv,
1272 
    i => ss_13);
1273 
  rg16_latch13_an1 : a2_x2
1274 
    PORT MAP (
1275 
    vss => vss,
1276 
    vdd => vdd,
1277 
    q => rg16_latch13_o_an1,
1278 
    i1 => rg16_netops256,
1279 
    i0 => rg16_latch13_o_inv);
1280 
  rg16_latch13_an2 : a2_x2
1281 
    PORT MAP (
1282 
    vss => vss,
1283 
    vdd => vdd,
1284 
    q => rg16_latch13_o_an2,
1285 
    i1 => rg16_netops256,
1286 
    i0 => ss_13);
1287 
  rg16_latch13_nor1 : no3_x4
1288 
    PORT MAP (
1289 
    vss => vss,
1290 
    vdd => vdd,
1291 
    nq => s(13),
1292 
    i2 => rg16_latch13_o_nor2,
1293 
    i1 => rg16_netops255,
1294 
    i0 => rg16_latch13_o_an1);
1295 
  rg16_latch13_nor2 : no2_x4
1296 
    PORT MAP (
1297 
    vss => vss,
1298 
    vdd => vdd,
1299 
    nq => rg16_latch13_o_nor2,
1300 
    i1 => rg16_latch13_o_an2,
1301 
    i0 => s(13));
1302 
  rg16_latch14_inv : inv_x2
1303 
    PORT MAP (
1304 
    vss => vss,
1305 
    vdd => vdd,
1306 
    nq => rg16_latch14_o_inv,
1307 
    i => ss_14);
1308 
  rg16_latch14_an1 : a2_x2
1309 
    PORT MAP (
1310 
    vss => vss,
1311 
    vdd => vdd,
1312 
    q => rg16_latch14_o_an1,
1313 
    i1 => rg16_netops256,
1314 
    i0 => rg16_latch14_o_inv);
1315 
  rg16_latch14_an2 : a2_x2
1316 
    PORT MAP (
1317 
    vss => vss,
1318 
    vdd => vdd,
1319 
    q => rg16_latch14_o_an2,
1320 
    i1 => rg16_netops256,
1321 
    i0 => ss_14);
1322 
  rg16_latch14_nor1 : no3_x4
1323 
    PORT MAP (
1324 
    vss => vss,
1325 
    vdd => vdd,
1326 
    nq => s(14),
1327 
    i2 => rg16_latch14_o_nor2,
1328 
    i1 => rg16_netops255,
1329 
    i0 => rg16_latch14_o_an1);
1330 
  rg16_latch14_nor2 : no2_x4
1331 
    PORT MAP (
1332 
    vss => vss,
1333 
    vdd => vdd,
1334 
    nq => rg16_latch14_o_nor2,
1335 
    i1 => rg16_latch14_o_an2,
1336 
    i0 => s(14));
1337 
  rg16_latch15_inv : inv_x2
1338 
    PORT MAP (
1339 
    vss => vss,
1340 
    vdd => vdd,
1341 
    nq => rg16_latch15_o_inv,
1342 
    i => ss_15);
1343 
  rg16_latch15_an1 : a2_x2
1344 
    PORT MAP (
1345 
    vss => vss,
1346 
    vdd => vdd,
1347 
    q => rg16_latch15_o_an1,
1348 
    i1 => rg16_netops256,
1349 
    i0 => rg16_latch15_o_inv);
1350 
  rg16_latch15_an2 : a2_x2
1351 
    PORT MAP (
1352 
    vss => vss,
1353 
    vdd => vdd,
1354 
    q => rg16_latch15_o_an2,
1355 
    i1 => rg16_netops256,
1356 
    i0 => ss_15);
1357 
  rg16_latch15_nor1 : no3_x4
1358 
    PORT MAP (
1359 
    vss => vss,
1360 
    vdd => vdd,
1361 
    nq => s(15),
1362 
    i2 => rg16_latch15_o_nor2,
1363 
    i1 => rg16_netops255,
1364 
    i0 => rg16_latch15_o_an1);
1365 
  rg16_latch15_nor2 : no2_x4
1366 
    PORT MAP (
1367 
    vss => vss,
1368 
    vdd => vdd,
1369 
    nq => rg16_latch15_o_nor2,
1370 
    i1 => rg16_latch15_o_an2,
1371 
    i0 => s(15));
1372 
  rg16_netopi255 : buf_x2
1373 
    PORT MAP (
1374 
    vss => vss,
1375 
    vdd => vdd,
1376 
    q => rg16_netops255,
1377 
    i => clr);
1378 
  rg16_netopi256 : buf_x2
1379 
    PORT MAP (
1380 
    vss => vss,
1381 
    vdd => vdd,
1382 
    q => rg16_netops256,
1383 
    i => en);
1384 
  netopi363 : buf_x2
1385 
    PORT MAP (
1386 
    vss => vss,
1387 
    vdd => vdd,
1388 
    q => netops363,
1389 
    i => b(14));
1390 
  netopi364 : buf_x2
1391 
    PORT MAP (
1392 
    vss => vss,
1393 
    vdd => vdd,
1394 
    q => netops364,
1395 
    i => b(13));
1396 
  netopi365 : buf_x2
1397 
    PORT MAP (
1398 
    vss => vss,
1399 
    vdd => vdd,
1400 
    q => netops365,
1401 
    i => b(12));
1402 
  netopi366 : buf_x2
1403 
    PORT MAP (
1404 
    vss => vss,
1405 
    vdd => vdd,
1406 
    q => netops366,
1407 
    i => b(11));
1408 
  netopi367 : buf_x2
1409 
    PORT MAP (
1410 
    vss => vss,
1411 
    vdd => vdd,
1412 
    q => netops367,
1413 
    i => b(10));
1414 
  netopi368 : buf_x2
1415 
    PORT MAP (
1416 
    vss => vss,
1417 
    vdd => vdd,
1418 
    q => netops368,
1419 
    i => b(9));
1420 
  netopi369 : buf_x2
1421 
    PORT MAP (
1422 
    vss => vss,
1423 
    vdd => vdd,
1424 
    q => netops369,
1425 
    i => b(8));
1426 
  netopi370 : buf_x2
1427 
    PORT MAP (
1428 
    vss => vss,
1429 
    vdd => vdd,
1430 
    q => netops370,
1431 
    i => b(7));
1432 
  netopi371 : buf_x2
1433 
    PORT MAP (
1434 
    vss => vss,
1435 
    vdd => vdd,
1436 
    q => netops371,
1437 
    i => b(6));
1438 
  netopi372 : buf_x2
1439 
    PORT MAP (
1440 
    vss => vss,
1441 
    vdd => vdd,
1442 
    q => netops372,
1443 
    i => b(5));
1444 
  netopi373 : buf_x2
1445 
    PORT MAP (
1446 
    vss => vss,
1447 
    vdd => vdd,
1448 
    q => netops373,
1449 
    i => b(4));
1450 
  netopi374 : buf_x2
1451 
    PORT MAP (
1452 
    vss => vss,
1453 
    vdd => vdd,
1454 
    q => netops374,
1455 
    i => b(3));
1456 
  netopi375 : buf_x2
1457 
    PORT MAP (
1458 
    vss => vss,
1459 
    vdd => vdd,
1460 
    q => netops375,
1461 
    i => b(2));
1462 
  netopi376 : buf_x2
1463 
    PORT MAP (
1464 
    vss => vss,
1465 
    vdd => vdd,
1466 
    q => netops376,
1467 
    i => b(1));
1468 
  netopi377 : buf_x2
1469 
    PORT MAP (
1470 
    vss => vss,
1471 
    vdd => vdd,
1472 
    q => netops377,
1473 
    i => a(14));
1474 
  netopi378 : buf_x2
1475 
    PORT MAP (
1476 
    vss => vss,
1477 
    vdd => vdd,
1478 
    q => netops378,
1479 
    i => a(13));
1480 
  netopi379 : buf_x2
1481 
    PORT MAP (
1482 
    vss => vss,
1483 
    vdd => vdd,
1484 
    q => netops379,
1485 
    i => a(12));
1486 
  netopi380 : buf_x2
1487 
    PORT MAP (
1488 
    vss => vss,
1489 
    vdd => vdd,
1490 
    q => netops380,
1491 
    i => a(11));
1492 
  netopi381 : buf_x2
1493 
    PORT MAP (
1494 
    vss => vss,
1495 
    vdd => vdd,
1496 
    q => netops381,
1497 
    i => a(10));
1498 
  netopi382 : buf_x2
1499 
    PORT MAP (
1500 
    vss => vss,
1501 
    vdd => vdd,
1502 
    q => netops382,
1503 
    i => a(9));
1504 
  netopi383 : buf_x2
1505 
    PORT MAP (
1506 
    vss => vss,
1507 
    vdd => vdd,
1508 
    q => netops383,
1509 
    i => a(8));
1510 
  netopi384 : buf_x2
1511 
    PORT MAP (
1512 
    vss => vss,
1513 
    vdd => vdd,
1514 
    q => netops384,
1515 
    i => a(7));
1516 
  netopi385 : buf_x2
1517 
    PORT MAP (
1518 
    vss => vss,
1519 
    vdd => vdd,
1520 
    q => netops385,
1521 
    i => a(6));
1522 
  netopi386 : buf_x2
1523 
    PORT MAP (
1524 
    vss => vss,
1525 
    vdd => vdd,
1526 
    q => netops386,
1527 
    i => a(5));
1528 
  netopi387 : buf_x2
1529 
    PORT MAP (
1530 
    vss => vss,
1531 
    vdd => vdd,
1532 
    q => netops387,
1533 
    i => a(4));
1534 
  netopi388 : buf_x2
1535 
    PORT MAP (
1536 
    vss => vss,
1537 
    vdd => vdd,
1538 
    q => netops388,
1539 
    i => a(3));
1540 
  netopi389 : buf_x2
1541 
    PORT MAP (
1542 
    vss => vss,
1543 
    vdd => vdd,
1544 
    q => netops389,
1545 
    i => a(2));
1546 
  netopi390 : buf_x2
1547 
    PORT MAP (
1548 
    vss => vss,
1549 
    vdd => vdd,
1550 
    q => netops390,
1551 
    i => a(1));
1552 
 
1553 
end VST;

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