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[/] [structural_vhdl/] [trunk/] [idea_machine/] [sm16plus1mul.vst] - Blame information for rev 4

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-- VHDL structural description generated from `sm16plus1mul`
--              date : Sat Sep  8 04:28:34 2001
 
 
-- Entity Declaration
 
ENTITY sm16plus1mul IS
  PORT (
  in1 : in BIT_VECTOR (0 TO 15);        -- in1
  in2 : in BIT_VECTOR (0 TO 15);        -- in2
  en : in BIT;  -- en
  clr : in BIT; -- clr
  mulout : out BIT_VECTOR (0 TO 15);    -- mulout
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END sm16plus1mul;
 
-- Architecture Declaration
 
ARCHITECTURE VST OF sm16plus1mul IS
  COMPONENT comp1_glopg
    port (
    kin : in BIT_VECTOR(15 DOWNTO 0);   -- kin
    kout1 : out BIT_VECTOR(16 DOWNTO 0);        -- kout1
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT mul17_glopg
    port (
    a : in BIT_VECTOR(16 DOWNTO 0);     -- a
    b : in BIT_VECTOR(16 DOWNTO 0);     -- b
    sum : out BIT_VECTOR(31 DOWNTO 0);  -- sum
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT comp2_glopg
    port (
    vss : in BIT;       -- vss
    vdd : in BIT;       -- vdd
    kout2 : out BIT_VECTOR(0 TO 15);    -- kout2
    q : in BIT_VECTOR(0 TO 15); -- q
    p : in BIT_VECTOR(0 TO 15)  -- p
    );
  END COMPONENT;
 
  COMPONENT subtract16_glopg
    port (
    a : in BIT_VECTOR(0 TO 15); -- a
    b : in BIT_VECTOR(0 TO 15); -- b
    s : out BIT_VECTOR(0 TO 15);        -- s
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT reg16_glopf
    port (
    d : in BIT_VECTOR(0 TO 15); -- d
    en : in BIT;        -- en
    clr : in BIT;       -- clr
    q : inout BIT_VECTOR(0 TO 15);      -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT m16adder_glopg
    port (
    a : in BIT_VECTOR(0 TO 15); -- a
    b : in BIT_VECTOR(0 TO 15); -- b
    s : out BIT_VECTOR(0 TO 15);        -- s
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  SIGNAL dif_0 : BIT;   -- dif 0
  SIGNAL dif_1 : BIT;   -- dif 1
  SIGNAL dif_2 : BIT;   -- dif 2
  SIGNAL dif_3 : BIT;   -- dif 3
  SIGNAL dif_4 : BIT;   -- dif 4
  SIGNAL dif_5 : BIT;   -- dif 5
  SIGNAL dif_6 : BIT;   -- dif 6
  SIGNAL dif_7 : BIT;   -- dif 7
  SIGNAL dif_8 : BIT;   -- dif 8
  SIGNAL dif_9 : BIT;   -- dif 9
  SIGNAL dif_10 : BIT;  -- dif 10
  SIGNAL dif_11 : BIT;  -- dif 11
  SIGNAL dif_12 : BIT;  -- dif 12
  SIGNAL dif_13 : BIT;  -- dif 13
  SIGNAL dif_14 : BIT;  -- dif 14
  SIGNAL dif_15 : BIT;  -- dif 15
  SIGNAL kout1a_0 : BIT;        -- kout1a 0
  SIGNAL kout1a_1 : BIT;        -- kout1a 1
  SIGNAL kout1a_2 : BIT;        -- kout1a 2
  SIGNAL kout1a_3 : BIT;        -- kout1a 3
  SIGNAL kout1a_4 : BIT;        -- kout1a 4
  SIGNAL kout1a_5 : BIT;        -- kout1a 5
  SIGNAL kout1a_6 : BIT;        -- kout1a 6
  SIGNAL kout1a_7 : BIT;        -- kout1a 7
  SIGNAL kout1a_8 : BIT;        -- kout1a 8
  SIGNAL kout1a_9 : BIT;        -- kout1a 9
  SIGNAL kout1a_10 : BIT;       -- kout1a 10
  SIGNAL kout1a_11 : BIT;       -- kout1a 11
  SIGNAL kout1a_12 : BIT;       -- kout1a 12
  SIGNAL kout1a_13 : BIT;       -- kout1a 13
  SIGNAL kout1a_14 : BIT;       -- kout1a 14
  SIGNAL kout1a_15 : BIT;       -- kout1a 15
  SIGNAL kout1a_16 : BIT;       -- kout1a 16
  SIGNAL kout1b_0 : BIT;        -- kout1b 0
  SIGNAL kout1b_1 : BIT;        -- kout1b 1
  SIGNAL kout1b_2 : BIT;        -- kout1b 2
  SIGNAL kout1b_3 : BIT;        -- kout1b 3
  SIGNAL kout1b_4 : BIT;        -- kout1b 4
  SIGNAL kout1b_5 : BIT;        -- kout1b 5
  SIGNAL kout1b_6 : BIT;        -- kout1b 6
  SIGNAL kout1b_7 : BIT;        -- kout1b 7
  SIGNAL kout1b_8 : BIT;        -- kout1b 8
  SIGNAL kout1b_9 : BIT;        -- kout1b 9
  SIGNAL kout1b_10 : BIT;       -- kout1b 10
  SIGNAL kout1b_11 : BIT;       -- kout1b 11
  SIGNAL kout1b_12 : BIT;       -- kout1b 12
  SIGNAL kout1b_13 : BIT;       -- kout1b 13
  SIGNAL kout1b_14 : BIT;       -- kout1b 14
  SIGNAL kout1b_15 : BIT;       -- kout1b 15
  SIGNAL kout1b_16 : BIT;       -- kout1b 16
  SIGNAL kout2_0 : BIT; -- kout2 0
  SIGNAL kout2_1 : BIT; -- kout2 1
  SIGNAL kout2_2 : BIT; -- kout2 2
  SIGNAL kout2_3 : BIT; -- kout2 3
  SIGNAL kout2_4 : BIT; -- kout2 4
  SIGNAL kout2_5 : BIT; -- kout2 5
  SIGNAL kout2_6 : BIT; -- kout2 6
  SIGNAL kout2_7 : BIT; -- kout2 7
  SIGNAL kout2_8 : BIT; -- kout2 8
  SIGNAL kout2_9 : BIT; -- kout2 9
  SIGNAL kout2_10 : BIT;        -- kout2 10
  SIGNAL kout2_11 : BIT;        -- kout2 11
  SIGNAL kout2_12 : BIT;        -- kout2 12
  SIGNAL kout2_13 : BIT;        -- kout2 13
  SIGNAL kout2_14 : BIT;        -- kout2 14
  SIGNAL kout2_15 : BIT;        -- kout2 15
  SIGNAL r1_0 : BIT;    -- r1 0
  SIGNAL r1_1 : BIT;    -- r1 1
  SIGNAL r1_2 : BIT;    -- r1 2
  SIGNAL r1_3 : BIT;    -- r1 3
  SIGNAL r1_4 : BIT;    -- r1 4
  SIGNAL r1_5 : BIT;    -- r1 5
  SIGNAL r1_6 : BIT;    -- r1 6
  SIGNAL r1_7 : BIT;    -- r1 7
  SIGNAL r1_8 : BIT;    -- r1 8
  SIGNAL r1_9 : BIT;    -- r1 9
  SIGNAL r1_10 : BIT;   -- r1 10
  SIGNAL r1_11 : BIT;   -- r1 11
  SIGNAL r1_12 : BIT;   -- r1 12
  SIGNAL r1_13 : BIT;   -- r1 13
  SIGNAL r1_14 : BIT;   -- r1 14
  SIGNAL r1_15 : BIT;   -- r1 15
  SIGNAL r2_0 : BIT;    -- r2 0
  SIGNAL r2_1 : BIT;    -- r2 1
  SIGNAL r2_2 : BIT;    -- r2 2
  SIGNAL r2_3 : BIT;    -- r2 3
  SIGNAL r2_4 : BIT;    -- r2 4
  SIGNAL r2_5 : BIT;    -- r2 5
  SIGNAL r2_6 : BIT;    -- r2 6
  SIGNAL r2_7 : BIT;    -- r2 7
  SIGNAL r2_8 : BIT;    -- r2 8
  SIGNAL r2_9 : BIT;    -- r2 9
  SIGNAL r2_10 : BIT;   -- r2 10
  SIGNAL r2_11 : BIT;   -- r2 11
  SIGNAL r2_12 : BIT;   -- r2 12
  SIGNAL r2_13 : BIT;   -- r2 13
  SIGNAL r2_14 : BIT;   -- r2 14
  SIGNAL r2_15 : BIT;   -- r2 15
  SIGNAL res_0 : BIT;   -- res 0
  SIGNAL res_1 : BIT;   -- res 1
  SIGNAL res_2 : BIT;   -- res 2
  SIGNAL res_3 : BIT;   -- res 3
  SIGNAL res_4 : BIT;   -- res 4
  SIGNAL res_5 : BIT;   -- res 5
  SIGNAL res_6 : BIT;   -- res 6
  SIGNAL res_7 : BIT;   -- res 7
  SIGNAL res_8 : BIT;   -- res 8
  SIGNAL res_9 : BIT;   -- res 9
  SIGNAL res_10 : BIT;  -- res 10
  SIGNAL res_11 : BIT;  -- res 11
  SIGNAL res_12 : BIT;  -- res 12
  SIGNAL res_13 : BIT;  -- res 13
  SIGNAL res_14 : BIT;  -- res 14
  SIGNAL res_15 : BIT;  -- res 15
  SIGNAL res_16 : BIT;  -- res 16
  SIGNAL res_17 : BIT;  -- res 17
  SIGNAL res_18 : BIT;  -- res 18
  SIGNAL res_19 : BIT;  -- res 19
  SIGNAL res_20 : BIT;  -- res 20
  SIGNAL res_21 : BIT;  -- res 21
  SIGNAL res_22 : BIT;  -- res 22
  SIGNAL res_23 : BIT;  -- res 23
  SIGNAL res_24 : BIT;  -- res 24
  SIGNAL res_25 : BIT;  -- res 25
  SIGNAL res_26 : BIT;  -- res 26
  SIGNAL res_27 : BIT;  -- res 27
  SIGNAL res_28 : BIT;  -- res 28
  SIGNAL res_29 : BIT;  -- res 29
  SIGNAL res_30 : BIT;  -- res 30
  SIGNAL res_31 : BIT;  -- res 31
 
BEGIN
 
  com1a : comp1_glopg
    PORT MAP (
    vss => vss,
    vdd => vdd,
    kout1 => kout1a_16& kout1a_15& kout1a_14& kout1a_13& kout1a_12& kout1a_11& kout1a_10& kout1a_9& kout1a_8& kout1a_7& kout1a_6& kout1a_5& kout1a_4& kout1a_3& kout1a_2& kout1a_1& kout1a_0,
    kin => in1(15)& in1(14)& in1(13)& in1(12)& in1(11)& in1(10)& in1(9)& in1(8)& in1(7)& in1(6)& in1(5)& in1(4)& in1(3)& in1(2)& in1(1)& in1(0));
  com1b : comp1_glopg
    PORT MAP (
    vss => vss,
    vdd => vdd,
    kout1 => kout1b_16& kout1b_15& kout1b_14& kout1b_13& kout1b_12& kout1b_11& kout1b_10& kout1b_9& kout1b_8& kout1b_7& kout1b_6& kout1b_5& kout1b_4& kout1b_3& kout1b_2& kout1b_1& kout1b_0,
    kin => in2(15)& in2(14)& in2(13)& in2(12)& in2(11)& in2(10)& in2(9)& in2(8)& in2(7)& in2(6)& in2(5)& in2(4)& in2(3)& in2(2)& in2(1)& in2(0));
  mul : mul17_glopg
    PORT MAP (
    vss => vss,
    vdd => vdd,
    sum => res_31& res_30& res_29& res_28& res_27& res_26& res_25& res_24& res_23& res_22& res_21& res_20& res_19& res_18& res_17& res_16& res_15& res_14& res_13& res_12& res_11& res_10& res_9& res_8& res_7& res_6& res_5& res_4& res_3& res_2& res_1& res_0,
    b => kout1b_16& kout1b_15& kout1b_14& kout1b_13& kout1b_12& kout1b_11& kout1b_10& kout1b_9& kout1b_8& kout1b_7& kout1b_6& kout1b_5& kout1b_4& kout1b_3& kout1b_2& kout1b_1& kout1b_0,
    a => kout1a_16& kout1a_15& kout1a_14& kout1a_13& kout1a_12& kout1a_11& kout1a_10& kout1a_9& kout1a_8& kout1a_7& kout1a_6& kout1a_5& kout1a_4& kout1a_3& kout1a_2& kout1a_1& kout1a_0);
  com2 : comp2_glopg
    PORT MAP (
    p => res_0& res_1& res_2& res_3& res_4& res_5& res_6& res_7& res_8& res_9& res_10& res_11& res_12& res_13& res_14& res_15,
    q => res_16& res_17& res_18& res_19& res_20& res_21& res_22& res_23& res_24& res_25& res_26& res_27& res_28& res_29& res_30& res_31,
    kout2 => kout2_0& kout2_1& kout2_2& kout2_3& kout2_4& kout2_5& kout2_6& kout2_7& kout2_8& kout2_9& kout2_10& kout2_11& kout2_12& kout2_13& kout2_14& kout2_15,
    vdd => vdd,
    vss => vss);
  sub : subtract16_glopg
    PORT MAP (
    vss => vss,
    vdd => vdd,
    s => dif_0& dif_1& dif_2& dif_3& dif_4& dif_5& dif_6& dif_7& dif_8& dif_9& dif_10& dif_11& dif_12& dif_13& dif_14& dif_15,
    b => res_16& res_17& res_18& res_19& res_20& res_21& res_22& res_23& res_24& res_25& res_26& res_27& res_28& res_29& res_30& res_31,
    a => res_0& res_1& res_2& res_3& res_4& res_5& res_6& res_7& res_8& res_9& res_10& res_11& res_12& res_13& res_14& res_15);
  reg1 : reg16_glopf
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r1_0& r1_1& r1_2& r1_3& r1_4& r1_5& r1_6& r1_7& r1_8& r1_9& r1_10& r1_11& r1_12& r1_13& r1_14& r1_15,
    clr => clr,
    en => en,
    d => kout2_0& kout2_1& kout2_2& kout2_3& kout2_4& kout2_5& kout2_6& kout2_7& kout2_8& kout2_9& kout2_10& kout2_11& kout2_12& kout2_13& kout2_14& kout2_15);
  reg2 : reg16_glopf
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r2_0& r2_1& r2_2& r2_3& r2_4& r2_5& r2_6& r2_7& r2_8& r2_9& r2_10& r2_11& r2_12& r2_13& r2_14& r2_15,
    clr => clr,
    en => en,
    d => dif_0& dif_1& dif_2& dif_3& dif_4& dif_5& dif_6& dif_7& dif_8& dif_9& dif_10& dif_11& dif_12& dif_13& dif_14& dif_15);
  add : m16adder_glopg
    PORT MAP (
    vss => vss,
    vdd => vdd,
    s => mulout(0)& mulout(1)& mulout(2)& mulout(3)& mulout(4)& mulout(5)& mulout(6)& mulout(7)& mulout(8)& mulout(9)& mulout(10)& mulout(11)& mulout(12)& mulout(13)& mulout(14)& mulout(15),
    b => r1_0& r1_1& r1_2& r1_3& r1_4& r1_5& r1_6& r1_7& r1_8& r1_9& r1_10& r1_11& r1_12& r1_13& r1_14& r1_15,
    a => r2_0& r2_1& r2_2& r2_3& r2_4& r2_5& r2_6& r2_7& r2_8& r2_9& r2_10& r2_11& r2_12& r2_13& r2_14& r2_15);
 
end VST;

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Subversion Repositories structural_vhdl

[/] [structural_vhdl/] [trunk/] [idea_machine/] [sm16plus1mul.vst] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	marta	-- VHDL structural description generated from `sm16plus1mul`
2			`-- date : Sat Sep 8 04:28:34 2001`
3
4
5			`-- Entity Declaration`
6
7			`ENTITY sm16plus1mul IS`
8			`PORT (`
9			`in1 : in BIT_VECTOR (0 TO 15); -- in1`
10			`in2 : in BIT_VECTOR (0 TO 15); -- in2`
11			`en : in BIT; -- en`
12			`clr : in BIT; -- clr`
13			`mulout : out BIT_VECTOR (0 TO 15); -- mulout`
14			`vdd : in BIT; -- vdd`
15			`vss : in BIT -- vss`
16			`);`
17			`END sm16plus1mul;`
18
19			`-- Architecture Declaration`
20
21			`ARCHITECTURE VST OF sm16plus1mul IS`
22			`COMPONENT comp1_glopg`
23			`port (`
24			`kin : in BIT_VECTOR(15 DOWNTO 0); -- kin`
25			`kout1 : out BIT_VECTOR(16 DOWNTO 0); -- kout1`
26			`vdd : in BIT; -- vdd`
27			`vss : in BIT -- vss`
28			`);`
29			`END COMPONENT;`
30
31			`COMPONENT mul17_glopg`
32			`port (`
33			`a : in BIT_VECTOR(16 DOWNTO 0); -- a`
34			`b : in BIT_VECTOR(16 DOWNTO 0); -- b`
35			`sum : out BIT_VECTOR(31 DOWNTO 0); -- sum`
36			`vdd : in BIT; -- vdd`
37			`vss : in BIT -- vss`
38			`);`
39			`END COMPONENT;`
40
41			`COMPONENT comp2_glopg`
42			`port (`
43			`vss : in BIT; -- vss`
44			`vdd : in BIT; -- vdd`
45			`kout2 : out BIT_VECTOR(0 TO 15); -- kout2`
46			`q : in BIT_VECTOR(0 TO 15); -- q`
47			`p : in BIT_VECTOR(0 TO 15) -- p`
48			`);`
49			`END COMPONENT;`
50
51			`COMPONENT subtract16_glopg`
52			`port (`
53			`a : in BIT_VECTOR(0 TO 15); -- a`
54			`b : in BIT_VECTOR(0 TO 15); -- b`
55			`s : out BIT_VECTOR(0 TO 15); -- s`
56			`vdd : in BIT; -- vdd`
57			`vss : in BIT -- vss`
58			`);`
59			`END COMPONENT;`
60
61			`COMPONENT reg16_glopf`
62			`port (`
63			`d : in BIT_VECTOR(0 TO 15); -- d`
64			`en : in BIT; -- en`
65			`clr : in BIT; -- clr`
66			`q : inout BIT_VECTOR(0 TO 15); -- q`
67			`vdd : in BIT; -- vdd`
68			`vss : in BIT -- vss`
69			`);`
70			`END COMPONENT;`
71
72			`COMPONENT m16adder_glopg`
73			`port (`
74			`a : in BIT_VECTOR(0 TO 15); -- a`
75			`b : in BIT_VECTOR(0 TO 15); -- b`
76			`s : out BIT_VECTOR(0 TO 15); -- s`
77			`vdd : in BIT; -- vdd`
78			`vss : in BIT -- vss`
79			`);`
80			`END COMPONENT;`
81
82			`SIGNAL dif_0 : BIT; -- dif 0`
83			`SIGNAL dif_1 : BIT; -- dif 1`
84			`SIGNAL dif_2 : BIT; -- dif 2`
85			`SIGNAL dif_3 : BIT; -- dif 3`
86			`SIGNAL dif_4 : BIT; -- dif 4`
87			`SIGNAL dif_5 : BIT; -- dif 5`
88			`SIGNAL dif_6 : BIT; -- dif 6`
89			`SIGNAL dif_7 : BIT; -- dif 7`
90			`SIGNAL dif_8 : BIT; -- dif 8`
91			`SIGNAL dif_9 : BIT; -- dif 9`
92			`SIGNAL dif_10 : BIT; -- dif 10`
93			`SIGNAL dif_11 : BIT; -- dif 11`
94			`SIGNAL dif_12 : BIT; -- dif 12`
95			`SIGNAL dif_13 : BIT; -- dif 13`
96			`SIGNAL dif_14 : BIT; -- dif 14`
97			`SIGNAL dif_15 : BIT; -- dif 15`
98			`SIGNAL kout1a_0 : BIT; -- kout1a 0`
99			`SIGNAL kout1a_1 : BIT; -- kout1a 1`
100			`SIGNAL kout1a_2 : BIT; -- kout1a 2`
101			`SIGNAL kout1a_3 : BIT; -- kout1a 3`
102			`SIGNAL kout1a_4 : BIT; -- kout1a 4`
103			`SIGNAL kout1a_5 : BIT; -- kout1a 5`
104			`SIGNAL kout1a_6 : BIT; -- kout1a 6`
105			`SIGNAL kout1a_7 : BIT; -- kout1a 7`
106			`SIGNAL kout1a_8 : BIT; -- kout1a 8`
107			`SIGNAL kout1a_9 : BIT; -- kout1a 9`
108			`SIGNAL kout1a_10 : BIT; -- kout1a 10`
109			`SIGNAL kout1a_11 : BIT; -- kout1a 11`
110			`SIGNAL kout1a_12 : BIT; -- kout1a 12`
111			`SIGNAL kout1a_13 : BIT; -- kout1a 13`
112			`SIGNAL kout1a_14 : BIT; -- kout1a 14`
113			`SIGNAL kout1a_15 : BIT; -- kout1a 15`
114			`SIGNAL kout1a_16 : BIT; -- kout1a 16`
115			`SIGNAL kout1b_0 : BIT; -- kout1b 0`
116			`SIGNAL kout1b_1 : BIT; -- kout1b 1`
117			`SIGNAL kout1b_2 : BIT; -- kout1b 2`
118			`SIGNAL kout1b_3 : BIT; -- kout1b 3`
119			`SIGNAL kout1b_4 : BIT; -- kout1b 4`
120			`SIGNAL kout1b_5 : BIT; -- kout1b 5`
121			`SIGNAL kout1b_6 : BIT; -- kout1b 6`
122			`SIGNAL kout1b_7 : BIT; -- kout1b 7`
123			`SIGNAL kout1b_8 : BIT; -- kout1b 8`
124			`SIGNAL kout1b_9 : BIT; -- kout1b 9`
125			`SIGNAL kout1b_10 : BIT; -- kout1b 10`
126			`SIGNAL kout1b_11 : BIT; -- kout1b 11`
127			`SIGNAL kout1b_12 : BIT; -- kout1b 12`
128			`SIGNAL kout1b_13 : BIT; -- kout1b 13`
129			`SIGNAL kout1b_14 : BIT; -- kout1b 14`
130			`SIGNAL kout1b_15 : BIT; -- kout1b 15`
131			`SIGNAL kout1b_16 : BIT; -- kout1b 16`
132			`SIGNAL kout2_0 : BIT; -- kout2 0`
133			`SIGNAL kout2_1 : BIT; -- kout2 1`
134			`SIGNAL kout2_2 : BIT; -- kout2 2`
135			`SIGNAL kout2_3 : BIT; -- kout2 3`
136			`SIGNAL kout2_4 : BIT; -- kout2 4`
137			`SIGNAL kout2_5 : BIT; -- kout2 5`
138			`SIGNAL kout2_6 : BIT; -- kout2 6`
139			`SIGNAL kout2_7 : BIT; -- kout2 7`
140			`SIGNAL kout2_8 : BIT; -- kout2 8`
141			`SIGNAL kout2_9 : BIT; -- kout2 9`
142			`SIGNAL kout2_10 : BIT; -- kout2 10`
143			`SIGNAL kout2_11 : BIT; -- kout2 11`
144			`SIGNAL kout2_12 : BIT; -- kout2 12`
145			`SIGNAL kout2_13 : BIT; -- kout2 13`
146			`SIGNAL kout2_14 : BIT; -- kout2 14`
147			`SIGNAL kout2_15 : BIT; -- kout2 15`
148			`SIGNAL r1_0 : BIT; -- r1 0`
149			`SIGNAL r1_1 : BIT; -- r1 1`
150			`SIGNAL r1_2 : BIT; -- r1 2`
151			`SIGNAL r1_3 : BIT; -- r1 3`
152			`SIGNAL r1_4 : BIT; -- r1 4`
153			`SIGNAL r1_5 : BIT; -- r1 5`
154			`SIGNAL r1_6 : BIT; -- r1 6`
155			`SIGNAL r1_7 : BIT; -- r1 7`
156			`SIGNAL r1_8 : BIT; -- r1 8`
157			`SIGNAL r1_9 : BIT; -- r1 9`
158			`SIGNAL r1_10 : BIT; -- r1 10`
159			`SIGNAL r1_11 : BIT; -- r1 11`
160			`SIGNAL r1_12 : BIT; -- r1 12`
161			`SIGNAL r1_13 : BIT; -- r1 13`
162			`SIGNAL r1_14 : BIT; -- r1 14`
163			`SIGNAL r1_15 : BIT; -- r1 15`
164			`SIGNAL r2_0 : BIT; -- r2 0`
165			`SIGNAL r2_1 : BIT; -- r2 1`
166			`SIGNAL r2_2 : BIT; -- r2 2`
167			`SIGNAL r2_3 : BIT; -- r2 3`
168			`SIGNAL r2_4 : BIT; -- r2 4`
169			`SIGNAL r2_5 : BIT; -- r2 5`
170			`SIGNAL r2_6 : BIT; -- r2 6`
171			`SIGNAL r2_7 : BIT; -- r2 7`
172			`SIGNAL r2_8 : BIT; -- r2 8`
173			`SIGNAL r2_9 : BIT; -- r2 9`
174			`SIGNAL r2_10 : BIT; -- r2 10`
175			`SIGNAL r2_11 : BIT; -- r2 11`
176			`SIGNAL r2_12 : BIT; -- r2 12`
177			`SIGNAL r2_13 : BIT; -- r2 13`
178			`SIGNAL r2_14 : BIT; -- r2 14`
179			`SIGNAL r2_15 : BIT; -- r2 15`
180			`SIGNAL res_0 : BIT; -- res 0`
181			`SIGNAL res_1 : BIT; -- res 1`
182			`SIGNAL res_2 : BIT; -- res 2`
183			`SIGNAL res_3 : BIT; -- res 3`
184			`SIGNAL res_4 : BIT; -- res 4`
185			`SIGNAL res_5 : BIT; -- res 5`
186			`SIGNAL res_6 : BIT; -- res 6`
187			`SIGNAL res_7 : BIT; -- res 7`
188			`SIGNAL res_8 : BIT; -- res 8`
189			`SIGNAL res_9 : BIT; -- res 9`
190			`SIGNAL res_10 : BIT; -- res 10`
191			`SIGNAL res_11 : BIT; -- res 11`
192			`SIGNAL res_12 : BIT; -- res 12`
193			`SIGNAL res_13 : BIT; -- res 13`
194			`SIGNAL res_14 : BIT; -- res 14`
195			`SIGNAL res_15 : BIT; -- res 15`
196			`SIGNAL res_16 : BIT; -- res 16`
197			`SIGNAL res_17 : BIT; -- res 17`
198			`SIGNAL res_18 : BIT; -- res 18`
199			`SIGNAL res_19 : BIT; -- res 19`
200			`SIGNAL res_20 : BIT; -- res 20`
201			`SIGNAL res_21 : BIT; -- res 21`
202			`SIGNAL res_22 : BIT; -- res 22`
203			`SIGNAL res_23 : BIT; -- res 23`
204			`SIGNAL res_24 : BIT; -- res 24`
205			`SIGNAL res_25 : BIT; -- res 25`
206			`SIGNAL res_26 : BIT; -- res 26`
207			`SIGNAL res_27 : BIT; -- res 27`
208			`SIGNAL res_28 : BIT; -- res 28`
209			`SIGNAL res_29 : BIT; -- res 29`
210			`SIGNAL res_30 : BIT; -- res 30`
211			`SIGNAL res_31 : BIT; -- res 31`
212
213			`BEGIN`
214
215			`com1a : comp1_glopg`
216			`PORT MAP (`
217			`vss => vss,`
218			`vdd => vdd,`
219			`kout1 => kout1a_16& kout1a_15& kout1a_14& kout1a_13& kout1a_12& kout1a_11& kout1a_10& kout1a_9& kout1a_8& kout1a_7& kout1a_6& kout1a_5& kout1a_4& kout1a_3& kout1a_2& kout1a_1& kout1a_0,`
220			`kin => in1(15)& in1(14)& in1(13)& in1(12)& in1(11)& in1(10)& in1(9)& in1(8)& in1(7)& in1(6)& in1(5)& in1(4)& in1(3)& in1(2)& in1(1)& in1(0));`
221			`com1b : comp1_glopg`
222			`PORT MAP (`
223			`vss => vss,`
224			`vdd => vdd,`
225			`kout1 => kout1b_16& kout1b_15& kout1b_14& kout1b_13& kout1b_12& kout1b_11& kout1b_10& kout1b_9& kout1b_8& kout1b_7& kout1b_6& kout1b_5& kout1b_4& kout1b_3& kout1b_2& kout1b_1& kout1b_0,`
226			`kin => in2(15)& in2(14)& in2(13)& in2(12)& in2(11)& in2(10)& in2(9)& in2(8)& in2(7)& in2(6)& in2(5)& in2(4)& in2(3)& in2(2)& in2(1)& in2(0));`
227			`mul : mul17_glopg`
228			`PORT MAP (`
229			`vss => vss,`
230			`vdd => vdd,`
231			`sum => res_31& res_30& res_29& res_28& res_27& res_26& res_25& res_24& res_23& res_22& res_21& res_20& res_19& res_18& res_17& res_16& res_15& res_14& res_13& res_12& res_11& res_10& res_9& res_8& res_7& res_6& res_5& res_4& res_3& res_2& res_1& res_0,`
232			`b => kout1b_16& kout1b_15& kout1b_14& kout1b_13& kout1b_12& kout1b_11& kout1b_10& kout1b_9& kout1b_8& kout1b_7& kout1b_6& kout1b_5& kout1b_4& kout1b_3& kout1b_2& kout1b_1& kout1b_0,`
233			`a => kout1a_16& kout1a_15& kout1a_14& kout1a_13& kout1a_12& kout1a_11& kout1a_10& kout1a_9& kout1a_8& kout1a_7& kout1a_6& kout1a_5& kout1a_4& kout1a_3& kout1a_2& kout1a_1& kout1a_0);`
234			`com2 : comp2_glopg`
235			`PORT MAP (`
236			`p => res_0& res_1& res_2& res_3& res_4& res_5& res_6& res_7& res_8& res_9& res_10& res_11& res_12& res_13& res_14& res_15,`
237			`q => res_16& res_17& res_18& res_19& res_20& res_21& res_22& res_23& res_24& res_25& res_26& res_27& res_28& res_29& res_30& res_31,`
238			`kout2 => kout2_0& kout2_1& kout2_2& kout2_3& kout2_4& kout2_5& kout2_6& kout2_7& kout2_8& kout2_9& kout2_10& kout2_11& kout2_12& kout2_13& kout2_14& kout2_15,`
239			`vdd => vdd,`
240			`vss => vss);`
241			`sub : subtract16_glopg`
242			`PORT MAP (`
243			`vss => vss,`
244			`vdd => vdd,`
245			`s => dif_0& dif_1& dif_2& dif_3& dif_4& dif_5& dif_6& dif_7& dif_8& dif_9& dif_10& dif_11& dif_12& dif_13& dif_14& dif_15,`
246			`b => res_16& res_17& res_18& res_19& res_20& res_21& res_22& res_23& res_24& res_25& res_26& res_27& res_28& res_29& res_30& res_31,`
247			`a => res_0& res_1& res_2& res_3& res_4& res_5& res_6& res_7& res_8& res_9& res_10& res_11& res_12& res_13& res_14& res_15);`
248			`reg1 : reg16_glopf`
249			`PORT MAP (`
250			`vss => vss,`
251			`vdd => vdd,`
252			`q => r1_0& r1_1& r1_2& r1_3& r1_4& r1_5& r1_6& r1_7& r1_8& r1_9& r1_10& r1_11& r1_12& r1_13& r1_14& r1_15,`
253			`clr => clr,`
254			`en => en,`
255			`d => kout2_0& kout2_1& kout2_2& kout2_3& kout2_4& kout2_5& kout2_6& kout2_7& kout2_8& kout2_9& kout2_10& kout2_11& kout2_12& kout2_13& kout2_14& kout2_15);`
256			`reg2 : reg16_glopf`
257			`PORT MAP (`
258			`vss => vss,`
259			`vdd => vdd,`
260			`q => r2_0& r2_1& r2_2& r2_3& r2_4& r2_5& r2_6& r2_7& r2_8& r2_9& r2_10& r2_11& r2_12& r2_13& r2_14& r2_15,`
261			`clr => clr,`
262			`en => en,`
263			`d => dif_0& dif_1& dif_2& dif_3& dif_4& dif_5& dif_6& dif_7& dif_8& dif_9& dif_10& dif_11& dif_12& dif_13& dif_14& dif_15);`
264			`add : m16adder_glopg`
265			`PORT MAP (`
266			`vss => vss,`
267			`vdd => vdd,`
268			`s => mulout(0)& mulout(1)& mulout(2)& mulout(3)& mulout(4)& mulout(5)& mulout(6)& mulout(7)& mulout(8)& mulout(9)& mulout(10)& mulout(11)& mulout(12)& mulout(13)& mulout(14)& mulout(15),`
269			`b => r1_0& r1_1& r1_2& r1_3& r1_4& r1_5& r1_6& r1_7& r1_8& r1_9& r1_10& r1_11& r1_12& r1_13& r1_14& r1_15,`
270			`a => r2_0& r2_1& r2_2& r2_3& r2_4& r2_5& r2_6& r2_7& r2_8& r2_9& r2_10& r2_11& r2_12& r2_13& r2_14& r2_15);`
271
272			`end VST;`