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[/] [structural_vhdl/] [trunk/] [idea_machine/] [subtract16.vst] - Blame information for rev 4

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1 2 marta 
-- VHDL structural description generated from `subtract16`
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--              date : Sat Sep  8 04:14:01 2001
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-- Entity Declaration
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ENTITY subtract16 IS
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  PORT (
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  a : in BIT_VECTOR (0 TO 15);  -- a
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  b : in BIT_VECTOR (0 TO 15);  -- b
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  s : out BIT_VECTOR (0 TO 15); -- s
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  vdd : in BIT; -- vdd
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  vss : in BIT  -- vss
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  );
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END subtract16;
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-- Architecture Declaration
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ARCHITECTURE VST OF subtract16 IS
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  COMPONENT zero_x0
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    port (
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    nq : out BIT;       -- nq
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  COMPONENT fsub_glopg
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    port (
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    a : in BIT; -- a
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    b : in BIT; -- b
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    bin : in BIT;       -- bin
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    d : out BIT;        -- d
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    bout : out BIT;     -- bout
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  COMPONENT xr2_x1
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    port (
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    i0 : in BIT;        -- i0
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    i1 : in BIT;        -- i1
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    q : out BIT;        -- q
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  SIGNAL bo_0 : BIT;    -- bo 0
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  SIGNAL bo_1 : BIT;    -- bo 1
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  SIGNAL bo_2 : BIT;    -- bo 2
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  SIGNAL bo_3 : BIT;    -- bo 3
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  SIGNAL bo_4 : BIT;    -- bo 4
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  SIGNAL bo_5 : BIT;    -- bo 5
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  SIGNAL bo_6 : BIT;    -- bo 6
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  SIGNAL bo_7 : BIT;    -- bo 7
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  SIGNAL bo_8 : BIT;    -- bo 8
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  SIGNAL bo_9 : BIT;    -- bo 9
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  SIGNAL bo_10 : BIT;   -- bo 10
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  SIGNAL bo_11 : BIT;   -- bo 11
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  SIGNAL bo_12 : BIT;   -- bo 12
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  SIGNAL bo_13 : BIT;   -- bo 13
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  SIGNAL bo_14 : BIT;   -- bo 14
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  SIGNAL o_xr2 : BIT;   -- o_xr2
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  SIGNAL o_zero : BIT;  -- o_zero
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BEGIN
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  zero : zero_x0
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => o_zero);
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  fs0 : fsub_glopg
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    bout => bo_0,
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    d => s(0),
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    bin => o_zero,
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    b => b(0),
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    a => a(0));
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  fs1 : fsub_glopg
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    bout => bo_1,
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    d => s(1),
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    bin => bo_0,
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    b => b(1),
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    a => a(1));
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  fs2 : fsub_glopg
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    bout => bo_2,
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    d => s(2),
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    bin => bo_1,
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    b => b(2),
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    a => a(2));
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  fs3 : fsub_glopg
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    bout => bo_3,
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    d => s(3),
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    bin => bo_2,
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    b => b(3),
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    a => a(3));
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  fs4 : fsub_glopg
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    bout => bo_4,
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    d => s(4),
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    bin => bo_3,
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    b => b(4),
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    a => a(4));
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  fs5 : fsub_glopg
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    bout => bo_5,
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    d => s(5),
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    bin => bo_4,
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    b => b(5),
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    a => a(5));
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  fs6 : fsub_glopg
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    bout => bo_6,
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    d => s(6),
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    bin => bo_5,
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    b => b(6),
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    a => a(6));
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  fs7 : fsub_glopg
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    bout => bo_7,
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    d => s(7),
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    bin => bo_6,
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    b => b(7),
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    a => a(7));
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  fs8 : fsub_glopg
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    bout => bo_8,
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    d => s(8),
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    bin => bo_7,
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    b => b(8),
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    a => a(8));
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  fs9 : fsub_glopg
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    bout => bo_9,
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    d => s(9),
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    bin => bo_8,
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    b => b(9),
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    a => a(9));
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  fs10 : fsub_glopg
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    bout => bo_10,
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    d => s(10),
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    bin => bo_9,
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    b => b(10),
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    a => a(10));
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  fs11 : fsub_glopg
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    bout => bo_11,
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    d => s(11),
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    bin => bo_10,
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    b => b(11),
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    a => a(11));
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  fs12 : fsub_glopg
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    bout => bo_12,
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    d => s(12),
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    bin => bo_11,
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    b => b(12),
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    a => a(12));
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  fs13 : fsub_glopg
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    bout => bo_13,
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    d => s(13),
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    bin => bo_12,
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    b => b(13),
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    a => a(13));
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  fs14 : fsub_glopg
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    bout => bo_14,
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    d => s(14),
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    bin => bo_13,
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    b => b(14),
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    a => a(14));
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  xr2 : xr2_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => o_xr2,
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    i1 => b(15),
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    i0 => a(15));
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  xr3 : xr2_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => s(15),
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    i1 => bo_14,
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    i0 => o_xr2);
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end VST;

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