OpenCores
URL https://opencores.org/ocsvn/structural_vhdl/structural_vhdl/trunk

Subversion Repositories structural_vhdl

[/] [structural_vhdl/] [trunk/] [idea_machine/] [xor16_glopg.vst] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 marta 
-- VHDL structural description generated from `xor16_glopg`
2 
--              date : Sat Sep  8 02:20:05 2001
3 
 
4 
 
5 
-- Entity Declaration
6 
 
7 
ENTITY xor16_glopg IS
8 
  PORT (
9 
  a : in BIT_VECTOR (0 TO 15);  -- a
10 
  b : in BIT_VECTOR (0 TO 15);  -- b
11 
  q : out BIT_VECTOR (0 TO 15); -- q
12 
  vdd : in BIT; -- vdd
13 
  vss : in BIT  -- vss
14 
  );
15 
END xor16_glopg;
16 
 
17 
-- Architecture Declaration
18 
 
19 
ARCHITECTURE VST OF xor16_glopg IS
20 
  COMPONENT xr2_x4
21 
    port (
22 
    i0 : in BIT;        -- i0
23 
    i1 : in BIT;        -- i1
24 
    q : out BIT;        -- q
25 
    vdd : in BIT;       -- vdd
26 
    vss : in BIT        -- vss
27 
    );
28 
  END COMPONENT;
29 
 
30 
 
31 
BEGIN
32 
 
33 
  xr0 : xr2_x4
34 
    PORT MAP (
35 
    vss => vss,
36 
    vdd => vdd,
37 
    q => q(0),
38 
    i1 => b(0),
39 
    i0 => a(0));
40 
  xr1 : xr2_x4
41 
    PORT MAP (
42 
    vss => vss,
43 
    vdd => vdd,
44 
    q => q(1),
45 
    i1 => b(1),
46 
    i0 => a(1));
47 
  xr2 : xr2_x4
48 
    PORT MAP (
49 
    vss => vss,
50 
    vdd => vdd,
51 
    q => q(2),
52 
    i1 => b(2),
53 
    i0 => a(2));
54 
  xr3 : xr2_x4
55 
    PORT MAP (
56 
    vss => vss,
57 
    vdd => vdd,
58 
    q => q(3),
59 
    i1 => b(3),
60 
    i0 => a(3));
61 
  xr4 : xr2_x4
62 
    PORT MAP (
63 
    vss => vss,
64 
    vdd => vdd,
65 
    q => q(4),
66 
    i1 => b(4),
67 
    i0 => a(4));
68 
  xr5 : xr2_x4
69 
    PORT MAP (
70 
    vss => vss,
71 
    vdd => vdd,
72 
    q => q(5),
73 
    i1 => b(5),
74 
    i0 => a(5));
75 
  xr6 : xr2_x4
76 
    PORT MAP (
77 
    vss => vss,
78 
    vdd => vdd,
79 
    q => q(6),
80 
    i1 => b(6),
81 
    i0 => a(6));
82 
  xr7 : xr2_x4
83 
    PORT MAP (
84 
    vss => vss,
85 
    vdd => vdd,
86 
    q => q(7),
87 
    i1 => b(7),
88 
    i0 => a(7));
89 
  xr8 : xr2_x4
90 
    PORT MAP (
91 
    vss => vss,
92 
    vdd => vdd,
93 
    q => q(8),
94 
    i1 => b(8),
95 
    i0 => a(8));
96 
  xr9 : xr2_x4
97 
    PORT MAP (
98 
    vss => vss,
99 
    vdd => vdd,
100 
    q => q(9),
101 
    i1 => b(9),
102 
    i0 => a(9));
103 
  xr10 : xr2_x4
104 
    PORT MAP (
105 
    vss => vss,
106 
    vdd => vdd,
107 
    q => q(10),
108 
    i1 => b(10),
109 
    i0 => a(10));
110 
  xr11 : xr2_x4
111 
    PORT MAP (
112 
    vss => vss,
113 
    vdd => vdd,
114 
    q => q(11),
115 
    i1 => b(11),
116 
    i0 => a(11));
117 
  xr12 : xr2_x4
118 
    PORT MAP (
119 
    vss => vss,
120 
    vdd => vdd,
121 
    q => q(12),
122 
    i1 => b(12),
123 
    i0 => a(12));
124 
  xr13 : xr2_x4
125 
    PORT MAP (
126 
    vss => vss,
127 
    vdd => vdd,
128 
    q => q(13),
129 
    i1 => b(13),
130 
    i0 => a(13));
131 
  xr14 : xr2_x4
132 
    PORT MAP (
133 
    vss => vss,
134 
    vdd => vdd,
135 
    q => q(14),
136 
    i1 => b(14),
137 
    i0 => a(14));
138 
  xr15 : xr2_x4
139 
    PORT MAP (
140 
    vss => vss,
141 
    vdd => vdd,
142 
    q => q(15),
143 
    i1 => b(15),
144 
    i0 => a(15));
145 
 
146 
end VST;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.