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[/] [structural_vhdl/] [trunk/] [idea_machine/] [xor16_glopg.vst] - Blame information for rev 4

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1 2 marta 
-- VHDL structural description generated from `xor16_glopg`
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--              date : Sat Sep  8 02:20:05 2001
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-- Entity Declaration
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ENTITY xor16_glopg IS
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  PORT (
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  a : in BIT_VECTOR (0 TO 15);  -- a
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  b : in BIT_VECTOR (0 TO 15);  -- b
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  q : out BIT_VECTOR (0 TO 15); -- q
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  vdd : in BIT; -- vdd
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  vss : in BIT  -- vss
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  );
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END xor16_glopg;
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-- Architecture Declaration
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ARCHITECTURE VST OF xor16_glopg IS
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  COMPONENT xr2_x4
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    port (
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    i0 : in BIT;        -- i0
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    i1 : in BIT;        -- i1
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    q : out BIT;        -- q
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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BEGIN
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  xr0 : xr2_x4
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => q(0),
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    i1 => b(0),
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    i0 => a(0));
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  xr1 : xr2_x4
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => q(1),
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    i1 => b(1),
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    i0 => a(1));
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  xr2 : xr2_x4
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => q(2),
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    i1 => b(2),
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    i0 => a(2));
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  xr3 : xr2_x4
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => q(3),
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    i1 => b(3),
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    i0 => a(3));
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  xr4 : xr2_x4
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => q(4),
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    i1 => b(4),
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    i0 => a(4));
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  xr5 : xr2_x4
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => q(5),
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    i1 => b(5),
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    i0 => a(5));
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  xr6 : xr2_x4
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => q(6),
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    i1 => b(6),
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    i0 => a(6));
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  xr7 : xr2_x4
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => q(7),
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    i1 => b(7),
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    i0 => a(7));
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  xr8 : xr2_x4
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => q(8),
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    i1 => b(8),
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    i0 => a(8));
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  xr9 : xr2_x4
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => q(9),
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    i1 => b(9),
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    i0 => a(9));
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  xr10 : xr2_x4
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => q(10),
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    i1 => b(10),
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    i0 => a(10));
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  xr11 : xr2_x4
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => q(11),
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    i1 => b(11),
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    i0 => a(11));
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  xr12 : xr2_x4
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => q(12),
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    i1 => b(12),
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    i0 => a(12));
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  xr13 : xr2_x4
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => q(13),
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    i1 => b(13),
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    i0 => a(13));
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  xr14 : xr2_x4
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => q(14),
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    i1 => b(14),
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    i0 => a(14));
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  xr15 : xr2_x4
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => q(15),
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    i1 => b(15),
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    i0 => a(15));
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end VST;

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