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[/] [structural_vhdl/] [trunk/] [inout_port/] [control_datain.vst] - Blame information for rev 2

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1 2 marta 
-- VHDL structural description generated from `control_datain`
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--              date : Mon Aug 27 03:14:41 2001
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-- Entity Declaration
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ENTITY control_datain IS
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  PORT (
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  clk : in BIT; -- clk
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  rst : in BIT; -- rst
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  dt_sended : in BIT;   -- dt_sended
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  emp_buf : in BIT;     -- emp_buf
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  en_bufin : inout BIT; -- en_bufin
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  req_dt : out BIT;     -- req_dt
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  dt_ready : inout BIT; -- dt_ready
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  n_block : inout BIT;  -- n_block
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  vdd : in BIT; -- vdd
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  vss : in BIT  -- vss
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  );
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END control_datain;
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-- Architecture Declaration
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ARCHITECTURE VST OF control_datain IS
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  COMPONENT ao22_x2
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    port (
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    i0 : in BIT;        -- i0
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    i1 : in BIT;        -- i1
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    i2 : in BIT;        -- i2
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    q : out BIT;        -- q
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  COMPONENT o3_x2
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    port (
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    i0 : in BIT;        -- i0
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    i1 : in BIT;        -- i1
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    i2 : in BIT;        -- i2
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    q : out BIT;        -- q
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  COMPONENT nao22_x1
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    port (
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    i0 : in BIT;        -- i0
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    i1 : in BIT;        -- i1
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    i2 : in BIT;        -- i2
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    nq : out BIT;       -- nq
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  COMPONENT an12_x1
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    port (
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    i0 : in BIT;        -- i0
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    i1 : in BIT;        -- i1
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    q : out BIT;        -- q
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  COMPONENT na2_x1
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    port (
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    i0 : in BIT;        -- i0
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    i1 : in BIT;        -- i1
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    nq : out BIT;       -- nq
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  COMPONENT no3_x1
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    port (
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    i0 : in BIT;        -- i0
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    i1 : in BIT;        -- i1
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    i2 : in BIT;        -- i2
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    nq : out BIT;       -- nq
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  COMPONENT o2_x2
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    port (
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    i0 : in BIT;        -- i0
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    i1 : in BIT;        -- i1
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    q : out BIT;        -- q
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  COMPONENT xr2_x1
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    port (
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    i0 : in BIT;        -- i0
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    i1 : in BIT;        -- i1
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    q : out BIT;        -- q
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  COMPONENT inv_x1
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    port (
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    i : in BIT; -- i
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    nq : out BIT;       -- nq
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  COMPONENT a2_x2
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    port (
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    i0 : in BIT;        -- i0
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    i1 : in BIT;        -- i1
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    q : out BIT;        -- q
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  COMPONENT oa22_x2
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    port (
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    i0 : in BIT;        -- i0
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    i1 : in BIT;        -- i1
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    i2 : in BIT;        -- i2
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    q : out BIT;        -- q
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  COMPONENT a4_x2
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    port (
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    i0 : in BIT;        -- i0
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    i1 : in BIT;        -- i1
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    i2 : in BIT;        -- i2
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    i3 : in BIT;        -- i3
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    q : out BIT;        -- q
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  COMPONENT sff1_x4
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    port (
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    ck : in BIT;        -- ck
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    i : in BIT; -- i
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    q : out BIT;        -- q
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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161 
  SIGNAL auxsc1 : BIT;  -- auxsc1
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  SIGNAL auxsc2 : BIT;  -- auxsc2
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  SIGNAL auxsc12 : BIT; -- auxsc12
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  SIGNAL auxsc13 : BIT; -- auxsc13
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  SIGNAL auxsc14 : BIT; -- auxsc14
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  SIGNAL auxsc15 : BIT; -- auxsc15
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  SIGNAL auxsc17 : BIT; -- auxsc17
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  SIGNAL auxsc19 : BIT; -- auxsc19
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  SIGNAL auxsc21 : BIT; -- auxsc21
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  SIGNAL auxsc36 : BIT; -- auxsc36
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  SIGNAL auxsc29 : BIT; -- auxsc29
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  SIGNAL auxsc37 : BIT; -- auxsc37
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  SIGNAL auxsc38 : BIT; -- auxsc38
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  SIGNAL auxsc39 : BIT; -- auxsc39
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  SIGNAL auxsc40 : BIT; -- auxsc40
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  SIGNAL auxsc41 : BIT; -- auxsc41
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  SIGNAL auxreg3 : BIT; -- auxreg3
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  SIGNAL auxreg2 : BIT; -- auxreg2
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  SIGNAL auxreg1 : BIT; -- auxreg1
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181 
BEGIN
182 
 
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  req_dt : ao22_x2
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => req_dt,
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    i2 => auxsc41,
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    i1 => auxsc17,
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    i0 => auxsc36);
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  auxsc41 : o3_x2
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => auxsc41,
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    i2 => auxsc40,
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    i1 => auxreg3,
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    i0 => rst);
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  auxsc40 : nao22_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc40,
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    i2 => auxsc39,
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    i1 => auxsc29,
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    i0 => dt_sended);
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  auxsc39 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc39,
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    i => auxsc38);
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  auxsc38 : an12_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => auxsc38,
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    i1 => auxreg2,
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    i0 => auxsc37);
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  auxsc37 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc37,
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    i => emp_buf);
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  auxsc29 : a2_x2
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => auxsc29,
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    i1 => auxreg2,
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    i0 => auxsc19);
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  auxsc36 : o2_x2
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => auxsc36,
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    i1 => auxsc19,
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    i0 => rst);
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  auxsc21 : na2_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc21,
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    i1 => auxreg2,
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    i0 => auxsc19);
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  auxsc19 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc19,
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    i => auxreg1);
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  auxsc17 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc17,
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    i => auxreg3);
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  auxsc15 : no3_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc15,
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    i2 => auxsc14,
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    i1 => auxsc13,
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    i0 => rst);
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  auxsc14 : o2_x2
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => auxsc14,
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    i1 => emp_buf,
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    i0 => auxreg3);
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  auxsc13 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc13,
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    i => auxreg2);
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  auxsc12 : a2_x2
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => auxsc12,
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    i1 => auxsc1,
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    i0 => auxreg3);
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  auxsc2 : xr2_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => auxsc2,
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    i1 => auxreg3,
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    i0 => auxreg1);
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  auxsc1 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc1,
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    i => rst);
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  auxinit1_a : a2_x2
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => n_block,
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    i1 => auxsc2,
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    i0 => auxsc1);
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  auxinit2_a : oa22_x2
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => dt_ready,
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    i2 => auxsc15,
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    i1 => auxreg1,
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    i0 => auxsc12);
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  auxinit3_a : a4_x2
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => en_bufin,
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    i3 => auxsc21,
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    i2 => auxsc1,
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    i1 => auxsc17,
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    i0 => dt_sended);
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  current_state_0 : sff1_x4
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => auxreg1,
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    i => n_block,
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    ck => clk);
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  current_state_1 : sff1_x4
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => auxreg2,
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    i => dt_ready,
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    ck => clk);
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  current_state_2 : sff1_x4
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => auxreg3,
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    i => en_bufin,
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    ck => clk);
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end VST;

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