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Subversion Repositories structural_vhdl

[/] [structural_vhdl/] [trunk/] [inout_port/] [data_in.vst] - Blame information for rev 4

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-- VHDL structural description generated from `data_in`
--              date : Mon Aug 27 06:36:23 2001
 
 
-- Entity Declaration
 
ENTITY data_in IS
  PORT (
  datain : in BIT_VECTOR (31 DOWNTO 0); -- datain
  dt_sended : in BIT;   -- dt_sended
  emp_buf : in BIT;     -- emp_buf
  clk : in BIT; -- clk
  rst : in BIT; -- rst
  req_dt : out BIT;     -- req_dt
  dt_ready : inout BIT; -- dt_ready
  data64in : out BIT_VECTOR (63 DOWNTO 0);      -- data64in
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END data_in;
 
-- Architecture Declaration
 
ARCHITECTURE VST OF data_in IS
  COMPONENT dec1to2
    port (
    a : in BIT_VECTOR(31 DOWNTO 0);     -- a
    sel : in BIT;       -- sel
    clk : in BIT;       -- clk
    rst : in BIT;       -- rst
    o1 : out BIT_VECTOR(31 DOWNTO 0);   -- o1
    o2 : out BIT_VECTOR(31 DOWNTO 0);   -- o2
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT control_datain
    port (
    clk : in BIT;       -- clk
    rst : in BIT;       -- rst
    dt_sended : in BIT; -- dt_sended
    emp_buf : in BIT;   -- emp_buf
    en_bufin : inout BIT;       -- en_bufin
    req_dt : out BIT;   -- req_dt
    dt_ready : inout BIT;       -- dt_ready
    n_block : inout BIT;        -- n_block
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT buf_x2
    port (
    i : in BIT; -- i
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  SIGNAL data64in_t_0 : BIT;    -- data64in_t 0
  SIGNAL data64in_t_1 : BIT;    -- data64in_t 1
  SIGNAL data64in_t_2 : BIT;    -- data64in_t 2
  SIGNAL data64in_t_3 : BIT;    -- data64in_t 3
  SIGNAL data64in_t_4 : BIT;    -- data64in_t 4
  SIGNAL data64in_t_5 : BIT;    -- data64in_t 5
  SIGNAL data64in_t_6 : BIT;    -- data64in_t 6
  SIGNAL data64in_t_7 : BIT;    -- data64in_t 7
  SIGNAL data64in_t_8 : BIT;    -- data64in_t 8
  SIGNAL data64in_t_9 : BIT;    -- data64in_t 9
  SIGNAL data64in_t_10 : BIT;   -- data64in_t 10
  SIGNAL data64in_t_11 : BIT;   -- data64in_t 11
  SIGNAL data64in_t_12 : BIT;   -- data64in_t 12
  SIGNAL data64in_t_13 : BIT;   -- data64in_t 13
  SIGNAL data64in_t_14 : BIT;   -- data64in_t 14
  SIGNAL data64in_t_15 : BIT;   -- data64in_t 15
  SIGNAL data64in_t_16 : BIT;   -- data64in_t 16
  SIGNAL data64in_t_17 : BIT;   -- data64in_t 17
  SIGNAL data64in_t_18 : BIT;   -- data64in_t 18
  SIGNAL data64in_t_19 : BIT;   -- data64in_t 19
  SIGNAL data64in_t_20 : BIT;   -- data64in_t 20
  SIGNAL data64in_t_21 : BIT;   -- data64in_t 21
  SIGNAL data64in_t_22 : BIT;   -- data64in_t 22
  SIGNAL data64in_t_23 : BIT;   -- data64in_t 23
  SIGNAL data64in_t_24 : BIT;   -- data64in_t 24
  SIGNAL data64in_t_25 : BIT;   -- data64in_t 25
  SIGNAL data64in_t_26 : BIT;   -- data64in_t 26
  SIGNAL data64in_t_27 : BIT;   -- data64in_t 27
  SIGNAL data64in_t_28 : BIT;   -- data64in_t 28
  SIGNAL data64in_t_29 : BIT;   -- data64in_t 29
  SIGNAL data64in_t_30 : BIT;   -- data64in_t 30
  SIGNAL data64in_t_31 : BIT;   -- data64in_t 31
  SIGNAL data64in_t_32 : BIT;   -- data64in_t 32
  SIGNAL data64in_t_33 : BIT;   -- data64in_t 33
  SIGNAL data64in_t_34 : BIT;   -- data64in_t 34
  SIGNAL data64in_t_35 : BIT;   -- data64in_t 35
  SIGNAL data64in_t_36 : BIT;   -- data64in_t 36
  SIGNAL data64in_t_37 : BIT;   -- data64in_t 37
  SIGNAL data64in_t_38 : BIT;   -- data64in_t 38
  SIGNAL data64in_t_39 : BIT;   -- data64in_t 39
  SIGNAL data64in_t_40 : BIT;   -- data64in_t 40
  SIGNAL data64in_t_41 : BIT;   -- data64in_t 41
  SIGNAL data64in_t_42 : BIT;   -- data64in_t 42
  SIGNAL data64in_t_43 : BIT;   -- data64in_t 43
  SIGNAL data64in_t_44 : BIT;   -- data64in_t 44
  SIGNAL data64in_t_45 : BIT;   -- data64in_t 45
  SIGNAL data64in_t_46 : BIT;   -- data64in_t 46
  SIGNAL data64in_t_47 : BIT;   -- data64in_t 47
  SIGNAL data64in_t_48 : BIT;   -- data64in_t 48
  SIGNAL data64in_t_49 : BIT;   -- data64in_t 49
  SIGNAL data64in_t_50 : BIT;   -- data64in_t 50
  SIGNAL data64in_t_51 : BIT;   -- data64in_t 51
  SIGNAL data64in_t_52 : BIT;   -- data64in_t 52
  SIGNAL data64in_t_53 : BIT;   -- data64in_t 53
  SIGNAL data64in_t_54 : BIT;   -- data64in_t 54
  SIGNAL data64in_t_55 : BIT;   -- data64in_t 55
  SIGNAL data64in_t_56 : BIT;   -- data64in_t 56
  SIGNAL data64in_t_57 : BIT;   -- data64in_t 57
  SIGNAL data64in_t_58 : BIT;   -- data64in_t 58
  SIGNAL data64in_t_59 : BIT;   -- data64in_t 59
  SIGNAL data64in_t_60 : BIT;   -- data64in_t 60
  SIGNAL data64in_t_61 : BIT;   -- data64in_t 61
  SIGNAL data64in_t_62 : BIT;   -- data64in_t 62
  SIGNAL data64in_t_63 : BIT;   -- data64in_t 63
  SIGNAL en_bufin : BIT;        -- en_bufin
  SIGNAL n_block : BIT; -- n_block
 
BEGIN
 
  dec12 : dec1to2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    o2 => data64in_t_31& data64in_t_30& data64in_t_29& data64in_t_28& data64in_t_27& data64in_t_26& data64in_t_25& data64in_t_24& data64in_t_23& data64in_t_22& data64in_t_21& data64in_t_20& data64in_t_19& data64in_t_18& data64in_t_17& data64in_t_16& data64in_t_15& data64in_t_14& data64in_t_13& data64in_t_12& data64in_t_11& data64in_t_10& data64in_t_9& data64in_t_8& data64in_t_7& data64in_t_6& data64in_t_5& data64in_t_4& data64in_t_3& data64in_t_2& data64in_t_1& data64in_t_0,
    o1 => data64in_t_63& data64in_t_62& data64in_t_61& data64in_t_60& data64in_t_59& data64in_t_58& data64in_t_57& data64in_t_56& data64in_t_55& data64in_t_54& data64in_t_53& data64in_t_52& data64in_t_51& data64in_t_50& data64in_t_49& data64in_t_48& data64in_t_47& data64in_t_46& data64in_t_45& data64in_t_44& data64in_t_43& data64in_t_42& data64in_t_41& data64in_t_40& data64in_t_39& data64in_t_38& data64in_t_37& data64in_t_36& data64in_t_35& data64in_t_34& data64in_t_33& data64in_t_32,
    rst => rst,
    clk => en_bufin,
    sel => n_block,
    a => datain(31)& datain(30)& datain(29)& datain(28)& datain(27)& datain(26)& datain(25)& datain(24)& datain(23)& datain(22)& datain(21)& datain(20)& datain(19)& datain(18)& datain(17)& datain(16)& datain(15)& datain(14)& datain(13)& datain(12)& datain(11)& datain(10)& datain(9)& datain(8)& datain(7)& datain(6)& datain(5)& datain(4)& datain(3)& datain(2)& datain(1)& datain(0));
  ctrl_dtin : control_datain
    PORT MAP (
    vss => vss,
    vdd => vdd,
    n_block => n_block,
    dt_ready => dt_ready,
    req_dt => req_dt,
    en_bufin => en_bufin,
    emp_buf => emp_buf,
    dt_sended => dt_sended,
    rst => rst,
    clk => clk);
  buf0 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(0),
    i => data64in_t_0);
  buf1 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(1),
    i => data64in_t_1);
  buf2 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(2),
    i => data64in_t_2);
  buf3 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(3),
    i => data64in_t_3);
  buf4 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(4),
    i => data64in_t_4);
  buf5 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(5),
    i => data64in_t_5);
  buf6 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(6),
    i => data64in_t_6);
  buf7 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(7),
    i => data64in_t_7);
  buf8 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(8),
    i => data64in_t_8);
  buf9 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(9),
    i => data64in_t_9);
  buf10 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(10),
    i => data64in_t_10);
  buf11 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(11),
    i => data64in_t_11);
  buf12 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(12),
    i => data64in_t_12);
  buf13 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(13),
    i => data64in_t_13);
  buf14 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(14),
    i => data64in_t_14);
  buf15 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(15),
    i => data64in_t_15);
  buf16 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(16),
    i => data64in_t_16);
  buf17 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(17),
    i => data64in_t_17);
  buf18 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(18),
    i => data64in_t_18);
  buf19 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(19),
    i => data64in_t_19);
  buf20 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(20),
    i => data64in_t_20);
  buf21 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(21),
    i => data64in_t_21);
  buf22 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(22),
    i => data64in_t_22);
  buf23 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(23),
    i => data64in_t_23);
  buf24 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(24),
    i => data64in_t_24);
  buf25 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(25),
    i => data64in_t_25);
  buf26 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(26),
    i => data64in_t_26);
  buf27 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(27),
    i => data64in_t_27);
  buf28 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(28),
    i => data64in_t_28);
  buf29 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(29),
    i => data64in_t_29);
  buf30 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(30),
    i => data64in_t_30);
  buf31 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(31),
    i => data64in_t_31);
  buf32 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(32),
    i => data64in_t_32);
  buf33 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(33),
    i => data64in_t_33);
  buf34 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(34),
    i => data64in_t_34);
  buf35 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(35),
    i => data64in_t_35);
  buf36 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(36),
    i => data64in_t_36);
  buf37 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(37),
    i => data64in_t_37);
  buf38 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(38),
    i => data64in_t_38);
  buf39 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(39),
    i => data64in_t_39);
  buf40 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(40),
    i => data64in_t_40);
  buf41 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(41),
    i => data64in_t_41);
  buf42 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(42),
    i => data64in_t_42);
  buf43 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(43),
    i => data64in_t_43);
  buf44 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(44),
    i => data64in_t_44);
  buf45 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(45),
    i => data64in_t_45);
  buf46 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(46),
    i => data64in_t_46);
  buf47 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(47),
    i => data64in_t_47);
  buf48 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(48),
    i => data64in_t_48);
  buf49 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(49),
    i => data64in_t_49);
  buf50 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(50),
    i => data64in_t_50);
  buf51 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(51),
    i => data64in_t_51);
  buf52 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(52),
    i => data64in_t_52);
  buf53 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(53),
    i => data64in_t_53);
  buf54 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(54),
    i => data64in_t_54);
  buf55 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(55),
    i => data64in_t_55);
  buf56 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(56),
    i => data64in_t_56);
  buf57 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(57),
    i => data64in_t_57);
  buf58 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(58),
    i => data64in_t_58);
  buf59 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(59),
    i => data64in_t_59);
  buf60 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(60),
    i => data64in_t_60);
  buf61 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(61),
    i => data64in_t_61);
  buf62 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(62),
    i => data64in_t_62);
  buf63 : buf_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => data64in(63),
    i => data64in_t_63);
 
end VST;

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Subversion Repositories structural_vhdl

[/] [structural_vhdl/] [trunk/] [inout_port/] [data_in.vst] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	marta	-- VHDL structural description generated from `data_in`
2			`-- date : Mon Aug 27 06:36:23 2001`
3
4
5			`-- Entity Declaration`
6
7			`ENTITY data_in IS`
8			`PORT (`
9			`datain : in BIT_VECTOR (31 DOWNTO 0); -- datain`
10			`dt_sended : in BIT; -- dt_sended`
11			`emp_buf : in BIT; -- emp_buf`
12			`clk : in BIT; -- clk`
13			`rst : in BIT; -- rst`
14			`req_dt : out BIT; -- req_dt`
15			`dt_ready : inout BIT; -- dt_ready`
16			`data64in : out BIT_VECTOR (63 DOWNTO 0); -- data64in`
17			`vdd : in BIT; -- vdd`
18			`vss : in BIT -- vss`
19			`);`
20			`END data_in;`
21
22			`-- Architecture Declaration`
23
24			`ARCHITECTURE VST OF data_in IS`
25			`COMPONENT dec1to2`
26			`port (`
27			`a : in BIT_VECTOR(31 DOWNTO 0); -- a`
28			`sel : in BIT; -- sel`
29			`clk : in BIT; -- clk`
30			`rst : in BIT; -- rst`
31			`o1 : out BIT_VECTOR(31 DOWNTO 0); -- o1`
32			`o2 : out BIT_VECTOR(31 DOWNTO 0); -- o2`
33			`vdd : in BIT; -- vdd`
34			`vss : in BIT -- vss`
35			`);`
36			`END COMPONENT;`
37
38			`COMPONENT control_datain`
39			`port (`
40			`clk : in BIT; -- clk`
41			`rst : in BIT; -- rst`
42			`dt_sended : in BIT; -- dt_sended`
43			`emp_buf : in BIT; -- emp_buf`
44			`en_bufin : inout BIT; -- en_bufin`
45			`req_dt : out BIT; -- req_dt`
46			`dt_ready : inout BIT; -- dt_ready`
47			`n_block : inout BIT; -- n_block`
48			`vdd : in BIT; -- vdd`
49			`vss : in BIT -- vss`
50			`);`
51			`END COMPONENT;`
52
53			`COMPONENT buf_x2`
54			`port (`
55			`i : in BIT; -- i`
56			`q : out BIT; -- q`
57			`vdd : in BIT; -- vdd`
58			`vss : in BIT -- vss`
59			`);`
60			`END COMPONENT;`
61
62			`SIGNAL data64in_t_0 : BIT; -- data64in_t 0`
63			`SIGNAL data64in_t_1 : BIT; -- data64in_t 1`
64			`SIGNAL data64in_t_2 : BIT; -- data64in_t 2`
65			`SIGNAL data64in_t_3 : BIT; -- data64in_t 3`
66			`SIGNAL data64in_t_4 : BIT; -- data64in_t 4`
67			`SIGNAL data64in_t_5 : BIT; -- data64in_t 5`
68			`SIGNAL data64in_t_6 : BIT; -- data64in_t 6`
69			`SIGNAL data64in_t_7 : BIT; -- data64in_t 7`
70			`SIGNAL data64in_t_8 : BIT; -- data64in_t 8`
71			`SIGNAL data64in_t_9 : BIT; -- data64in_t 9`
72			`SIGNAL data64in_t_10 : BIT; -- data64in_t 10`
73			`SIGNAL data64in_t_11 : BIT; -- data64in_t 11`
74			`SIGNAL data64in_t_12 : BIT; -- data64in_t 12`
75			`SIGNAL data64in_t_13 : BIT; -- data64in_t 13`
76			`SIGNAL data64in_t_14 : BIT; -- data64in_t 14`
77			`SIGNAL data64in_t_15 : BIT; -- data64in_t 15`
78			`SIGNAL data64in_t_16 : BIT; -- data64in_t 16`
79			`SIGNAL data64in_t_17 : BIT; -- data64in_t 17`
80			`SIGNAL data64in_t_18 : BIT; -- data64in_t 18`
81			`SIGNAL data64in_t_19 : BIT; -- data64in_t 19`
82			`SIGNAL data64in_t_20 : BIT; -- data64in_t 20`
83			`SIGNAL data64in_t_21 : BIT; -- data64in_t 21`
84			`SIGNAL data64in_t_22 : BIT; -- data64in_t 22`
85			`SIGNAL data64in_t_23 : BIT; -- data64in_t 23`
86			`SIGNAL data64in_t_24 : BIT; -- data64in_t 24`
87			`SIGNAL data64in_t_25 : BIT; -- data64in_t 25`
88			`SIGNAL data64in_t_26 : BIT; -- data64in_t 26`
89			`SIGNAL data64in_t_27 : BIT; -- data64in_t 27`
90			`SIGNAL data64in_t_28 : BIT; -- data64in_t 28`
91			`SIGNAL data64in_t_29 : BIT; -- data64in_t 29`
92			`SIGNAL data64in_t_30 : BIT; -- data64in_t 30`
93			`SIGNAL data64in_t_31 : BIT; -- data64in_t 31`
94			`SIGNAL data64in_t_32 : BIT; -- data64in_t 32`
95			`SIGNAL data64in_t_33 : BIT; -- data64in_t 33`
96			`SIGNAL data64in_t_34 : BIT; -- data64in_t 34`
97			`SIGNAL data64in_t_35 : BIT; -- data64in_t 35`
98			`SIGNAL data64in_t_36 : BIT; -- data64in_t 36`
99			`SIGNAL data64in_t_37 : BIT; -- data64in_t 37`
100			`SIGNAL data64in_t_38 : BIT; -- data64in_t 38`
101			`SIGNAL data64in_t_39 : BIT; -- data64in_t 39`
102			`SIGNAL data64in_t_40 : BIT; -- data64in_t 40`
103			`SIGNAL data64in_t_41 : BIT; -- data64in_t 41`
104			`SIGNAL data64in_t_42 : BIT; -- data64in_t 42`
105			`SIGNAL data64in_t_43 : BIT; -- data64in_t 43`
106			`SIGNAL data64in_t_44 : BIT; -- data64in_t 44`
107			`SIGNAL data64in_t_45 : BIT; -- data64in_t 45`
108			`SIGNAL data64in_t_46 : BIT; -- data64in_t 46`
109			`SIGNAL data64in_t_47 : BIT; -- data64in_t 47`
110			`SIGNAL data64in_t_48 : BIT; -- data64in_t 48`
111			`SIGNAL data64in_t_49 : BIT; -- data64in_t 49`
112			`SIGNAL data64in_t_50 : BIT; -- data64in_t 50`
113			`SIGNAL data64in_t_51 : BIT; -- data64in_t 51`
114			`SIGNAL data64in_t_52 : BIT; -- data64in_t 52`
115			`SIGNAL data64in_t_53 : BIT; -- data64in_t 53`
116			`SIGNAL data64in_t_54 : BIT; -- data64in_t 54`
117			`SIGNAL data64in_t_55 : BIT; -- data64in_t 55`
118			`SIGNAL data64in_t_56 : BIT; -- data64in_t 56`
119			`SIGNAL data64in_t_57 : BIT; -- data64in_t 57`
120			`SIGNAL data64in_t_58 : BIT; -- data64in_t 58`
121			`SIGNAL data64in_t_59 : BIT; -- data64in_t 59`
122			`SIGNAL data64in_t_60 : BIT; -- data64in_t 60`
123			`SIGNAL data64in_t_61 : BIT; -- data64in_t 61`
124			`SIGNAL data64in_t_62 : BIT; -- data64in_t 62`
125			`SIGNAL data64in_t_63 : BIT; -- data64in_t 63`
126			`SIGNAL en_bufin : BIT; -- en_bufin`
127			`SIGNAL n_block : BIT; -- n_block`
128
129			`BEGIN`
130
131			`dec12 : dec1to2`
132			`PORT MAP (`
133			`vss => vss,`
134			`vdd => vdd,`
135			`o2 => data64in_t_31& data64in_t_30& data64in_t_29& data64in_t_28& data64in_t_27& data64in_t_26& data64in_t_25& data64in_t_24& data64in_t_23& data64in_t_22& data64in_t_21& data64in_t_20& data64in_t_19& data64in_t_18& data64in_t_17& data64in_t_16& data64in_t_15& data64in_t_14& data64in_t_13& data64in_t_12& data64in_t_11& data64in_t_10& data64in_t_9& data64in_t_8& data64in_t_7& data64in_t_6& data64in_t_5& data64in_t_4& data64in_t_3& data64in_t_2& data64in_t_1& data64in_t_0,`
136			`o1 => data64in_t_63& data64in_t_62& data64in_t_61& data64in_t_60& data64in_t_59& data64in_t_58& data64in_t_57& data64in_t_56& data64in_t_55& data64in_t_54& data64in_t_53& data64in_t_52& data64in_t_51& data64in_t_50& data64in_t_49& data64in_t_48& data64in_t_47& data64in_t_46& data64in_t_45& data64in_t_44& data64in_t_43& data64in_t_42& data64in_t_41& data64in_t_40& data64in_t_39& data64in_t_38& data64in_t_37& data64in_t_36& data64in_t_35& data64in_t_34& data64in_t_33& data64in_t_32,`
137			`rst => rst,`
138			`clk => en_bufin,`
139			`sel => n_block,`
140			`a => datain(31)& datain(30)& datain(29)& datain(28)& datain(27)& datain(26)& datain(25)& datain(24)& datain(23)& datain(22)& datain(21)& datain(20)& datain(19)& datain(18)& datain(17)& datain(16)& datain(15)& datain(14)& datain(13)& datain(12)& datain(11)& datain(10)& datain(9)& datain(8)& datain(7)& datain(6)& datain(5)& datain(4)& datain(3)& datain(2)& datain(1)& datain(0));`
141			`ctrl_dtin : control_datain`
142			`PORT MAP (`
143			`vss => vss,`
144			`vdd => vdd,`
145			`n_block => n_block,`
146			`dt_ready => dt_ready,`
147			`req_dt => req_dt,`
148			`en_bufin => en_bufin,`
149			`emp_buf => emp_buf,`
150			`dt_sended => dt_sended,`
151			`rst => rst,`
152			`clk => clk);`
153			`buf0 : buf_x2`
154			`PORT MAP (`
155			`vss => vss,`
156			`vdd => vdd,`
157			`q => data64in(0),`
158			`i => data64in_t_0);`
159			`buf1 : buf_x2`
160			`PORT MAP (`
161			`vss => vss,`
162			`vdd => vdd,`
163			`q => data64in(1),`
164			`i => data64in_t_1);`
165			`buf2 : buf_x2`
166			`PORT MAP (`
167			`vss => vss,`
168			`vdd => vdd,`
169			`q => data64in(2),`
170			`i => data64in_t_2);`
171			`buf3 : buf_x2`
172			`PORT MAP (`
173			`vss => vss,`
174			`vdd => vdd,`
175			`q => data64in(3),`
176			`i => data64in_t_3);`
177			`buf4 : buf_x2`
178			`PORT MAP (`
179			`vss => vss,`
180			`vdd => vdd,`
181			`q => data64in(4),`
182			`i => data64in_t_4);`
183			`buf5 : buf_x2`
184			`PORT MAP (`
185			`vss => vss,`
186			`vdd => vdd,`
187			`q => data64in(5),`
188			`i => data64in_t_5);`
189			`buf6 : buf_x2`
190			`PORT MAP (`
191			`vss => vss,`
192			`vdd => vdd,`
193			`q => data64in(6),`
194			`i => data64in_t_6);`
195			`buf7 : buf_x2`
196			`PORT MAP (`
197			`vss => vss,`
198			`vdd => vdd,`
199			`q => data64in(7),`
200			`i => data64in_t_7);`
201			`buf8 : buf_x2`
202			`PORT MAP (`
203			`vss => vss,`
204			`vdd => vdd,`
205			`q => data64in(8),`
206			`i => data64in_t_8);`
207			`buf9 : buf_x2`
208			`PORT MAP (`
209			`vss => vss,`
210			`vdd => vdd,`
211			`q => data64in(9),`
212			`i => data64in_t_9);`
213			`buf10 : buf_x2`
214			`PORT MAP (`
215			`vss => vss,`
216			`vdd => vdd,`
217			`q => data64in(10),`
218			`i => data64in_t_10);`
219			`buf11 : buf_x2`
220			`PORT MAP (`
221			`vss => vss,`
222			`vdd => vdd,`
223			`q => data64in(11),`
224			`i => data64in_t_11);`
225			`buf12 : buf_x2`
226			`PORT MAP (`
227			`vss => vss,`
228			`vdd => vdd,`
229			`q => data64in(12),`
230			`i => data64in_t_12);`
231			`buf13 : buf_x2`
232			`PORT MAP (`
233			`vss => vss,`
234			`vdd => vdd,`
235			`q => data64in(13),`
236			`i => data64in_t_13);`
237			`buf14 : buf_x2`
238			`PORT MAP (`
239			`vss => vss,`
240			`vdd => vdd,`
241			`q => data64in(14),`
242			`i => data64in_t_14);`
243			`buf15 : buf_x2`
244			`PORT MAP (`
245			`vss => vss,`
246			`vdd => vdd,`
247			`q => data64in(15),`
248			`i => data64in_t_15);`
249			`buf16 : buf_x2`
250			`PORT MAP (`
251			`vss => vss,`
252			`vdd => vdd,`
253			`q => data64in(16),`
254			`i => data64in_t_16);`
255			`buf17 : buf_x2`
256			`PORT MAP (`
257			`vss => vss,`
258			`vdd => vdd,`
259			`q => data64in(17),`
260			`i => data64in_t_17);`
261			`buf18 : buf_x2`
262			`PORT MAP (`
263			`vss => vss,`
264			`vdd => vdd,`
265			`q => data64in(18),`
266			`i => data64in_t_18);`
267			`buf19 : buf_x2`
268			`PORT MAP (`
269			`vss => vss,`
270			`vdd => vdd,`
271			`q => data64in(19),`
272			`i => data64in_t_19);`
273			`buf20 : buf_x2`
274			`PORT MAP (`
275			`vss => vss,`
276			`vdd => vdd,`
277			`q => data64in(20),`
278			`i => data64in_t_20);`
279			`buf21 : buf_x2`
280			`PORT MAP (`
281			`vss => vss,`
282			`vdd => vdd,`
283			`q => data64in(21),`
284			`i => data64in_t_21);`
285			`buf22 : buf_x2`
286			`PORT MAP (`
287			`vss => vss,`
288			`vdd => vdd,`
289			`q => data64in(22),`
290			`i => data64in_t_22);`
291			`buf23 : buf_x2`
292			`PORT MAP (`
293			`vss => vss,`
294			`vdd => vdd,`
295			`q => data64in(23),`
296			`i => data64in_t_23);`
297			`buf24 : buf_x2`
298			`PORT MAP (`
299			`vss => vss,`
300			`vdd => vdd,`
301			`q => data64in(24),`
302			`i => data64in_t_24);`
303			`buf25 : buf_x2`
304			`PORT MAP (`
305			`vss => vss,`
306			`vdd => vdd,`
307			`q => data64in(25),`
308			`i => data64in_t_25);`
309			`buf26 : buf_x2`
310			`PORT MAP (`
311			`vss => vss,`
312			`vdd => vdd,`
313			`q => data64in(26),`
314			`i => data64in_t_26);`
315			`buf27 : buf_x2`
316			`PORT MAP (`
317			`vss => vss,`
318			`vdd => vdd,`
319			`q => data64in(27),`
320			`i => data64in_t_27);`
321			`buf28 : buf_x2`
322			`PORT MAP (`
323			`vss => vss,`
324			`vdd => vdd,`
325			`q => data64in(28),`
326			`i => data64in_t_28);`
327			`buf29 : buf_x2`
328			`PORT MAP (`
329			`vss => vss,`
330			`vdd => vdd,`
331			`q => data64in(29),`
332			`i => data64in_t_29);`
333			`buf30 : buf_x2`
334			`PORT MAP (`
335			`vss => vss,`
336			`vdd => vdd,`
337			`q => data64in(30),`
338			`i => data64in_t_30);`
339			`buf31 : buf_x2`
340			`PORT MAP (`
341			`vss => vss,`
342			`vdd => vdd,`
343			`q => data64in(31),`
344			`i => data64in_t_31);`
345			`buf32 : buf_x2`
346			`PORT MAP (`
347			`vss => vss,`
348			`vdd => vdd,`
349			`q => data64in(32),`
350			`i => data64in_t_32);`
351			`buf33 : buf_x2`
352			`PORT MAP (`
353			`vss => vss,`
354			`vdd => vdd,`
355			`q => data64in(33),`
356			`i => data64in_t_33);`
357			`buf34 : buf_x2`
358			`PORT MAP (`
359			`vss => vss,`
360			`vdd => vdd,`
361			`q => data64in(34),`
362			`i => data64in_t_34);`
363			`buf35 : buf_x2`
364			`PORT MAP (`
365			`vss => vss,`
366			`vdd => vdd,`
367			`q => data64in(35),`
368			`i => data64in_t_35);`
369			`buf36 : buf_x2`
370			`PORT MAP (`
371			`vss => vss,`
372			`vdd => vdd,`
373			`q => data64in(36),`
374			`i => data64in_t_36);`
375			`buf37 : buf_x2`
376			`PORT MAP (`
377			`vss => vss,`
378			`vdd => vdd,`
379			`q => data64in(37),`
380			`i => data64in_t_37);`
381			`buf38 : buf_x2`
382			`PORT MAP (`
383			`vss => vss,`
384			`vdd => vdd,`
385			`q => data64in(38),`
386			`i => data64in_t_38);`
387			`buf39 : buf_x2`
388			`PORT MAP (`
389			`vss => vss,`
390			`vdd => vdd,`
391			`q => data64in(39),`
392			`i => data64in_t_39);`
393			`buf40 : buf_x2`
394			`PORT MAP (`
395			`vss => vss,`
396			`vdd => vdd,`
397			`q => data64in(40),`
398			`i => data64in_t_40);`
399			`buf41 : buf_x2`
400			`PORT MAP (`
401			`vss => vss,`
402			`vdd => vdd,`
403			`q => data64in(41),`
404			`i => data64in_t_41);`
405			`buf42 : buf_x2`
406			`PORT MAP (`
407			`vss => vss,`
408			`vdd => vdd,`
409			`q => data64in(42),`
410			`i => data64in_t_42);`
411			`buf43 : buf_x2`
412			`PORT MAP (`
413			`vss => vss,`
414			`vdd => vdd,`
415			`q => data64in(43),`
416			`i => data64in_t_43);`
417			`buf44 : buf_x2`
418			`PORT MAP (`
419			`vss => vss,`
420			`vdd => vdd,`
421			`q => data64in(44),`
422			`i => data64in_t_44);`
423			`buf45 : buf_x2`
424			`PORT MAP (`
425			`vss => vss,`
426			`vdd => vdd,`
427			`q => data64in(45),`
428			`i => data64in_t_45);`
429			`buf46 : buf_x2`
430			`PORT MAP (`
431			`vss => vss,`
432			`vdd => vdd,`
433			`q => data64in(46),`
434			`i => data64in_t_46);`
435			`buf47 : buf_x2`
436			`PORT MAP (`
437			`vss => vss,`
438			`vdd => vdd,`
439			`q => data64in(47),`
440			`i => data64in_t_47);`
441			`buf48 : buf_x2`
442			`PORT MAP (`
443			`vss => vss,`
444			`vdd => vdd,`
445			`q => data64in(48),`
446			`i => data64in_t_48);`
447			`buf49 : buf_x2`
448			`PORT MAP (`
449			`vss => vss,`
450			`vdd => vdd,`
451			`q => data64in(49),`
452			`i => data64in_t_49);`
453			`buf50 : buf_x2`
454			`PORT MAP (`
455			`vss => vss,`
456			`vdd => vdd,`
457			`q => data64in(50),`
458			`i => data64in_t_50);`
459			`buf51 : buf_x2`
460			`PORT MAP (`
461			`vss => vss,`
462			`vdd => vdd,`
463			`q => data64in(51),`
464			`i => data64in_t_51);`
465			`buf52 : buf_x2`
466			`PORT MAP (`
467			`vss => vss,`
468			`vdd => vdd,`
469			`q => data64in(52),`
470			`i => data64in_t_52);`
471			`buf53 : buf_x2`
472			`PORT MAP (`
473			`vss => vss,`
474			`vdd => vdd,`
475			`q => data64in(53),`
476			`i => data64in_t_53);`
477			`buf54 : buf_x2`
478			`PORT MAP (`
479			`vss => vss,`
480			`vdd => vdd,`
481			`q => data64in(54),`
482			`i => data64in_t_54);`
483			`buf55 : buf_x2`
484			`PORT MAP (`
485			`vss => vss,`
486			`vdd => vdd,`
487			`q => data64in(55),`
488			`i => data64in_t_55);`
489			`buf56 : buf_x2`
490			`PORT MAP (`
491			`vss => vss,`
492			`vdd => vdd,`
493			`q => data64in(56),`
494			`i => data64in_t_56);`
495			`buf57 : buf_x2`
496			`PORT MAP (`
497			`vss => vss,`
498			`vdd => vdd,`
499			`q => data64in(57),`
500			`i => data64in_t_57);`
501			`buf58 : buf_x2`
502			`PORT MAP (`
503			`vss => vss,`
504			`vdd => vdd,`
505			`q => data64in(58),`
506			`i => data64in_t_58);`
507			`buf59 : buf_x2`
508			`PORT MAP (`
509			`vss => vss,`
510			`vdd => vdd,`
511			`q => data64in(59),`
512			`i => data64in_t_59);`
513			`buf60 : buf_x2`
514			`PORT MAP (`
515			`vss => vss,`
516			`vdd => vdd,`
517			`q => data64in(60),`
518			`i => data64in_t_60);`
519			`buf61 : buf_x2`
520			`PORT MAP (`
521			`vss => vss,`
522			`vdd => vdd,`
523			`q => data64in(61),`
524			`i => data64in_t_61);`
525			`buf62 : buf_x2`
526			`PORT MAP (`
527			`vss => vss,`
528			`vdd => vdd,`
529			`q => data64in(62),`
530			`i => data64in_t_62);`
531			`buf63 : buf_x2`
532			`PORT MAP (`
533			`vss => vss,`
534			`vdd => vdd,`
535			`q => data64in(63),`
536			`i => data64in_t_63);`
537
538			`end VST;`