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[/] [structural_vhdl/] [trunk/] [inout_port/] [data_in_glop.vst] - Blame information for rev 4

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1 2 marta 
-- VHDL structural description generated from `data_in_glop`
2 
--              date : Mon Aug 27 00:55:11 2001
3 
 
4 
 
5 
-- Entity Declaration
6 
 
7 
ENTITY data_in_glop IS
8 
  PORT (
9 
  datain : in BIT_VECTOR (31 DOWNTO 0); -- datain
10 
  dt_sended : in BIT;   -- dt_sended
11 
  emp_buf : in BIT;     -- emp_buf
12 
  clk : in BIT; -- clk
13 
  rst : in BIT; -- rst
14 
  req_dt : out BIT;     -- req_dt
15 
  dt_ready : inout BIT; -- dt_ready
16 
  data64in : inout BIT_VECTOR (63 DOWNTO 0);    -- data64in
17 
  vdd : in BIT; -- vdd
18 
  vss : in BIT  -- vss
19 
  );
20 
END data_in_glop;
21 
 
22 
-- Architecture Declaration
23 
 
24 
ARCHITECTURE VST OF data_in_glop IS
25 
  COMPONENT inv_x2
26 
    port (
27 
    i : in BIT; -- i
28 
    nq : out BIT;       -- nq
29 
    vdd : in BIT;       -- vdd
30 
    vss : in BIT        -- vss
31 
    );
32 
  END COMPONENT;
33 
 
34 
  COMPONENT no3_x4
35 
    port (
36 
    i0 : in BIT;        -- i0
37 
    i1 : in BIT;        -- i1
38 
    i2 : in BIT;        -- i2
39 
    nq : out BIT;       -- nq
40 
    vdd : in BIT;       -- vdd
41 
    vss : in BIT        -- vss
42 
    );
43 
  END COMPONENT;
44 
 
45 
  COMPONENT no2_x4
46 
    port (
47 
    i0 : in BIT;        -- i0
48 
    i1 : in BIT;        -- i1
49 
    nq : out BIT;       -- nq
50 
    vdd : in BIT;       -- vdd
51 
    vss : in BIT        -- vss
52 
    );
53 
  END COMPONENT;
54 
 
55 
  COMPONENT no4_x1
56 
    port (
57 
    i0 : in BIT;        -- i0
58 
    i1 : in BIT;        -- i1
59 
    i2 : in BIT;        -- i2
60 
    i3 : in BIT;        -- i3
61 
    nq : out BIT;       -- nq
62 
    vdd : in BIT;       -- vdd
63 
    vss : in BIT        -- vss
64 
    );
65 
  END COMPONENT;
66 
 
67 
  COMPONENT ao22_x2
68 
    port (
69 
    i0 : in BIT;        -- i0
70 
    i1 : in BIT;        -- i1
71 
    i2 : in BIT;        -- i2
72 
    q : out BIT;        -- q
73 
    vdd : in BIT;       -- vdd
74 
    vss : in BIT        -- vss
75 
    );
76 
  END COMPONENT;
77 
 
78 
  COMPONENT xr2_x1
79 
    port (
80 
    i0 : in BIT;        -- i0
81 
    i1 : in BIT;        -- i1
82 
    q : out BIT;        -- q
83 
    vdd : in BIT;       -- vdd
84 
    vss : in BIT        -- vss
85 
    );
86 
  END COMPONENT;
87 
 
88 
  COMPONENT o3_x2
89 
    port (
90 
    i0 : in BIT;        -- i0
91 
    i1 : in BIT;        -- i1
92 
    i2 : in BIT;        -- i2
93 
    q : out BIT;        -- q
94 
    vdd : in BIT;       -- vdd
95 
    vss : in BIT        -- vss
96 
    );
97 
  END COMPONENT;
98 
 
99 
  COMPONENT nao22_x1
100 
    port (
101 
    i0 : in BIT;        -- i0
102 
    i1 : in BIT;        -- i1
103 
    i2 : in BIT;        -- i2
104 
    nq : out BIT;       -- nq
105 
    vdd : in BIT;       -- vdd
106 
    vss : in BIT        -- vss
107 
    );
108 
  END COMPONENT;
109 
 
110 
  COMPONENT an12_x1
111 
    port (
112 
    i0 : in BIT;        -- i0
113 
    i1 : in BIT;        -- i1
114 
    q : out BIT;        -- q
115 
    vdd : in BIT;       -- vdd
116 
    vss : in BIT        -- vss
117 
    );
118 
  END COMPONENT;
119 
 
120 
  COMPONENT na2_x1
121 
    port (
122 
    i0 : in BIT;        -- i0
123 
    i1 : in BIT;        -- i1
124 
    nq : out BIT;       -- nq
125 
    vdd : in BIT;       -- vdd
126 
    vss : in BIT        -- vss
127 
    );
128 
  END COMPONENT;
129 
 
130 
  COMPONENT no3_x1
131 
    port (
132 
    i0 : in BIT;        -- i0
133 
    i1 : in BIT;        -- i1
134 
    i2 : in BIT;        -- i2
135 
    nq : out BIT;       -- nq
136 
    vdd : in BIT;       -- vdd
137 
    vss : in BIT        -- vss
138 
    );
139 
  END COMPONENT;
140 
 
141 
  COMPONENT o2_x2
142 
    port (
143 
    i0 : in BIT;        -- i0
144 
    i1 : in BIT;        -- i1
145 
    q : out BIT;        -- q
146 
    vdd : in BIT;       -- vdd
147 
    vss : in BIT        -- vss
148 
    );
149 
  END COMPONENT;
150 
 
151 
  COMPONENT oa22_x2
152 
    port (
153 
    i0 : in BIT;        -- i0
154 
    i1 : in BIT;        -- i1
155 
    i2 : in BIT;        -- i2
156 
    q : out BIT;        -- q
157 
    vdd : in BIT;       -- vdd
158 
    vss : in BIT        -- vss
159 
    );
160 
  END COMPONENT;
161 
 
162 
  COMPONENT a4_x2
163 
    port (
164 
    i0 : in BIT;        -- i0
165 
    i1 : in BIT;        -- i1
166 
    i2 : in BIT;        -- i2
167 
    i3 : in BIT;        -- i3
168 
    q : out BIT;        -- q
169 
    vdd : in BIT;       -- vdd
170 
    vss : in BIT        -- vss
171 
    );
172 
  END COMPONENT;
173 
 
174 
  COMPONENT sff1_x4
175 
    port (
176 
    ck : in BIT;        -- ck
177 
    i : in BIT; -- i
178 
    q : out BIT;        -- q
179 
    vdd : in BIT;       -- vdd
180 
    vss : in BIT        -- vss
181 
    );
182 
  END COMPONENT;
183 
 
184 
  COMPONENT inv_x1
185 
    port (
186 
    i : in BIT; -- i
187 
    nq : out BIT;       -- nq
188 
    vdd : in BIT;       -- vdd
189 
    vss : in BIT        -- vss
190 
    );
191 
  END COMPONENT;
192 
 
193 
  COMPONENT a2_x2
194 
    port (
195 
    i0 : in BIT;        -- i0
196 
    i1 : in BIT;        -- i1
197 
    q : out BIT;        -- q
198 
    vdd : in BIT;       -- vdd
199 
    vss : in BIT        -- vss
200 
    );
201 
  END COMPONENT;
202 
 
203 
  COMPONENT buf_x2
204 
    port (
205 
    i : in BIT; -- i
206 
    q : out BIT;        -- q
207 
    vdd : in BIT;       -- vdd
208 
    vss : in BIT        -- vss
209 
    );
210 
  END COMPONENT;
211 
 
212 
  SIGNAL o1_16 : BIT;   -- o1_16
213 
  SIGNAL en_bufin_c : BIT;      -- en_bufin_c
214 
  SIGNAL netops1414 : BIT;      -- netops1414
215 
  SIGNAL rg1_latch0_o_an1 : BIT;        -- rg1.latch0.o_an1
216 
  SIGNAL rg1_latch0_o_an2 : BIT;        -- rg1.latch0.o_an2
217 
  SIGNAL rg1_latch0_o_inv : BIT;        -- rg1.latch0.o_inv
218 
  SIGNAL rg1_latch0_o_nor2 : BIT;       -- rg1.latch0.o_nor2
219 
  SIGNAL o1_17 : BIT;   -- o1_17
220 
  SIGNAL rg1_latch1_o_an1 : BIT;        -- rg1.latch1.o_an1
221 
  SIGNAL rg1_latch1_o_an2 : BIT;        -- rg1.latch1.o_an2
222 
  SIGNAL rg1_latch1_o_inv : BIT;        -- rg1.latch1.o_inv
223 
  SIGNAL rg1_latch1_o_nor2 : BIT;       -- rg1.latch1.o_nor2
224 
  SIGNAL o1_18 : BIT;   -- o1_18
225 
  SIGNAL rg1_latch2_o_an1 : BIT;        -- rg1.latch2.o_an1
226 
  SIGNAL rg1_latch2_o_an2 : BIT;        -- rg1.latch2.o_an2
227 
  SIGNAL rg1_latch2_o_inv : BIT;        -- rg1.latch2.o_inv
228 
  SIGNAL rg1_latch2_o_nor2 : BIT;       -- rg1.latch2.o_nor2
229 
  SIGNAL o1_19 : BIT;   -- o1_19
230 
  SIGNAL rg1_latch3_o_an1 : BIT;        -- rg1.latch3.o_an1
231 
  SIGNAL rg1_latch3_o_an2 : BIT;        -- rg1.latch3.o_an2
232 
  SIGNAL rg1_latch3_o_inv : BIT;        -- rg1.latch3.o_inv
233 
  SIGNAL rg1_latch3_o_nor2 : BIT;       -- rg1.latch3.o_nor2
234 
  SIGNAL o1_20 : BIT;   -- o1_20
235 
  SIGNAL rg1_latch4_o_an1 : BIT;        -- rg1.latch4.o_an1
236 
  SIGNAL rg1_latch4_o_an2 : BIT;        -- rg1.latch4.o_an2
237 
  SIGNAL rg1_latch4_o_inv : BIT;        -- rg1.latch4.o_inv
238 
  SIGNAL rg1_latch4_o_nor2 : BIT;       -- rg1.latch4.o_nor2
239 
  SIGNAL o1_21 : BIT;   -- o1_21
240 
  SIGNAL rg1_latch5_o_an1 : BIT;        -- rg1.latch5.o_an1
241 
  SIGNAL rg1_latch5_o_an2 : BIT;        -- rg1.latch5.o_an2
242 
  SIGNAL rg1_latch5_o_inv : BIT;        -- rg1.latch5.o_inv
243 
  SIGNAL rg1_latch5_o_nor2 : BIT;       -- rg1.latch5.o_nor2
244 
  SIGNAL o1_22 : BIT;   -- o1_22
245 
  SIGNAL rg1_latch6_o_an1 : BIT;        -- rg1.latch6.o_an1
246 
  SIGNAL rg1_latch6_o_an2 : BIT;        -- rg1.latch6.o_an2
247 
  SIGNAL rg1_latch6_o_inv : BIT;        -- rg1.latch6.o_inv
248 
  SIGNAL rg1_latch6_o_nor2 : BIT;       -- rg1.latch6.o_nor2
249 
  SIGNAL o1_23 : BIT;   -- o1_23
250 
  SIGNAL rg1_latch7_o_an1 : BIT;        -- rg1.latch7.o_an1
251 
  SIGNAL rg1_latch7_o_an2 : BIT;        -- rg1.latch7.o_an2
252 
  SIGNAL rg1_latch7_o_inv : BIT;        -- rg1.latch7.o_inv
253 
  SIGNAL rg1_latch7_o_nor2 : BIT;       -- rg1.latch7.o_nor2
254 
  SIGNAL o1_24 : BIT;   -- o1_24
255 
  SIGNAL rg1_latch8_o_an1 : BIT;        -- rg1.latch8.o_an1
256 
  SIGNAL rg1_latch8_o_an2 : BIT;        -- rg1.latch8.o_an2
257 
  SIGNAL rg1_latch8_o_inv : BIT;        -- rg1.latch8.o_inv
258 
  SIGNAL rg1_latch8_o_nor2 : BIT;       -- rg1.latch8.o_nor2
259 
  SIGNAL o1_25 : BIT;   -- o1_25
260 
  SIGNAL rg1_latch9_o_an1 : BIT;        -- rg1.latch9.o_an1
261 
  SIGNAL rg1_latch9_o_an2 : BIT;        -- rg1.latch9.o_an2
262 
  SIGNAL rg1_latch9_o_inv : BIT;        -- rg1.latch9.o_inv
263 
  SIGNAL rg1_latch9_o_nor2 : BIT;       -- rg1.latch9.o_nor2
264 
  SIGNAL o1_26 : BIT;   -- o1_26
265 
  SIGNAL rg1_latch10_o_an1 : BIT;       -- rg1.latch10.o_an1
266 
  SIGNAL rg1_latch10_o_an2 : BIT;       -- rg1.latch10.o_an2
267 
  SIGNAL rg1_latch10_o_inv : BIT;       -- rg1.latch10.o_inv
268 
  SIGNAL rg1_latch10_o_nor2 : BIT;      -- rg1.latch10.o_nor2
269 
  SIGNAL o1_27 : BIT;   -- o1_27
270 
  SIGNAL rg1_latch11_o_an1 : BIT;       -- rg1.latch11.o_an1
271 
  SIGNAL rg1_latch11_o_an2 : BIT;       -- rg1.latch11.o_an2
272 
  SIGNAL rg1_latch11_o_inv : BIT;       -- rg1.latch11.o_inv
273 
  SIGNAL rg1_latch11_o_nor2 : BIT;      -- rg1.latch11.o_nor2
274 
  SIGNAL o1_28 : BIT;   -- o1_28
275 
  SIGNAL rg1_latch12_o_an1 : BIT;       -- rg1.latch12.o_an1
276 
  SIGNAL rg1_latch12_o_an2 : BIT;       -- rg1.latch12.o_an2
277 
  SIGNAL rg1_latch12_o_inv : BIT;       -- rg1.latch12.o_inv
278 
  SIGNAL rg1_latch12_o_nor2 : BIT;      -- rg1.latch12.o_nor2
279 
  SIGNAL o1_29 : BIT;   -- o1_29
280 
  SIGNAL rg1_latch13_o_an1 : BIT;       -- rg1.latch13.o_an1
281 
  SIGNAL rg1_latch13_o_an2 : BIT;       -- rg1.latch13.o_an2
282 
  SIGNAL rg1_latch13_o_inv : BIT;       -- rg1.latch13.o_inv
283 
  SIGNAL rg1_latch13_o_nor2 : BIT;      -- rg1.latch13.o_nor2
284 
  SIGNAL o1_30 : BIT;   -- o1_30
285 
  SIGNAL rg1_latch14_o_an1 : BIT;       -- rg1.latch14.o_an1
286 
  SIGNAL rg1_latch14_o_an2 : BIT;       -- rg1.latch14.o_an2
287 
  SIGNAL rg1_latch14_o_inv : BIT;       -- rg1.latch14.o_inv
288 
  SIGNAL rg1_latch14_o_nor2 : BIT;      -- rg1.latch14.o_nor2
289 
  SIGNAL o1_31 : BIT;   -- o1_31
290 
  SIGNAL rg1_latch15_o_an1 : BIT;       -- rg1.latch15.o_an1
291 
  SIGNAL rg1_latch15_o_an2 : BIT;       -- rg1.latch15.o_an2
292 
  SIGNAL rg1_latch15_o_inv : BIT;       -- rg1.latch15.o_inv
293 
  SIGNAL rg1_latch15_o_nor2 : BIT;      -- rg1.latch15.o_nor2
294 
  SIGNAL o1_0 : BIT;    -- o1_0
295 
  SIGNAL rg2_latch0_o_an1 : BIT;        -- rg2.latch0.o_an1
296 
  SIGNAL rg2_latch0_o_an2 : BIT;        -- rg2.latch0.o_an2
297 
  SIGNAL rg2_latch0_o_inv : BIT;        -- rg2.latch0.o_inv
298 
  SIGNAL rg2_latch0_o_nor2 : BIT;       -- rg2.latch0.o_nor2
299 
  SIGNAL o1_1 : BIT;    -- o1_1
300 
  SIGNAL rg2_latch1_o_an1 : BIT;        -- rg2.latch1.o_an1
301 
  SIGNAL rg2_latch1_o_an2 : BIT;        -- rg2.latch1.o_an2
302 
  SIGNAL rg2_latch1_o_inv : BIT;        -- rg2.latch1.o_inv
303 
  SIGNAL rg2_latch1_o_nor2 : BIT;       -- rg2.latch1.o_nor2
304 
  SIGNAL o1_2 : BIT;    -- o1_2
305 
  SIGNAL rg2_latch2_o_an1 : BIT;        -- rg2.latch2.o_an1
306 
  SIGNAL rg2_latch2_o_an2 : BIT;        -- rg2.latch2.o_an2
307 
  SIGNAL rg2_latch2_o_inv : BIT;        -- rg2.latch2.o_inv
308 
  SIGNAL rg2_latch2_o_nor2 : BIT;       -- rg2.latch2.o_nor2
309 
  SIGNAL o1_3 : BIT;    -- o1_3
310 
  SIGNAL rg2_latch3_o_an1 : BIT;        -- rg2.latch3.o_an1
311 
  SIGNAL rg2_latch3_o_an2 : BIT;        -- rg2.latch3.o_an2
312 
  SIGNAL rg2_latch3_o_inv : BIT;        -- rg2.latch3.o_inv
313 
  SIGNAL rg2_latch3_o_nor2 : BIT;       -- rg2.latch3.o_nor2
314 
  SIGNAL o1_4 : BIT;    -- o1_4
315 
  SIGNAL rg2_latch4_o_an1 : BIT;        -- rg2.latch4.o_an1
316 
  SIGNAL rg2_latch4_o_an2 : BIT;        -- rg2.latch4.o_an2
317 
  SIGNAL rg2_latch4_o_inv : BIT;        -- rg2.latch4.o_inv
318 
  SIGNAL rg2_latch4_o_nor2 : BIT;       -- rg2.latch4.o_nor2
319 
  SIGNAL o1_5 : BIT;    -- o1_5
320 
  SIGNAL rg2_latch5_o_an1 : BIT;        -- rg2.latch5.o_an1
321 
  SIGNAL rg2_latch5_o_an2 : BIT;        -- rg2.latch5.o_an2
322 
  SIGNAL rg2_latch5_o_inv : BIT;        -- rg2.latch5.o_inv
323 
  SIGNAL rg2_latch5_o_nor2 : BIT;       -- rg2.latch5.o_nor2
324 
  SIGNAL o1_6 : BIT;    -- o1_6
325 
  SIGNAL rg2_latch6_o_an1 : BIT;        -- rg2.latch6.o_an1
326 
  SIGNAL rg2_latch6_o_an2 : BIT;        -- rg2.latch6.o_an2
327 
  SIGNAL rg2_latch6_o_inv : BIT;        -- rg2.latch6.o_inv
328 
  SIGNAL rg2_latch6_o_nor2 : BIT;       -- rg2.latch6.o_nor2
329 
  SIGNAL o1_7 : BIT;    -- o1_7
330 
  SIGNAL rg2_latch7_o_an1 : BIT;        -- rg2.latch7.o_an1
331 
  SIGNAL rg2_latch7_o_an2 : BIT;        -- rg2.latch7.o_an2
332 
  SIGNAL rg2_latch7_o_inv : BIT;        -- rg2.latch7.o_inv
333 
  SIGNAL rg2_latch7_o_nor2 : BIT;       -- rg2.latch7.o_nor2
334 
  SIGNAL o1_8 : BIT;    -- o1_8
335 
  SIGNAL rg2_latch8_o_an1 : BIT;        -- rg2.latch8.o_an1
336 
  SIGNAL rg2_latch8_o_an2 : BIT;        -- rg2.latch8.o_an2
337 
  SIGNAL rg2_latch8_o_inv : BIT;        -- rg2.latch8.o_inv
338 
  SIGNAL rg2_latch8_o_nor2 : BIT;       -- rg2.latch8.o_nor2
339 
  SIGNAL o1_9 : BIT;    -- o1_9
340 
  SIGNAL rg2_latch9_o_an1 : BIT;        -- rg2.latch9.o_an1
341 
  SIGNAL rg2_latch9_o_an2 : BIT;        -- rg2.latch9.o_an2
342 
  SIGNAL rg2_latch9_o_inv : BIT;        -- rg2.latch9.o_inv
343 
  SIGNAL rg2_latch9_o_nor2 : BIT;       -- rg2.latch9.o_nor2
344 
  SIGNAL o1_10 : BIT;   -- o1_10
345 
  SIGNAL rg2_latch10_o_an1 : BIT;       -- rg2.latch10.o_an1
346 
  SIGNAL rg2_latch10_o_an2 : BIT;       -- rg2.latch10.o_an2
347 
  SIGNAL rg2_latch10_o_inv : BIT;       -- rg2.latch10.o_inv
348 
  SIGNAL rg2_latch10_o_nor2 : BIT;      -- rg2.latch10.o_nor2
349 
  SIGNAL o1_11 : BIT;   -- o1_11
350 
  SIGNAL rg2_latch11_o_an1 : BIT;       -- rg2.latch11.o_an1
351 
  SIGNAL rg2_latch11_o_an2 : BIT;       -- rg2.latch11.o_an2
352 
  SIGNAL rg2_latch11_o_inv : BIT;       -- rg2.latch11.o_inv
353 
  SIGNAL rg2_latch11_o_nor2 : BIT;      -- rg2.latch11.o_nor2
354 
  SIGNAL o1_12 : BIT;   -- o1_12
355 
  SIGNAL rg2_latch12_o_an1 : BIT;       -- rg2.latch12.o_an1
356 
  SIGNAL rg2_latch12_o_an2 : BIT;       -- rg2.latch12.o_an2
357 
  SIGNAL rg2_latch12_o_inv : BIT;       -- rg2.latch12.o_inv
358 
  SIGNAL rg2_latch12_o_nor2 : BIT;      -- rg2.latch12.o_nor2
359 
  SIGNAL o1_13 : BIT;   -- o1_13
360 
  SIGNAL rg2_latch13_o_an1 : BIT;       -- rg2.latch13.o_an1
361 
  SIGNAL rg2_latch13_o_an2 : BIT;       -- rg2.latch13.o_an2
362 
  SIGNAL rg2_latch13_o_inv : BIT;       -- rg2.latch13.o_inv
363 
  SIGNAL rg2_latch13_o_nor2 : BIT;      -- rg2.latch13.o_nor2
364 
  SIGNAL o1_14 : BIT;   -- o1_14
365 
  SIGNAL rg2_latch14_o_an1 : BIT;       -- rg2.latch14.o_an1
366 
  SIGNAL rg2_latch14_o_an2 : BIT;       -- rg2.latch14.o_an2
367 
  SIGNAL rg2_latch14_o_inv : BIT;       -- rg2.latch14.o_inv
368 
  SIGNAL rg2_latch14_o_nor2 : BIT;      -- rg2.latch14.o_nor2
369 
  SIGNAL o1_15 : BIT;   -- o1_15
370 
  SIGNAL rg2_latch15_o_an1 : BIT;       -- rg2.latch15.o_an1
371 
  SIGNAL rg2_latch15_o_an2 : BIT;       -- rg2.latch15.o_an2
372 
  SIGNAL rg2_latch15_o_inv : BIT;       -- rg2.latch15.o_inv
373 
  SIGNAL rg2_latch15_o_nor2 : BIT;      -- rg2.latch15.o_nor2
374 
  SIGNAL o2_16 : BIT;   -- o2_16
375 
  SIGNAL en_bufin : BIT;        -- en_bufin
376 
  SIGNAL rg3_latch0_o_an1 : BIT;        -- rg3.latch0.o_an1
377 
  SIGNAL rg3_latch0_o_an2 : BIT;        -- rg3.latch0.o_an2
378 
  SIGNAL rg3_latch0_o_inv : BIT;        -- rg3.latch0.o_inv
379 
  SIGNAL rg3_latch0_o_nor2 : BIT;       -- rg3.latch0.o_nor2
380 
  SIGNAL o2_17 : BIT;   -- o2_17
381 
  SIGNAL rg3_latch1_o_an1 : BIT;        -- rg3.latch1.o_an1
382 
  SIGNAL rg3_latch1_o_an2 : BIT;        -- rg3.latch1.o_an2
383 
  SIGNAL rg3_latch1_o_inv : BIT;        -- rg3.latch1.o_inv
384 
  SIGNAL rg3_latch1_o_nor2 : BIT;       -- rg3.latch1.o_nor2
385 
  SIGNAL o2_18 : BIT;   -- o2_18
386 
  SIGNAL rg3_latch2_o_an1 : BIT;        -- rg3.latch2.o_an1
387 
  SIGNAL rg3_latch2_o_an2 : BIT;        -- rg3.latch2.o_an2
388 
  SIGNAL rg3_latch2_o_inv : BIT;        -- rg3.latch2.o_inv
389 
  SIGNAL rg3_latch2_o_nor2 : BIT;       -- rg3.latch2.o_nor2
390 
  SIGNAL o2_19 : BIT;   -- o2_19
391 
  SIGNAL rg3_latch3_o_an1 : BIT;        -- rg3.latch3.o_an1
392 
  SIGNAL rg3_latch3_o_an2 : BIT;        -- rg3.latch3.o_an2
393 
  SIGNAL rg3_latch3_o_inv : BIT;        -- rg3.latch3.o_inv
394 
  SIGNAL rg3_latch3_o_nor2 : BIT;       -- rg3.latch3.o_nor2
395 
  SIGNAL o2_20 : BIT;   -- o2_20
396 
  SIGNAL rg3_latch4_o_an1 : BIT;        -- rg3.latch4.o_an1
397 
  SIGNAL rg3_latch4_o_an2 : BIT;        -- rg3.latch4.o_an2
398 
  SIGNAL rg3_latch4_o_inv : BIT;        -- rg3.latch4.o_inv
399 
  SIGNAL rg3_latch4_o_nor2 : BIT;       -- rg3.latch4.o_nor2
400 
  SIGNAL o2_21 : BIT;   -- o2_21
401 
  SIGNAL rg3_latch5_o_an1 : BIT;        -- rg3.latch5.o_an1
402 
  SIGNAL rg3_latch5_o_an2 : BIT;        -- rg3.latch5.o_an2
403 
  SIGNAL rg3_latch5_o_inv : BIT;        -- rg3.latch5.o_inv
404 
  SIGNAL rg3_latch5_o_nor2 : BIT;       -- rg3.latch5.o_nor2
405 
  SIGNAL o2_22 : BIT;   -- o2_22
406 
  SIGNAL rg3_latch6_o_an1 : BIT;        -- rg3.latch6.o_an1
407 
  SIGNAL rg3_latch6_o_an2 : BIT;        -- rg3.latch6.o_an2
408 
  SIGNAL rg3_latch6_o_inv : BIT;        -- rg3.latch6.o_inv
409 
  SIGNAL rg3_latch6_o_nor2 : BIT;       -- rg3.latch6.o_nor2
410 
  SIGNAL o2_23 : BIT;   -- o2_23
411 
  SIGNAL rg3_latch7_o_an1 : BIT;        -- rg3.latch7.o_an1
412 
  SIGNAL rg3_latch7_o_an2 : BIT;        -- rg3.latch7.o_an2
413 
  SIGNAL rg3_latch7_o_inv : BIT;        -- rg3.latch7.o_inv
414 
  SIGNAL rg3_latch7_o_nor2 : BIT;       -- rg3.latch7.o_nor2
415 
  SIGNAL o2_24 : BIT;   -- o2_24
416 
  SIGNAL rg3_latch8_o_an1 : BIT;        -- rg3.latch8.o_an1
417 
  SIGNAL rg3_latch8_o_an2 : BIT;        -- rg3.latch8.o_an2
418 
  SIGNAL rg3_latch8_o_inv : BIT;        -- rg3.latch8.o_inv
419 
  SIGNAL rg3_latch8_o_nor2 : BIT;       -- rg3.latch8.o_nor2
420 
  SIGNAL o2_25 : BIT;   -- o2_25
421 
  SIGNAL rg3_latch9_o_an1 : BIT;        -- rg3.latch9.o_an1
422 
  SIGNAL rg3_latch9_o_an2 : BIT;        -- rg3.latch9.o_an2
423 
  SIGNAL rg3_latch9_o_inv : BIT;        -- rg3.latch9.o_inv
424 
  SIGNAL rg3_latch9_o_nor2 : BIT;       -- rg3.latch9.o_nor2
425 
  SIGNAL o2_26 : BIT;   -- o2_26
426 
  SIGNAL rg3_latch10_o_an1 : BIT;       -- rg3.latch10.o_an1
427 
  SIGNAL rg3_latch10_o_an2 : BIT;       -- rg3.latch10.o_an2
428 
  SIGNAL rg3_latch10_o_inv : BIT;       -- rg3.latch10.o_inv
429 
  SIGNAL rg3_latch10_o_nor2 : BIT;      -- rg3.latch10.o_nor2
430 
  SIGNAL o2_27 : BIT;   -- o2_27
431 
  SIGNAL rg3_latch11_o_an1 : BIT;       -- rg3.latch11.o_an1
432 
  SIGNAL rg3_latch11_o_an2 : BIT;       -- rg3.latch11.o_an2
433 
  SIGNAL rg3_latch11_o_inv : BIT;       -- rg3.latch11.o_inv
434 
  SIGNAL rg3_latch11_o_nor2 : BIT;      -- rg3.latch11.o_nor2
435 
  SIGNAL o2_28 : BIT;   -- o2_28
436 
  SIGNAL rg3_latch12_o_an1 : BIT;       -- rg3.latch12.o_an1
437 
  SIGNAL rg3_latch12_o_an2 : BIT;       -- rg3.latch12.o_an2
438 
  SIGNAL rg3_latch12_o_inv : BIT;       -- rg3.latch12.o_inv
439 
  SIGNAL rg3_latch12_o_nor2 : BIT;      -- rg3.latch12.o_nor2
440 
  SIGNAL o2_29 : BIT;   -- o2_29
441 
  SIGNAL rg3_latch13_o_an1 : BIT;       -- rg3.latch13.o_an1
442 
  SIGNAL rg3_latch13_o_an2 : BIT;       -- rg3.latch13.o_an2
443 
  SIGNAL rg3_latch13_o_inv : BIT;       -- rg3.latch13.o_inv
444 
  SIGNAL rg3_latch13_o_nor2 : BIT;      -- rg3.latch13.o_nor2
445 
  SIGNAL o2_30 : BIT;   -- o2_30
446 
  SIGNAL rg3_latch14_o_an1 : BIT;       -- rg3.latch14.o_an1
447 
  SIGNAL rg3_latch14_o_an2 : BIT;       -- rg3.latch14.o_an2
448 
  SIGNAL rg3_latch14_o_inv : BIT;       -- rg3.latch14.o_inv
449 
  SIGNAL rg3_latch14_o_nor2 : BIT;      -- rg3.latch14.o_nor2
450 
  SIGNAL o2_31 : BIT;   -- o2_31
451 
  SIGNAL rg3_latch15_o_an1 : BIT;       -- rg3.latch15.o_an1
452 
  SIGNAL rg3_latch15_o_an2 : BIT;       -- rg3.latch15.o_an2
453 
  SIGNAL rg3_latch15_o_inv : BIT;       -- rg3.latch15.o_inv
454 
  SIGNAL rg3_latch15_o_nor2 : BIT;      -- rg3.latch15.o_nor2
455 
  SIGNAL o2_0 : BIT;    -- o2_0
456 
  SIGNAL rg4_latch0_o_an1 : BIT;        -- rg4.latch0.o_an1
457 
  SIGNAL rg4_latch0_o_an2 : BIT;        -- rg4.latch0.o_an2
458 
  SIGNAL rg4_latch0_o_inv : BIT;        -- rg4.latch0.o_inv
459 
  SIGNAL rg4_latch0_o_nor2 : BIT;       -- rg4.latch0.o_nor2
460 
  SIGNAL o2_1 : BIT;    -- o2_1
461 
  SIGNAL rg4_latch1_o_an1 : BIT;        -- rg4.latch1.o_an1
462 
  SIGNAL rg4_latch1_o_an2 : BIT;        -- rg4.latch1.o_an2
463 
  SIGNAL rg4_latch1_o_inv : BIT;        -- rg4.latch1.o_inv
464 
  SIGNAL rg4_latch1_o_nor2 : BIT;       -- rg4.latch1.o_nor2
465 
  SIGNAL o2_2 : BIT;    -- o2_2
466 
  SIGNAL rg4_latch2_o_an1 : BIT;        -- rg4.latch2.o_an1
467 
  SIGNAL rg4_latch2_o_an2 : BIT;        -- rg4.latch2.o_an2
468 
  SIGNAL rg4_latch2_o_inv : BIT;        -- rg4.latch2.o_inv
469 
  SIGNAL rg4_latch2_o_nor2 : BIT;       -- rg4.latch2.o_nor2
470 
  SIGNAL o2_3 : BIT;    -- o2_3
471 
  SIGNAL rg4_latch3_o_an1 : BIT;        -- rg4.latch3.o_an1
472 
  SIGNAL rg4_latch3_o_an2 : BIT;        -- rg4.latch3.o_an2
473 
  SIGNAL rg4_latch3_o_inv : BIT;        -- rg4.latch3.o_inv
474 
  SIGNAL rg4_latch3_o_nor2 : BIT;       -- rg4.latch3.o_nor2
475 
  SIGNAL o2_4 : BIT;    -- o2_4
476 
  SIGNAL rg4_latch4_o_an1 : BIT;        -- rg4.latch4.o_an1
477 
  SIGNAL rg4_latch4_o_an2 : BIT;        -- rg4.latch4.o_an2
478 
  SIGNAL rg4_latch4_o_inv : BIT;        -- rg4.latch4.o_inv
479 
  SIGNAL rg4_latch4_o_nor2 : BIT;       -- rg4.latch4.o_nor2
480 
  SIGNAL o2_5 : BIT;    -- o2_5
481 
  SIGNAL rg4_latch5_o_an1 : BIT;        -- rg4.latch5.o_an1
482 
  SIGNAL rg4_latch5_o_an2 : BIT;        -- rg4.latch5.o_an2
483 
  SIGNAL rg4_latch5_o_inv : BIT;        -- rg4.latch5.o_inv
484 
  SIGNAL rg4_latch5_o_nor2 : BIT;       -- rg4.latch5.o_nor2
485 
  SIGNAL o2_6 : BIT;    -- o2_6
486 
  SIGNAL rg4_latch6_o_an1 : BIT;        -- rg4.latch6.o_an1
487 
  SIGNAL rg4_latch6_o_an2 : BIT;        -- rg4.latch6.o_an2
488 
  SIGNAL rg4_latch6_o_inv : BIT;        -- rg4.latch6.o_inv
489 
  SIGNAL rg4_latch6_o_nor2 : BIT;       -- rg4.latch6.o_nor2
490 
  SIGNAL o2_7 : BIT;    -- o2_7
491 
  SIGNAL rg4_latch7_o_an1 : BIT;        -- rg4.latch7.o_an1
492 
  SIGNAL rg4_latch7_o_an2 : BIT;        -- rg4.latch7.o_an2
493 
  SIGNAL rg4_latch7_o_inv : BIT;        -- rg4.latch7.o_inv
494 
  SIGNAL rg4_latch7_o_nor2 : BIT;       -- rg4.latch7.o_nor2
495 
  SIGNAL o2_8 : BIT;    -- o2_8
496 
  SIGNAL rg4_latch8_o_an1 : BIT;        -- rg4.latch8.o_an1
497 
  SIGNAL rg4_latch8_o_an2 : BIT;        -- rg4.latch8.o_an2
498 
  SIGNAL rg4_latch8_o_inv : BIT;        -- rg4.latch8.o_inv
499 
  SIGNAL rg4_latch8_o_nor2 : BIT;       -- rg4.latch8.o_nor2
500 
  SIGNAL o2_9 : BIT;    -- o2_9
501 
  SIGNAL rg4_latch9_o_an1 : BIT;        -- rg4.latch9.o_an1
502 
  SIGNAL rg4_latch9_o_an2 : BIT;        -- rg4.latch9.o_an2
503 
  SIGNAL rg4_latch9_o_inv : BIT;        -- rg4.latch9.o_inv
504 
  SIGNAL rg4_latch9_o_nor2 : BIT;       -- rg4.latch9.o_nor2
505 
  SIGNAL o2_10 : BIT;   -- o2_10
506 
  SIGNAL rg4_latch10_o_an1 : BIT;       -- rg4.latch10.o_an1
507 
  SIGNAL rg4_latch10_o_an2 : BIT;       -- rg4.latch10.o_an2
508 
  SIGNAL rg4_latch10_o_inv : BIT;       -- rg4.latch10.o_inv
509 
  SIGNAL rg4_latch10_o_nor2 : BIT;      -- rg4.latch10.o_nor2
510 
  SIGNAL o2_11 : BIT;   -- o2_11
511 
  SIGNAL rg4_latch11_o_an1 : BIT;       -- rg4.latch11.o_an1
512 
  SIGNAL rg4_latch11_o_an2 : BIT;       -- rg4.latch11.o_an2
513 
  SIGNAL rg4_latch11_o_inv : BIT;       -- rg4.latch11.o_inv
514 
  SIGNAL rg4_latch11_o_nor2 : BIT;      -- rg4.latch11.o_nor2
515 
  SIGNAL o2_12 : BIT;   -- o2_12
516 
  SIGNAL rg4_latch12_o_an1 : BIT;       -- rg4.latch12.o_an1
517 
  SIGNAL rg4_latch12_o_an2 : BIT;       -- rg4.latch12.o_an2
518 
  SIGNAL rg4_latch12_o_inv : BIT;       -- rg4.latch12.o_inv
519 
  SIGNAL rg4_latch12_o_nor2 : BIT;      -- rg4.latch12.o_nor2
520 
  SIGNAL o2_13 : BIT;   -- o2_13
521 
  SIGNAL rg4_latch13_o_an1 : BIT;       -- rg4.latch13.o_an1
522 
  SIGNAL rg4_latch13_o_an2 : BIT;       -- rg4.latch13.o_an2
523 
  SIGNAL rg4_latch13_o_inv : BIT;       -- rg4.latch13.o_inv
524 
  SIGNAL rg4_latch13_o_nor2 : BIT;      -- rg4.latch13.o_nor2
525 
  SIGNAL o2_14 : BIT;   -- o2_14
526 
  SIGNAL rg4_latch14_o_an1 : BIT;       -- rg4.latch14.o_an1
527 
  SIGNAL rg4_latch14_o_an2 : BIT;       -- rg4.latch14.o_an2
528 
  SIGNAL rg4_latch14_o_inv : BIT;       -- rg4.latch14.o_inv
529 
  SIGNAL rg4_latch14_o_nor2 : BIT;      -- rg4.latch14.o_nor2
530 
  SIGNAL o2_15 : BIT;   -- o2_15
531 
  SIGNAL rg4_latch15_o_an1 : BIT;       -- rg4.latch15.o_an1
532 
  SIGNAL rg4_latch15_o_an2 : BIT;       -- rg4.latch15.o_an2
533 
  SIGNAL rg4_latch15_o_inv : BIT;       -- rg4.latch15.o_inv
534 
  SIGNAL rg4_latch15_o_nor2 : BIT;      -- rg4.latch15.o_nor2
535 
  SIGNAL n_block : BIT; -- n_block
536 
  SIGNAL dec12_auxsc1 : BIT;    -- dec12.auxsc1
537 
  SIGNAL ctrl_dtin_auxsc1 : BIT;        -- ctrl_dtin.auxsc1
538 
  SIGNAL ctrl_dtin_auxsc13 : BIT;       -- ctrl_dtin.auxsc13
539 
  SIGNAL ctrl_dtin_auxsc14 : BIT;       -- ctrl_dtin.auxsc14
540 
  SIGNAL ctrl_dtin_auxsc15 : BIT;       -- ctrl_dtin.auxsc15
541 
  SIGNAL ctrl_dtin_auxsc16 : BIT;       -- ctrl_dtin.auxsc16
542 
  SIGNAL ctrl_dtin_auxsc18 : BIT;       -- ctrl_dtin.auxsc18
543 
  SIGNAL ctrl_dtin_auxsc22 : BIT;       -- ctrl_dtin.auxsc22
544 
  SIGNAL ctrl_dtin_auxsc21 : BIT;       -- ctrl_dtin.auxsc21
545 
  SIGNAL ctrl_dtin_auxsc45 : BIT;       -- ctrl_dtin.auxsc45
546 
  SIGNAL ctrl_dtin_auxsc36 : BIT;       -- ctrl_dtin.auxsc36
547 
  SIGNAL ctrl_dtin_auxsc37 : BIT;       -- ctrl_dtin.auxsc37
548 
  SIGNAL ctrl_dtin_auxsc38 : BIT;       -- ctrl_dtin.auxsc38
549 
  SIGNAL ctrl_dtin_auxsc39 : BIT;       -- ctrl_dtin.auxsc39
550 
  SIGNAL ctrl_dtin_auxsc40 : BIT;       -- ctrl_dtin.auxsc40
551 
  SIGNAL ctrl_dtin_auxsc41 : BIT;       -- ctrl_dtin.auxsc41
552 
  SIGNAL ctrl_dtin_auxsc42 : BIT;       -- ctrl_dtin.auxsc42
553 
  SIGNAL ctrl_dtin_auxsc2 : BIT;        -- ctrl_dtin.auxsc2
554 
  SIGNAL ctrl_dtin_auxsc3 : BIT;        -- ctrl_dtin.auxsc3
555 
  SIGNAL ctrl_dtin_auxreg3 : BIT;       -- ctrl_dtin.auxreg3
556 
  SIGNAL ctrl_dtin_auxreg2 : BIT;       -- ctrl_dtin.auxreg2
557 
  SIGNAL ctrl_dtin_auxreg1 : BIT;       -- ctrl_dtin.auxreg1
558 
  SIGNAL o_inv : BIT;   -- o_inv
559 
 
560 
BEGIN
561 
 
562 
  rg1_latch0_inv : inv_x2
563 
    PORT MAP (
564 
    vss => vss,
565 
    vdd => vdd,
566 
    nq => rg1_latch0_o_inv,
567 
    i => o1_16);
568 
  rg1_latch0_an1 : a2_x2
569 
    PORT MAP (
570 
    vss => vss,
571 
    vdd => vdd,
572 
    q => rg1_latch0_o_an1,
573 
    i1 => en_bufin_c,
574 
    i0 => rg1_latch0_o_inv);
575 
  rg1_latch0_an2 : a2_x2
576 
    PORT MAP (
577 
    vss => vss,
578 
    vdd => vdd,
579 
    q => rg1_latch0_o_an2,
580 
    i1 => en_bufin_c,
581 
    i0 => o1_16);
582 
  rg1_latch0_nor1 : no3_x4
583 
    PORT MAP (
584 
    vss => vss,
585 
    vdd => vdd,
586 
    nq => data64in(48),
587 
    i2 => rg1_latch0_o_nor2,
588 
    i1 => netops1414,
589 
    i0 => rg1_latch0_o_an1);
590 
  rg1_latch0_nor2 : no2_x4
591 
    PORT MAP (
592 
    vss => vss,
593 
    vdd => vdd,
594 
    nq => rg1_latch0_o_nor2,
595 
    i1 => rg1_latch0_o_an2,
596 
    i0 => data64in(48));
597 
  rg1_latch1_inv : inv_x2
598 
    PORT MAP (
599 
    vss => vss,
600 
    vdd => vdd,
601 
    nq => rg1_latch1_o_inv,
602 
    i => o1_17);
603 
  rg1_latch1_an1 : a2_x2
604 
    PORT MAP (
605 
    vss => vss,
606 
    vdd => vdd,
607 
    q => rg1_latch1_o_an1,
608 
    i1 => en_bufin_c,
609 
    i0 => rg1_latch1_o_inv);
610 
  rg1_latch1_an2 : a2_x2
611 
    PORT MAP (
612 
    vss => vss,
613 
    vdd => vdd,
614 
    q => rg1_latch1_o_an2,
615 
    i1 => en_bufin_c,
616 
    i0 => o1_17);
617 
  rg1_latch1_nor1 : no3_x4
618 
    PORT MAP (
619 
    vss => vss,
620 
    vdd => vdd,
621 
    nq => data64in(49),
622 
    i2 => rg1_latch1_o_nor2,
623 
    i1 => netops1414,
624 
    i0 => rg1_latch1_o_an1);
625 
  rg1_latch1_nor2 : no2_x4
626 
    PORT MAP (
627 
    vss => vss,
628 
    vdd => vdd,
629 
    nq => rg1_latch1_o_nor2,
630 
    i1 => rg1_latch1_o_an2,
631 
    i0 => data64in(49));
632 
  rg1_latch2_inv : inv_x2
633 
    PORT MAP (
634 
    vss => vss,
635 
    vdd => vdd,
636 
    nq => rg1_latch2_o_inv,
637 
    i => o1_18);
638 
  rg1_latch2_an1 : a2_x2
639 
    PORT MAP (
640 
    vss => vss,
641 
    vdd => vdd,
642 
    q => rg1_latch2_o_an1,
643 
    i1 => en_bufin_c,
644 
    i0 => rg1_latch2_o_inv);
645 
  rg1_latch2_an2 : a2_x2
646 
    PORT MAP (
647 
    vss => vss,
648 
    vdd => vdd,
649 
    q => rg1_latch2_o_an2,
650 
    i1 => en_bufin_c,
651 
    i0 => o1_18);
652 
  rg1_latch2_nor1 : no3_x4
653 
    PORT MAP (
654 
    vss => vss,
655 
    vdd => vdd,
656 
    nq => data64in(50),
657 
    i2 => rg1_latch2_o_nor2,
658 
    i1 => netops1414,
659 
    i0 => rg1_latch2_o_an1);
660 
  rg1_latch2_nor2 : no2_x4
661 
    PORT MAP (
662 
    vss => vss,
663 
    vdd => vdd,
664 
    nq => rg1_latch2_o_nor2,
665 
    i1 => rg1_latch2_o_an2,
666 
    i0 => data64in(50));
667 
  rg1_latch3_inv : inv_x2
668 
    PORT MAP (
669 
    vss => vss,
670 
    vdd => vdd,
671 
    nq => rg1_latch3_o_inv,
672 
    i => o1_19);
673 
  rg1_latch3_an1 : a2_x2
674 
    PORT MAP (
675 
    vss => vss,
676 
    vdd => vdd,
677 
    q => rg1_latch3_o_an1,
678 
    i1 => en_bufin_c,
679 
    i0 => rg1_latch3_o_inv);
680 
  rg1_latch3_an2 : a2_x2
681 
    PORT MAP (
682 
    vss => vss,
683 
    vdd => vdd,
684 
    q => rg1_latch3_o_an2,
685 
    i1 => en_bufin_c,
686 
    i0 => o1_19);
687 
  rg1_latch3_nor1 : no3_x4
688 
    PORT MAP (
689 
    vss => vss,
690 
    vdd => vdd,
691 
    nq => data64in(51),
692 
    i2 => rg1_latch3_o_nor2,
693 
    i1 => netops1414,
694 
    i0 => rg1_latch3_o_an1);
695 
  rg1_latch3_nor2 : no2_x4
696 
    PORT MAP (
697 
    vss => vss,
698 
    vdd => vdd,
699 
    nq => rg1_latch3_o_nor2,
700 
    i1 => rg1_latch3_o_an2,
701 
    i0 => data64in(51));
702 
  rg1_latch4_inv : inv_x2
703 
    PORT MAP (
704 
    vss => vss,
705 
    vdd => vdd,
706 
    nq => rg1_latch4_o_inv,
707 
    i => o1_20);
708 
  rg1_latch4_an1 : a2_x2
709 
    PORT MAP (
710 
    vss => vss,
711 
    vdd => vdd,
712 
    q => rg1_latch4_o_an1,
713 
    i1 => en_bufin_c,
714 
    i0 => rg1_latch4_o_inv);
715 
  rg1_latch4_an2 : a2_x2
716 
    PORT MAP (
717 
    vss => vss,
718 
    vdd => vdd,
719 
    q => rg1_latch4_o_an2,
720 
    i1 => en_bufin_c,
721 
    i0 => o1_20);
722 
  rg1_latch4_nor1 : no3_x4
723 
    PORT MAP (
724 
    vss => vss,
725 
    vdd => vdd,
726 
    nq => data64in(52),
727 
    i2 => rg1_latch4_o_nor2,
728 
    i1 => netops1414,
729 
    i0 => rg1_latch4_o_an1);
730 
  rg1_latch4_nor2 : no2_x4
731 
    PORT MAP (
732 
    vss => vss,
733 
    vdd => vdd,
734 
    nq => rg1_latch4_o_nor2,
735 
    i1 => rg1_latch4_o_an2,
736 
    i0 => data64in(52));
737 
  rg1_latch5_inv : inv_x2
738 
    PORT MAP (
739 
    vss => vss,
740 
    vdd => vdd,
741 
    nq => rg1_latch5_o_inv,
742 
    i => o1_21);
743 
  rg1_latch5_an1 : a2_x2
744 
    PORT MAP (
745 
    vss => vss,
746 
    vdd => vdd,
747 
    q => rg1_latch5_o_an1,
748 
    i1 => en_bufin_c,
749 
    i0 => rg1_latch5_o_inv);
750 
  rg1_latch5_an2 : a2_x2
751 
    PORT MAP (
752 
    vss => vss,
753 
    vdd => vdd,
754 
    q => rg1_latch5_o_an2,
755 
    i1 => en_bufin_c,
756 
    i0 => o1_21);
757 
  rg1_latch5_nor1 : no3_x4
758 
    PORT MAP (
759 
    vss => vss,
760 
    vdd => vdd,
761 
    nq => data64in(53),
762 
    i2 => rg1_latch5_o_nor2,
763 
    i1 => netops1414,
764 
    i0 => rg1_latch5_o_an1);
765 
  rg1_latch5_nor2 : no2_x4
766 
    PORT MAP (
767 
    vss => vss,
768 
    vdd => vdd,
769 
    nq => rg1_latch5_o_nor2,
770 
    i1 => rg1_latch5_o_an2,
771 
    i0 => data64in(53));
772 
  rg1_latch6_inv : inv_x2
773 
    PORT MAP (
774 
    vss => vss,
775 
    vdd => vdd,
776 
    nq => rg1_latch6_o_inv,
777 
    i => o1_22);
778 
  rg1_latch6_an1 : a2_x2
779 
    PORT MAP (
780 
    vss => vss,
781 
    vdd => vdd,
782 
    q => rg1_latch6_o_an1,
783 
    i1 => en_bufin_c,
784 
    i0 => rg1_latch6_o_inv);
785 
  rg1_latch6_an2 : a2_x2
786 
    PORT MAP (
787 
    vss => vss,
788 
    vdd => vdd,
789 
    q => rg1_latch6_o_an2,
790 
    i1 => en_bufin_c,
791 
    i0 => o1_22);
792 
  rg1_latch6_nor1 : no3_x4
793 
    PORT MAP (
794 
    vss => vss,
795 
    vdd => vdd,
796 
    nq => data64in(54),
797 
    i2 => rg1_latch6_o_nor2,
798 
    i1 => netops1414,
799 
    i0 => rg1_latch6_o_an1);
800 
  rg1_latch6_nor2 : no2_x4
801 
    PORT MAP (
802 
    vss => vss,
803 
    vdd => vdd,
804 
    nq => rg1_latch6_o_nor2,
805 
    i1 => rg1_latch6_o_an2,
806 
    i0 => data64in(54));
807 
  rg1_latch7_inv : inv_x2
808 
    PORT MAP (
809 
    vss => vss,
810 
    vdd => vdd,
811 
    nq => rg1_latch7_o_inv,
812 
    i => o1_23);
813 
  rg1_latch7_an1 : a2_x2
814 
    PORT MAP (
815 
    vss => vss,
816 
    vdd => vdd,
817 
    q => rg1_latch7_o_an1,
818 
    i1 => en_bufin_c,
819 
    i0 => rg1_latch7_o_inv);
820 
  rg1_latch7_an2 : a2_x2
821 
    PORT MAP (
822 
    vss => vss,
823 
    vdd => vdd,
824 
    q => rg1_latch7_o_an2,
825 
    i1 => en_bufin_c,
826 
    i0 => o1_23);
827 
  rg1_latch7_nor1 : no3_x4
828 
    PORT MAP (
829 
    vss => vss,
830 
    vdd => vdd,
831 
    nq => data64in(55),
832 
    i2 => rg1_latch7_o_nor2,
833 
    i1 => netops1414,
834 
    i0 => rg1_latch7_o_an1);
835 
  rg1_latch7_nor2 : no2_x4
836 
    PORT MAP (
837 
    vss => vss,
838 
    vdd => vdd,
839 
    nq => rg1_latch7_o_nor2,
840 
    i1 => rg1_latch7_o_an2,
841 
    i0 => data64in(55));
842 
  rg1_latch8_inv : inv_x2
843 
    PORT MAP (
844 
    vss => vss,
845 
    vdd => vdd,
846 
    nq => rg1_latch8_o_inv,
847 
    i => o1_24);
848 
  rg1_latch8_an1 : a2_x2
849 
    PORT MAP (
850 
    vss => vss,
851 
    vdd => vdd,
852 
    q => rg1_latch8_o_an1,
853 
    i1 => en_bufin_c,
854 
    i0 => rg1_latch8_o_inv);
855 
  rg1_latch8_an2 : a2_x2
856 
    PORT MAP (
857 
    vss => vss,
858 
    vdd => vdd,
859 
    q => rg1_latch8_o_an2,
860 
    i1 => en_bufin_c,
861 
    i0 => o1_24);
862 
  rg1_latch8_nor1 : no3_x4
863 
    PORT MAP (
864 
    vss => vss,
865 
    vdd => vdd,
866 
    nq => data64in(56),
867 
    i2 => rg1_latch8_o_nor2,
868 
    i1 => netops1414,
869 
    i0 => rg1_latch8_o_an1);
870 
  rg1_latch8_nor2 : no2_x4
871 
    PORT MAP (
872 
    vss => vss,
873 
    vdd => vdd,
874 
    nq => rg1_latch8_o_nor2,
875 
    i1 => rg1_latch8_o_an2,
876 
    i0 => data64in(56));
877 
  rg1_latch9_inv : inv_x2
878 
    PORT MAP (
879 
    vss => vss,
880 
    vdd => vdd,
881 
    nq => rg1_latch9_o_inv,
882 
    i => o1_25);
883 
  rg1_latch9_an1 : a2_x2
884 
    PORT MAP (
885 
    vss => vss,
886 
    vdd => vdd,
887 
    q => rg1_latch9_o_an1,
888 
    i1 => en_bufin_c,
889 
    i0 => rg1_latch9_o_inv);
890 
  rg1_latch9_an2 : a2_x2
891 
    PORT MAP (
892 
    vss => vss,
893 
    vdd => vdd,
894 
    q => rg1_latch9_o_an2,
895 
    i1 => en_bufin_c,
896 
    i0 => o1_25);
897 
  rg1_latch9_nor1 : no3_x4
898 
    PORT MAP (
899 
    vss => vss,
900 
    vdd => vdd,
901 
    nq => data64in(57),
902 
    i2 => rg1_latch9_o_nor2,
903 
    i1 => netops1414,
904 
    i0 => rg1_latch9_o_an1);
905 
  rg1_latch9_nor2 : no2_x4
906 
    PORT MAP (
907 
    vss => vss,
908 
    vdd => vdd,
909 
    nq => rg1_latch9_o_nor2,
910 
    i1 => rg1_latch9_o_an2,
911 
    i0 => data64in(57));
912 
  rg1_latch10_inv : inv_x2
913 
    PORT MAP (
914 
    vss => vss,
915 
    vdd => vdd,
916 
    nq => rg1_latch10_o_inv,
917 
    i => o1_26);
918 
  rg1_latch10_an1 : a2_x2
919 
    PORT MAP (
920 
    vss => vss,
921 
    vdd => vdd,
922 
    q => rg1_latch10_o_an1,
923 
    i1 => en_bufin_c,
924 
    i0 => rg1_latch10_o_inv);
925 
  rg1_latch10_an2 : a2_x2
926 
    PORT MAP (
927 
    vss => vss,
928 
    vdd => vdd,
929 
    q => rg1_latch10_o_an2,
930 
    i1 => en_bufin_c,
931 
    i0 => o1_26);
932 
  rg1_latch10_nor1 : no3_x4
933 
    PORT MAP (
934 
    vss => vss,
935 
    vdd => vdd,
936 
    nq => data64in(58),
937 
    i2 => rg1_latch10_o_nor2,
938 
    i1 => netops1414,
939 
    i0 => rg1_latch10_o_an1);
940 
  rg1_latch10_nor2 : no2_x4
941 
    PORT MAP (
942 
    vss => vss,
943 
    vdd => vdd,
944 
    nq => rg1_latch10_o_nor2,
945 
    i1 => rg1_latch10_o_an2,
946 
    i0 => data64in(58));
947 
  rg1_latch11_inv : inv_x2
948 
    PORT MAP (
949 
    vss => vss,
950 
    vdd => vdd,
951 
    nq => rg1_latch11_o_inv,
952 
    i => o1_27);
953 
  rg1_latch11_an1 : a2_x2
954 
    PORT MAP (
955 
    vss => vss,
956 
    vdd => vdd,
957 
    q => rg1_latch11_o_an1,
958 
    i1 => en_bufin_c,
959 
    i0 => rg1_latch11_o_inv);
960 
  rg1_latch11_an2 : a2_x2
961 
    PORT MAP (
962 
    vss => vss,
963 
    vdd => vdd,
964 
    q => rg1_latch11_o_an2,
965 
    i1 => en_bufin_c,
966 
    i0 => o1_27);
967 
  rg1_latch11_nor1 : no3_x4
968 
    PORT MAP (
969 
    vss => vss,
970 
    vdd => vdd,
971 
    nq => data64in(59),
972 
    i2 => rg1_latch11_o_nor2,
973 
    i1 => netops1414,
974 
    i0 => rg1_latch11_o_an1);
975 
  rg1_latch11_nor2 : no2_x4
976 
    PORT MAP (
977 
    vss => vss,
978 
    vdd => vdd,
979 
    nq => rg1_latch11_o_nor2,
980 
    i1 => rg1_latch11_o_an2,
981 
    i0 => data64in(59));
982 
  rg1_latch12_inv : inv_x2
983 
    PORT MAP (
984 
    vss => vss,
985 
    vdd => vdd,
986 
    nq => rg1_latch12_o_inv,
987 
    i => o1_28);
988 
  rg1_latch12_an1 : a2_x2
989 
    PORT MAP (
990 
    vss => vss,
991 
    vdd => vdd,
992 
    q => rg1_latch12_o_an1,
993 
    i1 => en_bufin_c,
994 
    i0 => rg1_latch12_o_inv);
995 
  rg1_latch12_an2 : a2_x2
996 
    PORT MAP (
997 
    vss => vss,
998 
    vdd => vdd,
999 
    q => rg1_latch12_o_an2,
1000 
    i1 => en_bufin_c,
1001 
    i0 => o1_28);
1002 
  rg1_latch12_nor1 : no3_x4
1003 
    PORT MAP (
1004 
    vss => vss,
1005 
    vdd => vdd,
1006 
    nq => data64in(60),
1007 
    i2 => rg1_latch12_o_nor2,
1008 
    i1 => netops1414,
1009 
    i0 => rg1_latch12_o_an1);
1010 
  rg1_latch12_nor2 : no2_x4
1011 
    PORT MAP (
1012 
    vss => vss,
1013 
    vdd => vdd,
1014 
    nq => rg1_latch12_o_nor2,
1015 
    i1 => rg1_latch12_o_an2,
1016 
    i0 => data64in(60));
1017 
  rg1_latch13_inv : inv_x2
1018 
    PORT MAP (
1019 
    vss => vss,
1020 
    vdd => vdd,
1021 
    nq => rg1_latch13_o_inv,
1022 
    i => o1_29);
1023 
  rg1_latch13_an1 : a2_x2
1024 
    PORT MAP (
1025 
    vss => vss,
1026 
    vdd => vdd,
1027 
    q => rg1_latch13_o_an1,
1028 
    i1 => en_bufin_c,
1029 
    i0 => rg1_latch13_o_inv);
1030 
  rg1_latch13_an2 : a2_x2
1031 
    PORT MAP (
1032 
    vss => vss,
1033 
    vdd => vdd,
1034 
    q => rg1_latch13_o_an2,
1035 
    i1 => en_bufin_c,
1036 
    i0 => o1_29);
1037 
  rg1_latch13_nor1 : no3_x4
1038 
    PORT MAP (
1039 
    vss => vss,
1040 
    vdd => vdd,
1041 
    nq => data64in(61),
1042 
    i2 => rg1_latch13_o_nor2,
1043 
    i1 => netops1414,
1044 
    i0 => rg1_latch13_o_an1);
1045 
  rg1_latch13_nor2 : no2_x4
1046 
    PORT MAP (
1047 
    vss => vss,
1048 
    vdd => vdd,
1049 
    nq => rg1_latch13_o_nor2,
1050 
    i1 => rg1_latch13_o_an2,
1051 
    i0 => data64in(61));
1052 
  rg1_latch14_inv : inv_x2
1053 
    PORT MAP (
1054 
    vss => vss,
1055 
    vdd => vdd,
1056 
    nq => rg1_latch14_o_inv,
1057 
    i => o1_30);
1058 
  rg1_latch14_an1 : a2_x2
1059 
    PORT MAP (
1060 
    vss => vss,
1061 
    vdd => vdd,
1062 
    q => rg1_latch14_o_an1,
1063 
    i1 => en_bufin_c,
1064 
    i0 => rg1_latch14_o_inv);
1065 
  rg1_latch14_an2 : a2_x2
1066 
    PORT MAP (
1067 
    vss => vss,
1068 
    vdd => vdd,
1069 
    q => rg1_latch14_o_an2,
1070 
    i1 => en_bufin_c,
1071 
    i0 => o1_30);
1072 
  rg1_latch14_nor1 : no3_x4
1073 
    PORT MAP (
1074 
    vss => vss,
1075 
    vdd => vdd,
1076 
    nq => data64in(62),
1077 
    i2 => rg1_latch14_o_nor2,
1078 
    i1 => netops1414,
1079 
    i0 => rg1_latch14_o_an1);
1080 
  rg1_latch14_nor2 : no2_x4
1081 
    PORT MAP (
1082 
    vss => vss,
1083 
    vdd => vdd,
1084 
    nq => rg1_latch14_o_nor2,
1085 
    i1 => rg1_latch14_o_an2,
1086 
    i0 => data64in(62));
1087 
  rg1_latch15_inv : inv_x2
1088 
    PORT MAP (
1089 
    vss => vss,
1090 
    vdd => vdd,
1091 
    nq => rg1_latch15_o_inv,
1092 
    i => o1_31);
1093 
  rg1_latch15_an1 : a2_x2
1094 
    PORT MAP (
1095 
    vss => vss,
1096 
    vdd => vdd,
1097 
    q => rg1_latch15_o_an1,
1098 
    i1 => en_bufin_c,
1099 
    i0 => rg1_latch15_o_inv);
1100 
  rg1_latch15_an2 : a2_x2
1101 
    PORT MAP (
1102 
    vss => vss,
1103 
    vdd => vdd,
1104 
    q => rg1_latch15_o_an2,
1105 
    i1 => en_bufin_c,
1106 
    i0 => o1_31);
1107 
  rg1_latch15_nor1 : no3_x4
1108 
    PORT MAP (
1109 
    vss => vss,
1110 
    vdd => vdd,
1111 
    nq => data64in(63),
1112 
    i2 => rg1_latch15_o_nor2,
1113 
    i1 => netops1414,
1114 
    i0 => rg1_latch15_o_an1);
1115 
  rg1_latch15_nor2 : no2_x4
1116 
    PORT MAP (
1117 
    vss => vss,
1118 
    vdd => vdd,
1119 
    nq => rg1_latch15_o_nor2,
1120 
    i1 => rg1_latch15_o_an2,
1121 
    i0 => data64in(63));
1122 
  rg2_latch0_inv : inv_x2
1123 
    PORT MAP (
1124 
    vss => vss,
1125 
    vdd => vdd,
1126 
    nq => rg2_latch0_o_inv,
1127 
    i => o1_0);
1128 
  rg2_latch0_an1 : a2_x2
1129 
    PORT MAP (
1130 
    vss => vss,
1131 
    vdd => vdd,
1132 
    q => rg2_latch0_o_an1,
1133 
    i1 => en_bufin_c,
1134 
    i0 => rg2_latch0_o_inv);
1135 
  rg2_latch0_an2 : a2_x2
1136 
    PORT MAP (
1137 
    vss => vss,
1138 
    vdd => vdd,
1139 
    q => rg2_latch0_o_an2,
1140 
    i1 => en_bufin_c,
1141 
    i0 => o1_0);
1142 
  rg2_latch0_nor1 : no3_x4
1143 
    PORT MAP (
1144 
    vss => vss,
1145 
    vdd => vdd,
1146 
    nq => data64in(32),
1147 
    i2 => rg2_latch0_o_nor2,
1148 
    i1 => netops1414,
1149 
    i0 => rg2_latch0_o_an1);
1150 
  rg2_latch0_nor2 : no2_x4
1151 
    PORT MAP (
1152 
    vss => vss,
1153 
    vdd => vdd,
1154 
    nq => rg2_latch0_o_nor2,
1155 
    i1 => rg2_latch0_o_an2,
1156 
    i0 => data64in(32));
1157 
  rg2_latch1_inv : inv_x2
1158 
    PORT MAP (
1159 
    vss => vss,
1160 
    vdd => vdd,
1161 
    nq => rg2_latch1_o_inv,
1162 
    i => o1_1);
1163 
  rg2_latch1_an1 : a2_x2
1164 
    PORT MAP (
1165 
    vss => vss,
1166 
    vdd => vdd,
1167 
    q => rg2_latch1_o_an1,
1168 
    i1 => en_bufin_c,
1169 
    i0 => rg2_latch1_o_inv);
1170 
  rg2_latch1_an2 : a2_x2
1171 
    PORT MAP (
1172 
    vss => vss,
1173 
    vdd => vdd,
1174 
    q => rg2_latch1_o_an2,
1175 
    i1 => en_bufin_c,
1176 
    i0 => o1_1);
1177 
  rg2_latch1_nor1 : no3_x4
1178 
    PORT MAP (
1179 
    vss => vss,
1180 
    vdd => vdd,
1181 
    nq => data64in(33),
1182 
    i2 => rg2_latch1_o_nor2,
1183 
    i1 => netops1414,
1184 
    i0 => rg2_latch1_o_an1);
1185 
  rg2_latch1_nor2 : no2_x4
1186 
    PORT MAP (
1187 
    vss => vss,
1188 
    vdd => vdd,
1189 
    nq => rg2_latch1_o_nor2,
1190 
    i1 => rg2_latch1_o_an2,
1191 
    i0 => data64in(33));
1192 
  rg2_latch2_inv : inv_x2
1193 
    PORT MAP (
1194 
    vss => vss,
1195 
    vdd => vdd,
1196 
    nq => rg2_latch2_o_inv,
1197 
    i => o1_2);
1198 
  rg2_latch2_an1 : a2_x2
1199 
    PORT MAP (
1200 
    vss => vss,
1201 
    vdd => vdd,
1202 
    q => rg2_latch2_o_an1,
1203 
    i1 => en_bufin_c,
1204 
    i0 => rg2_latch2_o_inv);
1205 
  rg2_latch2_an2 : a2_x2
1206 
    PORT MAP (
1207 
    vss => vss,
1208 
    vdd => vdd,
1209 
    q => rg2_latch2_o_an2,
1210 
    i1 => en_bufin_c,
1211 
    i0 => o1_2);
1212 
  rg2_latch2_nor1 : no3_x4
1213 
    PORT MAP (
1214 
    vss => vss,
1215 
    vdd => vdd,
1216 
    nq => data64in(34),
1217 
    i2 => rg2_latch2_o_nor2,
1218 
    i1 => netops1414,
1219 
    i0 => rg2_latch2_o_an1);
1220 
  rg2_latch2_nor2 : no2_x4
1221 
    PORT MAP (
1222 
    vss => vss,
1223 
    vdd => vdd,
1224 
    nq => rg2_latch2_o_nor2,
1225 
    i1 => rg2_latch2_o_an2,
1226 
    i0 => data64in(34));
1227 
  rg2_latch3_inv : inv_x2
1228 
    PORT MAP (
1229 
    vss => vss,
1230 
    vdd => vdd,
1231 
    nq => rg2_latch3_o_inv,
1232 
    i => o1_3);
1233 
  rg2_latch3_an1 : a2_x2
1234 
    PORT MAP (
1235 
    vss => vss,
1236 
    vdd => vdd,
1237 
    q => rg2_latch3_o_an1,
1238 
    i1 => en_bufin_c,
1239 
    i0 => rg2_latch3_o_inv);
1240 
  rg2_latch3_an2 : a2_x2
1241 
    PORT MAP (
1242 
    vss => vss,
1243 
    vdd => vdd,
1244 
    q => rg2_latch3_o_an2,
1245 
    i1 => en_bufin_c,
1246 
    i0 => o1_3);
1247 
  rg2_latch3_nor1 : no3_x4
1248 
    PORT MAP (
1249 
    vss => vss,
1250 
    vdd => vdd,
1251 
    nq => data64in(35),
1252 
    i2 => rg2_latch3_o_nor2,
1253 
    i1 => netops1414,
1254 
    i0 => rg2_latch3_o_an1);
1255 
  rg2_latch3_nor2 : no2_x4
1256 
    PORT MAP (
1257 
    vss => vss,
1258 
    vdd => vdd,
1259 
    nq => rg2_latch3_o_nor2,
1260 
    i1 => rg2_latch3_o_an2,
1261 
    i0 => data64in(35));
1262 
  rg2_latch4_inv : inv_x2
1263 
    PORT MAP (
1264 
    vss => vss,
1265 
    vdd => vdd,
1266 
    nq => rg2_latch4_o_inv,
1267 
    i => o1_4);
1268 
  rg2_latch4_an1 : a2_x2
1269 
    PORT MAP (
1270 
    vss => vss,
1271 
    vdd => vdd,
1272 
    q => rg2_latch4_o_an1,
1273 
    i1 => en_bufin_c,
1274 
    i0 => rg2_latch4_o_inv);
1275 
  rg2_latch4_an2 : a2_x2
1276 
    PORT MAP (
1277 
    vss => vss,
1278 
    vdd => vdd,
1279 
    q => rg2_latch4_o_an2,
1280 
    i1 => en_bufin_c,
1281 
    i0 => o1_4);
1282 
  rg2_latch4_nor1 : no3_x4
1283 
    PORT MAP (
1284 
    vss => vss,
1285 
    vdd => vdd,
1286 
    nq => data64in(36),
1287 
    i2 => rg2_latch4_o_nor2,
1288 
    i1 => netops1414,
1289 
    i0 => rg2_latch4_o_an1);
1290 
  rg2_latch4_nor2 : no2_x4
1291 
    PORT MAP (
1292 
    vss => vss,
1293 
    vdd => vdd,
1294 
    nq => rg2_latch4_o_nor2,
1295 
    i1 => rg2_latch4_o_an2,
1296 
    i0 => data64in(36));
1297 
  rg2_latch5_inv : inv_x2
1298 
    PORT MAP (
1299 
    vss => vss,
1300 
    vdd => vdd,
1301 
    nq => rg2_latch5_o_inv,
1302 
    i => o1_5);
1303 
  rg2_latch5_an1 : a2_x2
1304 
    PORT MAP (
1305 
    vss => vss,
1306 
    vdd => vdd,
1307 
    q => rg2_latch5_o_an1,
1308 
    i1 => en_bufin_c,
1309 
    i0 => rg2_latch5_o_inv);
1310 
  rg2_latch5_an2 : a2_x2
1311 
    PORT MAP (
1312 
    vss => vss,
1313 
    vdd => vdd,
1314 
    q => rg2_latch5_o_an2,
1315 
    i1 => en_bufin_c,
1316 
    i0 => o1_5);
1317 
  rg2_latch5_nor1 : no3_x4
1318 
    PORT MAP (
1319 
    vss => vss,
1320 
    vdd => vdd,
1321 
    nq => data64in(37),
1322 
    i2 => rg2_latch5_o_nor2,
1323 
    i1 => netops1414,
1324 
    i0 => rg2_latch5_o_an1);
1325 
  rg2_latch5_nor2 : no2_x4
1326 
    PORT MAP (
1327 
    vss => vss,
1328 
    vdd => vdd,
1329 
    nq => rg2_latch5_o_nor2,
1330 
    i1 => rg2_latch5_o_an2,
1331 
    i0 => data64in(37));
1332 
  rg2_latch6_inv : inv_x2
1333 
    PORT MAP (
1334 
    vss => vss,
1335 
    vdd => vdd,
1336 
    nq => rg2_latch6_o_inv,
1337 
    i => o1_6);
1338 
  rg2_latch6_an1 : a2_x2
1339 
    PORT MAP (
1340 
    vss => vss,
1341 
    vdd => vdd,
1342 
    q => rg2_latch6_o_an1,
1343 
    i1 => en_bufin_c,
1344 
    i0 => rg2_latch6_o_inv);
1345 
  rg2_latch6_an2 : a2_x2
1346 
    PORT MAP (
1347 
    vss => vss,
1348 
    vdd => vdd,
1349 
    q => rg2_latch6_o_an2,
1350 
    i1 => en_bufin_c,
1351 
    i0 => o1_6);
1352 
  rg2_latch6_nor1 : no3_x4
1353 
    PORT MAP (
1354 
    vss => vss,
1355 
    vdd => vdd,
1356 
    nq => data64in(38),
1357 
    i2 => rg2_latch6_o_nor2,
1358 
    i1 => netops1414,
1359 
    i0 => rg2_latch6_o_an1);
1360 
  rg2_latch6_nor2 : no2_x4
1361 
    PORT MAP (
1362 
    vss => vss,
1363 
    vdd => vdd,
1364 
    nq => rg2_latch6_o_nor2,
1365 
    i1 => rg2_latch6_o_an2,
1366 
    i0 => data64in(38));
1367 
  rg2_latch7_inv : inv_x2
1368 
    PORT MAP (
1369 
    vss => vss,
1370 
    vdd => vdd,
1371 
    nq => rg2_latch7_o_inv,
1372 
    i => o1_7);
1373 
  rg2_latch7_an1 : a2_x2
1374 
    PORT MAP (
1375 
    vss => vss,
1376 
    vdd => vdd,
1377 
    q => rg2_latch7_o_an1,
1378 
    i1 => en_bufin_c,
1379 
    i0 => rg2_latch7_o_inv);
1380 
  rg2_latch7_an2 : a2_x2
1381 
    PORT MAP (
1382 
    vss => vss,
1383 
    vdd => vdd,
1384 
    q => rg2_latch7_o_an2,
1385 
    i1 => en_bufin_c,
1386 
    i0 => o1_7);
1387 
  rg2_latch7_nor1 : no3_x4
1388 
    PORT MAP (
1389 
    vss => vss,
1390 
    vdd => vdd,
1391 
    nq => data64in(39),
1392 
    i2 => rg2_latch7_o_nor2,
1393 
    i1 => netops1414,
1394 
    i0 => rg2_latch7_o_an1);
1395 
  rg2_latch7_nor2 : no2_x4
1396 
    PORT MAP (
1397 
    vss => vss,
1398 
    vdd => vdd,
1399 
    nq => rg2_latch7_o_nor2,
1400 
    i1 => rg2_latch7_o_an2,
1401 
    i0 => data64in(39));
1402 
  rg2_latch8_inv : inv_x2
1403 
    PORT MAP (
1404 
    vss => vss,
1405 
    vdd => vdd,
1406 
    nq => rg2_latch8_o_inv,
1407 
    i => o1_8);
1408 
  rg2_latch8_an1 : a2_x2
1409 
    PORT MAP (
1410 
    vss => vss,
1411 
    vdd => vdd,
1412 
    q => rg2_latch8_o_an1,
1413 
    i1 => en_bufin_c,
1414 
    i0 => rg2_latch8_o_inv);
1415 
  rg2_latch8_an2 : a2_x2
1416 
    PORT MAP (
1417 
    vss => vss,
1418 
    vdd => vdd,
1419 
    q => rg2_latch8_o_an2,
1420 
    i1 => en_bufin_c,
1421 
    i0 => o1_8);
1422 
  rg2_latch8_nor1 : no3_x4
1423 
    PORT MAP (
1424 
    vss => vss,
1425 
    vdd => vdd,
1426 
    nq => data64in(40),
1427 
    i2 => rg2_latch8_o_nor2,
1428 
    i1 => netops1414,
1429 
    i0 => rg2_latch8_o_an1);
1430 
  rg2_latch8_nor2 : no2_x4
1431 
    PORT MAP (
1432 
    vss => vss,
1433 
    vdd => vdd,
1434 
    nq => rg2_latch8_o_nor2,
1435 
    i1 => rg2_latch8_o_an2,
1436 
    i0 => data64in(40));
1437 
  rg2_latch9_inv : inv_x2
1438 
    PORT MAP (
1439 
    vss => vss,
1440 
    vdd => vdd,
1441 
    nq => rg2_latch9_o_inv,
1442 
    i => o1_9);
1443 
  rg2_latch9_an1 : a2_x2
1444 
    PORT MAP (
1445 
    vss => vss,
1446 
    vdd => vdd,
1447 
    q => rg2_latch9_o_an1,
1448 
    i1 => en_bufin_c,
1449 
    i0 => rg2_latch9_o_inv);
1450 
  rg2_latch9_an2 : a2_x2
1451 
    PORT MAP (
1452 
    vss => vss,
1453 
    vdd => vdd,
1454 
    q => rg2_latch9_o_an2,
1455 
    i1 => en_bufin_c,
1456 
    i0 => o1_9);
1457 
  rg2_latch9_nor1 : no3_x4
1458 
    PORT MAP (
1459 
    vss => vss,
1460 
    vdd => vdd,
1461 
    nq => data64in(41),
1462 
    i2 => rg2_latch9_o_nor2,
1463 
    i1 => netops1414,
1464 
    i0 => rg2_latch9_o_an1);
1465 
  rg2_latch9_nor2 : no2_x4
1466 
    PORT MAP (
1467 
    vss => vss,
1468 
    vdd => vdd,
1469 
    nq => rg2_latch9_o_nor2,
1470 
    i1 => rg2_latch9_o_an2,
1471 
    i0 => data64in(41));
1472 
  rg2_latch10_inv : inv_x2
1473 
    PORT MAP (
1474 
    vss => vss,
1475 
    vdd => vdd,
1476 
    nq => rg2_latch10_o_inv,
1477 
    i => o1_10);
1478 
  rg2_latch10_an1 : a2_x2
1479 
    PORT MAP (
1480 
    vss => vss,
1481 
    vdd => vdd,
1482 
    q => rg2_latch10_o_an1,
1483 
    i1 => en_bufin_c,
1484 
    i0 => rg2_latch10_o_inv);
1485 
  rg2_latch10_an2 : a2_x2
1486 
    PORT MAP (
1487 
    vss => vss,
1488 
    vdd => vdd,
1489 
    q => rg2_latch10_o_an2,
1490 
    i1 => en_bufin_c,
1491 
    i0 => o1_10);
1492 
  rg2_latch10_nor1 : no3_x4
1493 
    PORT MAP (
1494 
    vss => vss,
1495 
    vdd => vdd,
1496 
    nq => data64in(42),
1497 
    i2 => rg2_latch10_o_nor2,
1498 
    i1 => netops1414,
1499 
    i0 => rg2_latch10_o_an1);
1500 
  rg2_latch10_nor2 : no2_x4
1501 
    PORT MAP (
1502 
    vss => vss,
1503 
    vdd => vdd,
1504 
    nq => rg2_latch10_o_nor2,
1505 
    i1 => rg2_latch10_o_an2,
1506 
    i0 => data64in(42));
1507 
  rg2_latch11_inv : inv_x2
1508 
    PORT MAP (
1509 
    vss => vss,
1510 
    vdd => vdd,
1511 
    nq => rg2_latch11_o_inv,
1512 
    i => o1_11);
1513 
  rg2_latch11_an1 : a2_x2
1514 
    PORT MAP (
1515 
    vss => vss,
1516 
    vdd => vdd,
1517 
    q => rg2_latch11_o_an1,
1518 
    i1 => en_bufin_c,
1519 
    i0 => rg2_latch11_o_inv);
1520 
  rg2_latch11_an2 : a2_x2
1521 
    PORT MAP (
1522 
    vss => vss,
1523 
    vdd => vdd,
1524 
    q => rg2_latch11_o_an2,
1525 
    i1 => en_bufin_c,
1526 
    i0 => o1_11);
1527 
  rg2_latch11_nor1 : no3_x4
1528 
    PORT MAP (
1529 
    vss => vss,
1530 
    vdd => vdd,
1531 
    nq => data64in(43),
1532 
    i2 => rg2_latch11_o_nor2,
1533 
    i1 => netops1414,
1534 
    i0 => rg2_latch11_o_an1);
1535 
  rg2_latch11_nor2 : no2_x4
1536 
    PORT MAP (
1537 
    vss => vss,
1538 
    vdd => vdd,
1539 
    nq => rg2_latch11_o_nor2,
1540 
    i1 => rg2_latch11_o_an2,
1541 
    i0 => data64in(43));
1542 
  rg2_latch12_inv : inv_x2
1543 
    PORT MAP (
1544 
    vss => vss,
1545 
    vdd => vdd,
1546 
    nq => rg2_latch12_o_inv,
1547 
    i => o1_12);
1548 
  rg2_latch12_an1 : a2_x2
1549 
    PORT MAP (
1550 
    vss => vss,
1551 
    vdd => vdd,
1552 
    q => rg2_latch12_o_an1,
1553 
    i1 => en_bufin_c,
1554 
    i0 => rg2_latch12_o_inv);
1555 
  rg2_latch12_an2 : a2_x2
1556 
    PORT MAP (
1557 
    vss => vss,
1558 
    vdd => vdd,
1559 
    q => rg2_latch12_o_an2,
1560 
    i1 => en_bufin_c,
1561 
    i0 => o1_12);
1562 
  rg2_latch12_nor1 : no3_x4
1563 
    PORT MAP (
1564 
    vss => vss,
1565 
    vdd => vdd,
1566 
    nq => data64in(44),
1567 
    i2 => rg2_latch12_o_nor2,
1568 
    i1 => netops1414,
1569 
    i0 => rg2_latch12_o_an1);
1570 
  rg2_latch12_nor2 : no2_x4
1571 
    PORT MAP (
1572 
    vss => vss,
1573 
    vdd => vdd,
1574 
    nq => rg2_latch12_o_nor2,
1575 
    i1 => rg2_latch12_o_an2,
1576 
    i0 => data64in(44));
1577 
  rg2_latch13_inv : inv_x2
1578 
    PORT MAP (
1579 
    vss => vss,
1580 
    vdd => vdd,
1581 
    nq => rg2_latch13_o_inv,
1582 
    i => o1_13);
1583 
  rg2_latch13_an1 : a2_x2
1584 
    PORT MAP (
1585 
    vss => vss,
1586 
    vdd => vdd,
1587 
    q => rg2_latch13_o_an1,
1588 
    i1 => en_bufin_c,
1589 
    i0 => rg2_latch13_o_inv);
1590 
  rg2_latch13_an2 : a2_x2
1591 
    PORT MAP (
1592 
    vss => vss,
1593 
    vdd => vdd,
1594 
    q => rg2_latch13_o_an2,
1595 
    i1 => en_bufin_c,
1596 
    i0 => o1_13);
1597 
  rg2_latch13_nor1 : no3_x4
1598 
    PORT MAP (
1599 
    vss => vss,
1600 
    vdd => vdd,
1601 
    nq => data64in(45),
1602 
    i2 => rg2_latch13_o_nor2,
1603 
    i1 => netops1414,
1604 
    i0 => rg2_latch13_o_an1);
1605 
  rg2_latch13_nor2 : no2_x4
1606 
    PORT MAP (
1607 
    vss => vss,
1608 
    vdd => vdd,
1609 
    nq => rg2_latch13_o_nor2,
1610 
    i1 => rg2_latch13_o_an2,
1611 
    i0 => data64in(45));
1612 
  rg2_latch14_inv : inv_x2
1613 
    PORT MAP (
1614 
    vss => vss,
1615 
    vdd => vdd,
1616 
    nq => rg2_latch14_o_inv,
1617 
    i => o1_14);
1618 
  rg2_latch14_an1 : a2_x2
1619 
    PORT MAP (
1620 
    vss => vss,
1621 
    vdd => vdd,
1622 
    q => rg2_latch14_o_an1,
1623 
    i1 => en_bufin_c,
1624 
    i0 => rg2_latch14_o_inv);
1625 
  rg2_latch14_an2 : a2_x2
1626 
    PORT MAP (
1627 
    vss => vss,
1628 
    vdd => vdd,
1629 
    q => rg2_latch14_o_an2,
1630 
    i1 => en_bufin_c,
1631 
    i0 => o1_14);
1632 
  rg2_latch14_nor1 : no3_x4
1633 
    PORT MAP (
1634 
    vss => vss,
1635 
    vdd => vdd,
1636 
    nq => data64in(46),
1637 
    i2 => rg2_latch14_o_nor2,
1638 
    i1 => netops1414,
1639 
    i0 => rg2_latch14_o_an1);
1640 
  rg2_latch14_nor2 : no2_x4
1641 
    PORT MAP (
1642 
    vss => vss,
1643 
    vdd => vdd,
1644 
    nq => rg2_latch14_o_nor2,
1645 
    i1 => rg2_latch14_o_an2,
1646 
    i0 => data64in(46));
1647 
  rg2_latch15_inv : inv_x2
1648 
    PORT MAP (
1649 
    vss => vss,
1650 
    vdd => vdd,
1651 
    nq => rg2_latch15_o_inv,
1652 
    i => o1_15);
1653 
  rg2_latch15_an1 : a2_x2
1654 
    PORT MAP (
1655 
    vss => vss,
1656 
    vdd => vdd,
1657 
    q => rg2_latch15_o_an1,
1658 
    i1 => en_bufin_c,
1659 
    i0 => rg2_latch15_o_inv);
1660 
  rg2_latch15_an2 : a2_x2
1661 
    PORT MAP (
1662 
    vss => vss,
1663 
    vdd => vdd,
1664 
    q => rg2_latch15_o_an2,
1665 
    i1 => en_bufin_c,
1666 
    i0 => o1_15);
1667 
  rg2_latch15_nor1 : no3_x4
1668 
    PORT MAP (
1669 
    vss => vss,
1670 
    vdd => vdd,
1671 
    nq => data64in(47),
1672 
    i2 => rg2_latch15_o_nor2,
1673 
    i1 => netops1414,
1674 
    i0 => rg2_latch15_o_an1);
1675 
  rg2_latch15_nor2 : no2_x4
1676 
    PORT MAP (
1677 
    vss => vss,
1678 
    vdd => vdd,
1679 
    nq => rg2_latch15_o_nor2,
1680 
    i1 => rg2_latch15_o_an2,
1681 
    i0 => data64in(47));
1682 
  rg3_latch0_inv : inv_x2
1683 
    PORT MAP (
1684 
    vss => vss,
1685 
    vdd => vdd,
1686 
    nq => rg3_latch0_o_inv,
1687 
    i => o2_16);
1688 
  rg3_latch0_an1 : a2_x2
1689 
    PORT MAP (
1690 
    vss => vss,
1691 
    vdd => vdd,
1692 
    q => rg3_latch0_o_an1,
1693 
    i1 => en_bufin,
1694 
    i0 => rg3_latch0_o_inv);
1695 
  rg3_latch0_an2 : a2_x2
1696 
    PORT MAP (
1697 
    vss => vss,
1698 
    vdd => vdd,
1699 
    q => rg3_latch0_o_an2,
1700 
    i1 => en_bufin,
1701 
    i0 => o2_16);
1702 
  rg3_latch0_nor1 : no3_x4
1703 
    PORT MAP (
1704 
    vss => vss,
1705 
    vdd => vdd,
1706 
    nq => data64in(16),
1707 
    i2 => rg3_latch0_o_nor2,
1708 
    i1 => netops1414,
1709 
    i0 => rg3_latch0_o_an1);
1710 
  rg3_latch0_nor2 : no2_x4
1711 
    PORT MAP (
1712 
    vss => vss,
1713 
    vdd => vdd,
1714 
    nq => rg3_latch0_o_nor2,
1715 
    i1 => rg3_latch0_o_an2,
1716 
    i0 => data64in(16));
1717 
  rg3_latch1_inv : inv_x2
1718 
    PORT MAP (
1719 
    vss => vss,
1720 
    vdd => vdd,
1721 
    nq => rg3_latch1_o_inv,
1722 
    i => o2_17);
1723 
  rg3_latch1_an1 : a2_x2
1724 
    PORT MAP (
1725 
    vss => vss,
1726 
    vdd => vdd,
1727 
    q => rg3_latch1_o_an1,
1728 
    i1 => en_bufin,
1729 
    i0 => rg3_latch1_o_inv);
1730 
  rg3_latch1_an2 : a2_x2
1731 
    PORT MAP (
1732 
    vss => vss,
1733 
    vdd => vdd,
1734 
    q => rg3_latch1_o_an2,
1735 
    i1 => en_bufin,
1736 
    i0 => o2_17);
1737 
  rg3_latch1_nor1 : no3_x4
1738 
    PORT MAP (
1739 
    vss => vss,
1740 
    vdd => vdd,
1741 
    nq => data64in(17),
1742 
    i2 => rg3_latch1_o_nor2,
1743 
    i1 => netops1414,
1744 
    i0 => rg3_latch1_o_an1);
1745 
  rg3_latch1_nor2 : no2_x4
1746 
    PORT MAP (
1747 
    vss => vss,
1748 
    vdd => vdd,
1749 
    nq => rg3_latch1_o_nor2,
1750 
    i1 => rg3_latch1_o_an2,
1751 
    i0 => data64in(17));
1752 
  rg3_latch2_inv : inv_x2
1753 
    PORT MAP (
1754 
    vss => vss,
1755 
    vdd => vdd,
1756 
    nq => rg3_latch2_o_inv,
1757 
    i => o2_18);
1758 
  rg3_latch2_an1 : a2_x2
1759 
    PORT MAP (
1760 
    vss => vss,
1761 
    vdd => vdd,
1762 
    q => rg3_latch2_o_an1,
1763 
    i1 => en_bufin,
1764 
    i0 => rg3_latch2_o_inv);
1765 
  rg3_latch2_an2 : a2_x2
1766 
    PORT MAP (
1767 
    vss => vss,
1768 
    vdd => vdd,
1769 
    q => rg3_latch2_o_an2,
1770 
    i1 => en_bufin,
1771 
    i0 => o2_18);
1772 
  rg3_latch2_nor1 : no3_x4
1773 
    PORT MAP (
1774 
    vss => vss,
1775 
    vdd => vdd,
1776 
    nq => data64in(18),
1777 
    i2 => rg3_latch2_o_nor2,
1778 
    i1 => netops1414,
1779 
    i0 => rg3_latch2_o_an1);
1780 
  rg3_latch2_nor2 : no2_x4
1781 
    PORT MAP (
1782 
    vss => vss,
1783 
    vdd => vdd,
1784 
    nq => rg3_latch2_o_nor2,
1785 
    i1 => rg3_latch2_o_an2,
1786 
    i0 => data64in(18));
1787 
  rg3_latch3_inv : inv_x2
1788 
    PORT MAP (
1789 
    vss => vss,
1790 
    vdd => vdd,
1791 
    nq => rg3_latch3_o_inv,
1792 
    i => o2_19);
1793 
  rg3_latch3_an1 : a2_x2
1794 
    PORT MAP (
1795 
    vss => vss,
1796 
    vdd => vdd,
1797 
    q => rg3_latch3_o_an1,
1798 
    i1 => en_bufin,
1799 
    i0 => rg3_latch3_o_inv);
1800 
  rg3_latch3_an2 : a2_x2
1801 
    PORT MAP (
1802 
    vss => vss,
1803 
    vdd => vdd,
1804 
    q => rg3_latch3_o_an2,
1805 
    i1 => en_bufin,
1806 
    i0 => o2_19);
1807 
  rg3_latch3_nor1 : no3_x4
1808 
    PORT MAP (
1809 
    vss => vss,
1810 
    vdd => vdd,
1811 
    nq => data64in(19),
1812 
    i2 => rg3_latch3_o_nor2,
1813 
    i1 => netops1414,
1814 
    i0 => rg3_latch3_o_an1);
1815 
  rg3_latch3_nor2 : no2_x4
1816 
    PORT MAP (
1817 
    vss => vss,
1818 
    vdd => vdd,
1819 
    nq => rg3_latch3_o_nor2,
1820 
    i1 => rg3_latch3_o_an2,
1821 
    i0 => data64in(19));
1822 
  rg3_latch4_inv : inv_x2
1823 
    PORT MAP (
1824 
    vss => vss,
1825 
    vdd => vdd,
1826 
    nq => rg3_latch4_o_inv,
1827 
    i => o2_20);
1828 
  rg3_latch4_an1 : a2_x2
1829 
    PORT MAP (
1830 
    vss => vss,
1831 
    vdd => vdd,
1832 
    q => rg3_latch4_o_an1,
1833 
    i1 => en_bufin,
1834 
    i0 => rg3_latch4_o_inv);
1835 
  rg3_latch4_an2 : a2_x2
1836 
    PORT MAP (
1837 
    vss => vss,
1838 
    vdd => vdd,
1839 
    q => rg3_latch4_o_an2,
1840 
    i1 => en_bufin,
1841 
    i0 => o2_20);
1842 
  rg3_latch4_nor1 : no3_x4
1843 
    PORT MAP (
1844 
    vss => vss,
1845 
    vdd => vdd,
1846 
    nq => data64in(20),
1847 
    i2 => rg3_latch4_o_nor2,
1848 
    i1 => netops1414,
1849 
    i0 => rg3_latch4_o_an1);
1850 
  rg3_latch4_nor2 : no2_x4
1851 
    PORT MAP (
1852 
    vss => vss,
1853 
    vdd => vdd,
1854 
    nq => rg3_latch4_o_nor2,
1855 
    i1 => rg3_latch4_o_an2,
1856 
    i0 => data64in(20));
1857 
  rg3_latch5_inv : inv_x2
1858 
    PORT MAP (
1859 
    vss => vss,
1860 
    vdd => vdd,
1861 
    nq => rg3_latch5_o_inv,
1862 
    i => o2_21);
1863 
  rg3_latch5_an1 : a2_x2
1864 
    PORT MAP (
1865 
    vss => vss,
1866 
    vdd => vdd,
1867 
    q => rg3_latch5_o_an1,
1868 
    i1 => en_bufin,
1869 
    i0 => rg3_latch5_o_inv);
1870 
  rg3_latch5_an2 : a2_x2
1871 
    PORT MAP (
1872 
    vss => vss,
1873 
    vdd => vdd,
1874 
    q => rg3_latch5_o_an2,
1875 
    i1 => en_bufin,
1876 
    i0 => o2_21);
1877 
  rg3_latch5_nor1 : no3_x4
1878 
    PORT MAP (
1879 
    vss => vss,
1880 
    vdd => vdd,
1881 
    nq => data64in(21),
1882 
    i2 => rg3_latch5_o_nor2,
1883 
    i1 => netops1414,
1884 
    i0 => rg3_latch5_o_an1);
1885 
  rg3_latch5_nor2 : no2_x4
1886 
    PORT MAP (
1887 
    vss => vss,
1888 
    vdd => vdd,
1889 
    nq => rg3_latch5_o_nor2,
1890 
    i1 => rg3_latch5_o_an2,
1891 
    i0 => data64in(21));
1892 
  rg3_latch6_inv : inv_x2
1893 
    PORT MAP (
1894 
    vss => vss,
1895 
    vdd => vdd,
1896 
    nq => rg3_latch6_o_inv,
1897 
    i => o2_22);
1898 
  rg3_latch6_an1 : a2_x2
1899 
    PORT MAP (
1900 
    vss => vss,
1901 
    vdd => vdd,
1902 
    q => rg3_latch6_o_an1,
1903 
    i1 => en_bufin,
1904 
    i0 => rg3_latch6_o_inv);
1905 
  rg3_latch6_an2 : a2_x2
1906 
    PORT MAP (
1907 
    vss => vss,
1908 
    vdd => vdd,
1909 
    q => rg3_latch6_o_an2,
1910 
    i1 => en_bufin,
1911 
    i0 => o2_22);
1912 
  rg3_latch6_nor1 : no3_x4
1913 
    PORT MAP (
1914 
    vss => vss,
1915 
    vdd => vdd,
1916 
    nq => data64in(22),
1917 
    i2 => rg3_latch6_o_nor2,
1918 
    i1 => netops1414,
1919 
    i0 => rg3_latch6_o_an1);
1920 
  rg3_latch6_nor2 : no2_x4
1921 
    PORT MAP (
1922 
    vss => vss,
1923 
    vdd => vdd,
1924 
    nq => rg3_latch6_o_nor2,
1925 
    i1 => rg3_latch6_o_an2,
1926 
    i0 => data64in(22));
1927 
  rg3_latch7_inv : inv_x2
1928 
    PORT MAP (
1929 
    vss => vss,
1930 
    vdd => vdd,
1931 
    nq => rg3_latch7_o_inv,
1932 
    i => o2_23);
1933 
  rg3_latch7_an1 : a2_x2
1934 
    PORT MAP (
1935 
    vss => vss,
1936 
    vdd => vdd,
1937 
    q => rg3_latch7_o_an1,
1938 
    i1 => en_bufin,
1939 
    i0 => rg3_latch7_o_inv);
1940 
  rg3_latch7_an2 : a2_x2
1941 
    PORT MAP (
1942 
    vss => vss,
1943 
    vdd => vdd,
1944 
    q => rg3_latch7_o_an2,
1945 
    i1 => en_bufin,
1946 
    i0 => o2_23);
1947 
  rg3_latch7_nor1 : no3_x4
1948 
    PORT MAP (
1949 
    vss => vss,
1950 
    vdd => vdd,
1951 
    nq => data64in(23),
1952 
    i2 => rg3_latch7_o_nor2,
1953 
    i1 => netops1414,
1954 
    i0 => rg3_latch7_o_an1);
1955 
  rg3_latch7_nor2 : no2_x4
1956 
    PORT MAP (
1957 
    vss => vss,
1958 
    vdd => vdd,
1959 
    nq => rg3_latch7_o_nor2,
1960 
    i1 => rg3_latch7_o_an2,
1961 
    i0 => data64in(23));
1962 
  rg3_latch8_inv : inv_x2
1963 
    PORT MAP (
1964 
    vss => vss,
1965 
    vdd => vdd,
1966 
    nq => rg3_latch8_o_inv,
1967 
    i => o2_24);
1968 
  rg3_latch8_an1 : a2_x2
1969 
    PORT MAP (
1970 
    vss => vss,
1971 
    vdd => vdd,
1972 
    q => rg3_latch8_o_an1,
1973 
    i1 => en_bufin,
1974 
    i0 => rg3_latch8_o_inv);
1975 
  rg3_latch8_an2 : a2_x2
1976 
    PORT MAP (
1977 
    vss => vss,
1978 
    vdd => vdd,
1979 
    q => rg3_latch8_o_an2,
1980 
    i1 => en_bufin,
1981 
    i0 => o2_24);
1982 
  rg3_latch8_nor1 : no3_x4
1983 
    PORT MAP (
1984 
    vss => vss,
1985 
    vdd => vdd,
1986 
    nq => data64in(24),
1987 
    i2 => rg3_latch8_o_nor2,
1988 
    i1 => netops1414,
1989 
    i0 => rg3_latch8_o_an1);
1990 
  rg3_latch8_nor2 : no2_x4
1991 
    PORT MAP (
1992 
    vss => vss,
1993 
    vdd => vdd,
1994 
    nq => rg3_latch8_o_nor2,
1995 
    i1 => rg3_latch8_o_an2,
1996 
    i0 => data64in(24));
1997 
  rg3_latch9_inv : inv_x2
1998 
    PORT MAP (
1999 
    vss => vss,
2000 
    vdd => vdd,
2001 
    nq => rg3_latch9_o_inv,
2002 
    i => o2_25);
2003 
  rg3_latch9_an1 : a2_x2
2004 
    PORT MAP (
2005 
    vss => vss,
2006 
    vdd => vdd,
2007 
    q => rg3_latch9_o_an1,
2008 
    i1 => en_bufin,
2009 
    i0 => rg3_latch9_o_inv);
2010 
  rg3_latch9_an2 : a2_x2
2011 
    PORT MAP (
2012 
    vss => vss,
2013 
    vdd => vdd,
2014 
    q => rg3_latch9_o_an2,
2015 
    i1 => en_bufin,
2016 
    i0 => o2_25);
2017 
  rg3_latch9_nor1 : no3_x4
2018 
    PORT MAP (
2019 
    vss => vss,
2020 
    vdd => vdd,
2021 
    nq => data64in(25),
2022 
    i2 => rg3_latch9_o_nor2,
2023 
    i1 => netops1414,
2024 
    i0 => rg3_latch9_o_an1);
2025 
  rg3_latch9_nor2 : no2_x4
2026 
    PORT MAP (
2027 
    vss => vss,
2028 
    vdd => vdd,
2029 
    nq => rg3_latch9_o_nor2,
2030 
    i1 => rg3_latch9_o_an2,
2031 
    i0 => data64in(25));
2032 
  rg3_latch10_inv : inv_x2
2033 
    PORT MAP (
2034 
    vss => vss,
2035 
    vdd => vdd,
2036 
    nq => rg3_latch10_o_inv,
2037 
    i => o2_26);
2038 
  rg3_latch10_an1 : a2_x2
2039 
    PORT MAP (
2040 
    vss => vss,
2041 
    vdd => vdd,
2042 
    q => rg3_latch10_o_an1,
2043 
    i1 => en_bufin,
2044 
    i0 => rg3_latch10_o_inv);
2045 
  rg3_latch10_an2 : a2_x2
2046 
    PORT MAP (
2047 
    vss => vss,
2048 
    vdd => vdd,
2049 
    q => rg3_latch10_o_an2,
2050 
    i1 => en_bufin,
2051 
    i0 => o2_26);
2052 
  rg3_latch10_nor1 : no3_x4
2053 
    PORT MAP (
2054 
    vss => vss,
2055 
    vdd => vdd,
2056 
    nq => data64in(26),
2057 
    i2 => rg3_latch10_o_nor2,
2058 
    i1 => netops1414,
2059 
    i0 => rg3_latch10_o_an1);
2060 
  rg3_latch10_nor2 : no2_x4
2061 
    PORT MAP (
2062 
    vss => vss,
2063 
    vdd => vdd,
2064 
    nq => rg3_latch10_o_nor2,
2065 
    i1 => rg3_latch10_o_an2,
2066 
    i0 => data64in(26));
2067 
  rg3_latch11_inv : inv_x2
2068 
    PORT MAP (
2069 
    vss => vss,
2070 
    vdd => vdd,
2071 
    nq => rg3_latch11_o_inv,
2072 
    i => o2_27);
2073 
  rg3_latch11_an1 : a2_x2
2074 
    PORT MAP (
2075 
    vss => vss,
2076 
    vdd => vdd,
2077 
    q => rg3_latch11_o_an1,
2078 
    i1 => en_bufin,
2079 
    i0 => rg3_latch11_o_inv);
2080 
  rg3_latch11_an2 : a2_x2
2081 
    PORT MAP (
2082 
    vss => vss,
2083 
    vdd => vdd,
2084 
    q => rg3_latch11_o_an2,
2085 
    i1 => en_bufin,
2086 
    i0 => o2_27);
2087 
  rg3_latch11_nor1 : no3_x4
2088 
    PORT MAP (
2089 
    vss => vss,
2090 
    vdd => vdd,
2091 
    nq => data64in(27),
2092 
    i2 => rg3_latch11_o_nor2,
2093 
    i1 => netops1414,
2094 
    i0 => rg3_latch11_o_an1);
2095 
  rg3_latch11_nor2 : no2_x4
2096 
    PORT MAP (
2097 
    vss => vss,
2098 
    vdd => vdd,
2099 
    nq => rg3_latch11_o_nor2,
2100 
    i1 => rg3_latch11_o_an2,
2101 
    i0 => data64in(27));
2102 
  rg3_latch12_inv : inv_x2
2103 
    PORT MAP (
2104 
    vss => vss,
2105 
    vdd => vdd,
2106 
    nq => rg3_latch12_o_inv,
2107 
    i => o2_28);
2108 
  rg3_latch12_an1 : a2_x2
2109 
    PORT MAP (
2110 
    vss => vss,
2111 
    vdd => vdd,
2112 
    q => rg3_latch12_o_an1,
2113 
    i1 => en_bufin,
2114 
    i0 => rg3_latch12_o_inv);
2115 
  rg3_latch12_an2 : a2_x2
2116 
    PORT MAP (
2117 
    vss => vss,
2118 
    vdd => vdd,
2119 
    q => rg3_latch12_o_an2,
2120 
    i1 => en_bufin,
2121 
    i0 => o2_28);
2122 
  rg3_latch12_nor1 : no3_x4
2123 
    PORT MAP (
2124 
    vss => vss,
2125 
    vdd => vdd,
2126 
    nq => data64in(28),
2127 
    i2 => rg3_latch12_o_nor2,
2128 
    i1 => netops1414,
2129 
    i0 => rg3_latch12_o_an1);
2130 
  rg3_latch12_nor2 : no2_x4
2131 
    PORT MAP (
2132 
    vss => vss,
2133 
    vdd => vdd,
2134 
    nq => rg3_latch12_o_nor2,
2135 
    i1 => rg3_latch12_o_an2,
2136 
    i0 => data64in(28));
2137 
  rg3_latch13_inv : inv_x2
2138 
    PORT MAP (
2139 
    vss => vss,
2140 
    vdd => vdd,
2141 
    nq => rg3_latch13_o_inv,
2142 
    i => o2_29);
2143 
  rg3_latch13_an1 : a2_x2
2144 
    PORT MAP (
2145 
    vss => vss,
2146 
    vdd => vdd,
2147 
    q => rg3_latch13_o_an1,
2148 
    i1 => en_bufin,
2149 
    i0 => rg3_latch13_o_inv);
2150 
  rg3_latch13_an2 : a2_x2
2151 
    PORT MAP (
2152 
    vss => vss,
2153 
    vdd => vdd,
2154 
    q => rg3_latch13_o_an2,
2155 
    i1 => en_bufin,
2156 
    i0 => o2_29);
2157 
  rg3_latch13_nor1 : no3_x4
2158 
    PORT MAP (
2159 
    vss => vss,
2160 
    vdd => vdd,
2161 
    nq => data64in(29),
2162 
    i2 => rg3_latch13_o_nor2,
2163 
    i1 => netops1414,
2164 
    i0 => rg3_latch13_o_an1);
2165 
  rg3_latch13_nor2 : no2_x4
2166 
    PORT MAP (
2167 
    vss => vss,
2168 
    vdd => vdd,
2169 
    nq => rg3_latch13_o_nor2,
2170 
    i1 => rg3_latch13_o_an2,
2171 
    i0 => data64in(29));
2172 
  rg3_latch14_inv : inv_x2
2173 
    PORT MAP (
2174 
    vss => vss,
2175 
    vdd => vdd,
2176 
    nq => rg3_latch14_o_inv,
2177 
    i => o2_30);
2178 
  rg3_latch14_an1 : a2_x2
2179 
    PORT MAP (
2180 
    vss => vss,
2181 
    vdd => vdd,
2182 
    q => rg3_latch14_o_an1,
2183 
    i1 => en_bufin,
2184 
    i0 => rg3_latch14_o_inv);
2185 
  rg3_latch14_an2 : a2_x2
2186 
    PORT MAP (
2187 
    vss => vss,
2188 
    vdd => vdd,
2189 
    q => rg3_latch14_o_an2,
2190 
    i1 => en_bufin,
2191 
    i0 => o2_30);
2192 
  rg3_latch14_nor1 : no3_x4
2193 
    PORT MAP (
2194 
    vss => vss,
2195 
    vdd => vdd,
2196 
    nq => data64in(30),
2197 
    i2 => rg3_latch14_o_nor2,
2198 
    i1 => netops1414,
2199 
    i0 => rg3_latch14_o_an1);
2200 
  rg3_latch14_nor2 : no2_x4
2201 
    PORT MAP (
2202 
    vss => vss,
2203 
    vdd => vdd,
2204 
    nq => rg3_latch14_o_nor2,
2205 
    i1 => rg3_latch14_o_an2,
2206 
    i0 => data64in(30));
2207 
  rg3_latch15_inv : inv_x2
2208 
    PORT MAP (
2209 
    vss => vss,
2210 
    vdd => vdd,
2211 
    nq => rg3_latch15_o_inv,
2212 
    i => o2_31);
2213 
  rg3_latch15_an1 : a2_x2
2214 
    PORT MAP (
2215 
    vss => vss,
2216 
    vdd => vdd,
2217 
    q => rg3_latch15_o_an1,
2218 
    i1 => en_bufin,
2219 
    i0 => rg3_latch15_o_inv);
2220 
  rg3_latch15_an2 : a2_x2
2221 
    PORT MAP (
2222 
    vss => vss,
2223 
    vdd => vdd,
2224 
    q => rg3_latch15_o_an2,
2225 
    i1 => en_bufin,
2226 
    i0 => o2_31);
2227 
  rg3_latch15_nor1 : no3_x4
2228 
    PORT MAP (
2229 
    vss => vss,
2230 
    vdd => vdd,
2231 
    nq => data64in(31),
2232 
    i2 => rg3_latch15_o_nor2,
2233 
    i1 => netops1414,
2234 
    i0 => rg3_latch15_o_an1);
2235 
  rg3_latch15_nor2 : no2_x4
2236 
    PORT MAP (
2237 
    vss => vss,
2238 
    vdd => vdd,
2239 
    nq => rg3_latch15_o_nor2,
2240 
    i1 => rg3_latch15_o_an2,
2241 
    i0 => data64in(31));
2242 
  rg4_latch0_inv : inv_x2
2243 
    PORT MAP (
2244 
    vss => vss,
2245 
    vdd => vdd,
2246 
    nq => rg4_latch0_o_inv,
2247 
    i => o2_0);
2248 
  rg4_latch0_an1 : a2_x2
2249 
    PORT MAP (
2250 
    vss => vss,
2251 
    vdd => vdd,
2252 
    q => rg4_latch0_o_an1,
2253 
    i1 => en_bufin,
2254 
    i0 => rg4_latch0_o_inv);
2255 
  rg4_latch0_an2 : a2_x2
2256 
    PORT MAP (
2257 
    vss => vss,
2258 
    vdd => vdd,
2259 
    q => rg4_latch0_o_an2,
2260 
    i1 => en_bufin,
2261 
    i0 => o2_0);
2262 
  rg4_latch0_nor1 : no3_x4
2263 
    PORT MAP (
2264 
    vss => vss,
2265 
    vdd => vdd,
2266 
    nq => data64in(0),
2267 
    i2 => rg4_latch0_o_nor2,
2268 
    i1 => netops1414,
2269 
    i0 => rg4_latch0_o_an1);
2270 
  rg4_latch0_nor2 : no2_x4
2271 
    PORT MAP (
2272 
    vss => vss,
2273 
    vdd => vdd,
2274 
    nq => rg4_latch0_o_nor2,
2275 
    i1 => rg4_latch0_o_an2,
2276 
    i0 => data64in(0));
2277 
  rg4_latch1_inv : inv_x2
2278 
    PORT MAP (
2279 
    vss => vss,
2280 
    vdd => vdd,
2281 
    nq => rg4_latch1_o_inv,
2282 
    i => o2_1);
2283 
  rg4_latch1_an1 : a2_x2
2284 
    PORT MAP (
2285 
    vss => vss,
2286 
    vdd => vdd,
2287 
    q => rg4_latch1_o_an1,
2288 
    i1 => en_bufin,
2289 
    i0 => rg4_latch1_o_inv);
2290 
  rg4_latch1_an2 : a2_x2
2291 
    PORT MAP (
2292 
    vss => vss,
2293 
    vdd => vdd,
2294 
    q => rg4_latch1_o_an2,
2295 
    i1 => en_bufin,
2296 
    i0 => o2_1);
2297 
  rg4_latch1_nor1 : no3_x4
2298 
    PORT MAP (
2299 
    vss => vss,
2300 
    vdd => vdd,
2301 
    nq => data64in(1),
2302 
    i2 => rg4_latch1_o_nor2,
2303 
    i1 => netops1414,
2304 
    i0 => rg4_latch1_o_an1);
2305 
  rg4_latch1_nor2 : no2_x4
2306 
    PORT MAP (
2307 
    vss => vss,
2308 
    vdd => vdd,
2309 
    nq => rg4_latch1_o_nor2,
2310 
    i1 => rg4_latch1_o_an2,
2311 
    i0 => data64in(1));
2312 
  rg4_latch2_inv : inv_x2
2313 
    PORT MAP (
2314 
    vss => vss,
2315 
    vdd => vdd,
2316 
    nq => rg4_latch2_o_inv,
2317 
    i => o2_2);
2318 
  rg4_latch2_an1 : a2_x2
2319 
    PORT MAP (
2320 
    vss => vss,
2321 
    vdd => vdd,
2322 
    q => rg4_latch2_o_an1,
2323 
    i1 => en_bufin,
2324 
    i0 => rg4_latch2_o_inv);
2325 
  rg4_latch2_an2 : a2_x2
2326 
    PORT MAP (
2327 
    vss => vss,
2328 
    vdd => vdd,
2329 
    q => rg4_latch2_o_an2,
2330 
    i1 => en_bufin,
2331 
    i0 => o2_2);
2332 
  rg4_latch2_nor1 : no3_x4
2333 
    PORT MAP (
2334 
    vss => vss,
2335 
    vdd => vdd,
2336 
    nq => data64in(2),
2337 
    i2 => rg4_latch2_o_nor2,
2338 
    i1 => netops1414,
2339 
    i0 => rg4_latch2_o_an1);
2340 
  rg4_latch2_nor2 : no2_x4
2341 
    PORT MAP (
2342 
    vss => vss,
2343 
    vdd => vdd,
2344 
    nq => rg4_latch2_o_nor2,
2345 
    i1 => rg4_latch2_o_an2,
2346 
    i0 => data64in(2));
2347 
  rg4_latch3_inv : inv_x2
2348 
    PORT MAP (
2349 
    vss => vss,
2350 
    vdd => vdd,
2351 
    nq => rg4_latch3_o_inv,
2352 
    i => o2_3);
2353 
  rg4_latch3_an1 : a2_x2
2354 
    PORT MAP (
2355 
    vss => vss,
2356 
    vdd => vdd,
2357 
    q => rg4_latch3_o_an1,
2358 
    i1 => en_bufin,
2359 
    i0 => rg4_latch3_o_inv);
2360 
  rg4_latch3_an2 : a2_x2
2361 
    PORT MAP (
2362 
    vss => vss,
2363 
    vdd => vdd,
2364 
    q => rg4_latch3_o_an2,
2365 
    i1 => en_bufin,
2366 
    i0 => o2_3);
2367 
  rg4_latch3_nor1 : no3_x4
2368 
    PORT MAP (
2369 
    vss => vss,
2370 
    vdd => vdd,
2371 
    nq => data64in(3),
2372 
    i2 => rg4_latch3_o_nor2,
2373 
    i1 => netops1414,
2374 
    i0 => rg4_latch3_o_an1);
2375 
  rg4_latch3_nor2 : no2_x4
2376 
    PORT MAP (
2377 
    vss => vss,
2378 
    vdd => vdd,
2379 
    nq => rg4_latch3_o_nor2,
2380 
    i1 => rg4_latch3_o_an2,
2381 
    i0 => data64in(3));
2382 
  rg4_latch4_inv : inv_x2
2383 
    PORT MAP (
2384 
    vss => vss,
2385 
    vdd => vdd,
2386 
    nq => rg4_latch4_o_inv,
2387 
    i => o2_4);
2388 
  rg4_latch4_an1 : a2_x2
2389 
    PORT MAP (
2390 
    vss => vss,
2391 
    vdd => vdd,
2392 
    q => rg4_latch4_o_an1,
2393 
    i1 => en_bufin,
2394 
    i0 => rg4_latch4_o_inv);
2395 
  rg4_latch4_an2 : a2_x2
2396 
    PORT MAP (
2397 
    vss => vss,
2398 
    vdd => vdd,
2399 
    q => rg4_latch4_o_an2,
2400 
    i1 => en_bufin,
2401 
    i0 => o2_4);
2402 
  rg4_latch4_nor1 : no3_x4
2403 
    PORT MAP (
2404 
    vss => vss,
2405 
    vdd => vdd,
2406 
    nq => data64in(4),
2407 
    i2 => rg4_latch4_o_nor2,
2408 
    i1 => netops1414,
2409 
    i0 => rg4_latch4_o_an1);
2410 
  rg4_latch4_nor2 : no2_x4
2411 
    PORT MAP (
2412 
    vss => vss,
2413 
    vdd => vdd,
2414 
    nq => rg4_latch4_o_nor2,
2415 
    i1 => rg4_latch4_o_an2,
2416 
    i0 => data64in(4));
2417 
  rg4_latch5_inv : inv_x2
2418 
    PORT MAP (
2419 
    vss => vss,
2420 
    vdd => vdd,
2421 
    nq => rg4_latch5_o_inv,
2422 
    i => o2_5);
2423 
  rg4_latch5_an1 : a2_x2
2424 
    PORT MAP (
2425 
    vss => vss,
2426 
    vdd => vdd,
2427 
    q => rg4_latch5_o_an1,
2428 
    i1 => en_bufin,
2429 
    i0 => rg4_latch5_o_inv);
2430 
  rg4_latch5_an2 : a2_x2
2431 
    PORT MAP (
2432 
    vss => vss,
2433 
    vdd => vdd,
2434 
    q => rg4_latch5_o_an2,
2435 
    i1 => en_bufin,
2436 
    i0 => o2_5);
2437 
  rg4_latch5_nor1 : no3_x4
2438 
    PORT MAP (
2439 
    vss => vss,
2440 
    vdd => vdd,
2441 
    nq => data64in(5),
2442 
    i2 => rg4_latch5_o_nor2,
2443 
    i1 => netops1414,
2444 
    i0 => rg4_latch5_o_an1);
2445 
  rg4_latch5_nor2 : no2_x4
2446 
    PORT MAP (
2447 
    vss => vss,
2448 
    vdd => vdd,
2449 
    nq => rg4_latch5_o_nor2,
2450 
    i1 => rg4_latch5_o_an2,
2451 
    i0 => data64in(5));
2452 
  rg4_latch6_inv : inv_x2
2453 
    PORT MAP (
2454 
    vss => vss,
2455 
    vdd => vdd,
2456 
    nq => rg4_latch6_o_inv,
2457 
    i => o2_6);
2458 
  rg4_latch6_an1 : a2_x2
2459 
    PORT MAP (
2460 
    vss => vss,
2461 
    vdd => vdd,
2462 
    q => rg4_latch6_o_an1,
2463 
    i1 => en_bufin,
2464 
    i0 => rg4_latch6_o_inv);
2465 
  rg4_latch6_an2 : a2_x2
2466 
    PORT MAP (
2467 
    vss => vss,
2468 
    vdd => vdd,
2469 
    q => rg4_latch6_o_an2,
2470 
    i1 => en_bufin,
2471 
    i0 => o2_6);
2472 
  rg4_latch6_nor1 : no3_x4
2473 
    PORT MAP (
2474 
    vss => vss,
2475 
    vdd => vdd,
2476 
    nq => data64in(6),
2477 
    i2 => rg4_latch6_o_nor2,
2478 
    i1 => netops1414,
2479 
    i0 => rg4_latch6_o_an1);
2480 
  rg4_latch6_nor2 : no2_x4
2481 
    PORT MAP (
2482 
    vss => vss,
2483 
    vdd => vdd,
2484 
    nq => rg4_latch6_o_nor2,
2485 
    i1 => rg4_latch6_o_an2,
2486 
    i0 => data64in(6));
2487 
  rg4_latch7_inv : inv_x2
2488 
    PORT MAP (
2489 
    vss => vss,
2490 
    vdd => vdd,
2491 
    nq => rg4_latch7_o_inv,
2492 
    i => o2_7);
2493 
  rg4_latch7_an1 : a2_x2
2494 
    PORT MAP (
2495 
    vss => vss,
2496 
    vdd => vdd,
2497 
    q => rg4_latch7_o_an1,
2498 
    i1 => en_bufin,
2499 
    i0 => rg4_latch7_o_inv);
2500 
  rg4_latch7_an2 : a2_x2
2501 
    PORT MAP (
2502 
    vss => vss,
2503 
    vdd => vdd,
2504 
    q => rg4_latch7_o_an2,
2505 
    i1 => en_bufin,
2506 
    i0 => o2_7);
2507 
  rg4_latch7_nor1 : no3_x4
2508 
    PORT MAP (
2509 
    vss => vss,
2510 
    vdd => vdd,
2511 
    nq => data64in(7),
2512 
    i2 => rg4_latch7_o_nor2,
2513 
    i1 => netops1414,
2514 
    i0 => rg4_latch7_o_an1);
2515 
  rg4_latch7_nor2 : no2_x4
2516 
    PORT MAP (
2517 
    vss => vss,
2518 
    vdd => vdd,
2519 
    nq => rg4_latch7_o_nor2,
2520 
    i1 => rg4_latch7_o_an2,
2521 
    i0 => data64in(7));
2522 
  rg4_latch8_inv : inv_x2
2523 
    PORT MAP (
2524 
    vss => vss,
2525 
    vdd => vdd,
2526 
    nq => rg4_latch8_o_inv,
2527 
    i => o2_8);
2528 
  rg4_latch8_an1 : a2_x2
2529 
    PORT MAP (
2530 
    vss => vss,
2531 
    vdd => vdd,
2532 
    q => rg4_latch8_o_an1,
2533 
    i1 => en_bufin,
2534 
    i0 => rg4_latch8_o_inv);
2535 
  rg4_latch8_an2 : a2_x2
2536 
    PORT MAP (
2537 
    vss => vss,
2538 
    vdd => vdd,
2539 
    q => rg4_latch8_o_an2,
2540 
    i1 => en_bufin,
2541 
    i0 => o2_8);
2542 
  rg4_latch8_nor1 : no3_x4
2543 
    PORT MAP (
2544 
    vss => vss,
2545 
    vdd => vdd,
2546 
    nq => data64in(8),
2547 
    i2 => rg4_latch8_o_nor2,
2548 
    i1 => netops1414,
2549 
    i0 => rg4_latch8_o_an1);
2550 
  rg4_latch8_nor2 : no2_x4
2551 
    PORT MAP (
2552 
    vss => vss,
2553 
    vdd => vdd,
2554 
    nq => rg4_latch8_o_nor2,
2555 
    i1 => rg4_latch8_o_an2,
2556 
    i0 => data64in(8));
2557 
  rg4_latch9_inv : inv_x2
2558 
    PORT MAP (
2559 
    vss => vss,
2560 
    vdd => vdd,
2561 
    nq => rg4_latch9_o_inv,
2562 
    i => o2_9);
2563 
  rg4_latch9_an1 : a2_x2
2564 
    PORT MAP (
2565 
    vss => vss,
2566 
    vdd => vdd,
2567 
    q => rg4_latch9_o_an1,
2568 
    i1 => en_bufin,
2569 
    i0 => rg4_latch9_o_inv);
2570 
  rg4_latch9_an2 : a2_x2
2571 
    PORT MAP (
2572 
    vss => vss,
2573 
    vdd => vdd,
2574 
    q => rg4_latch9_o_an2,
2575 
    i1 => en_bufin,
2576 
    i0 => o2_9);
2577 
  rg4_latch9_nor1 : no3_x4
2578 
    PORT MAP (
2579 
    vss => vss,
2580 
    vdd => vdd,
2581 
    nq => data64in(9),
2582 
    i2 => rg4_latch9_o_nor2,
2583 
    i1 => netops1414,
2584 
    i0 => rg4_latch9_o_an1);
2585 
  rg4_latch9_nor2 : no2_x4
2586 
    PORT MAP (
2587 
    vss => vss,
2588 
    vdd => vdd,
2589 
    nq => rg4_latch9_o_nor2,
2590 
    i1 => rg4_latch9_o_an2,
2591 
    i0 => data64in(9));
2592 
  rg4_latch10_inv : inv_x2
2593 
    PORT MAP (
2594 
    vss => vss,
2595 
    vdd => vdd,
2596 
    nq => rg4_latch10_o_inv,
2597 
    i => o2_10);
2598 
  rg4_latch10_an1 : a2_x2
2599 
    PORT MAP (
2600 
    vss => vss,
2601 
    vdd => vdd,
2602 
    q => rg4_latch10_o_an1,
2603 
    i1 => en_bufin,
2604 
    i0 => rg4_latch10_o_inv);
2605 
  rg4_latch10_an2 : a2_x2
2606 
    PORT MAP (
2607 
    vss => vss,
2608 
    vdd => vdd,
2609 
    q => rg4_latch10_o_an2,
2610 
    i1 => en_bufin,
2611 
    i0 => o2_10);
2612 
  rg4_latch10_nor1 : no3_x4
2613 
    PORT MAP (
2614 
    vss => vss,
2615 
    vdd => vdd,
2616 
    nq => data64in(10),
2617 
    i2 => rg4_latch10_o_nor2,
2618 
    i1 => netops1414,
2619 
    i0 => rg4_latch10_o_an1);
2620 
  rg4_latch10_nor2 : no2_x4
2621 
    PORT MAP (
2622 
    vss => vss,
2623 
    vdd => vdd,
2624 
    nq => rg4_latch10_o_nor2,
2625 
    i1 => rg4_latch10_o_an2,
2626 
    i0 => data64in(10));
2627 
  rg4_latch11_inv : inv_x2
2628 
    PORT MAP (
2629 
    vss => vss,
2630 
    vdd => vdd,
2631 
    nq => rg4_latch11_o_inv,
2632 
    i => o2_11);
2633 
  rg4_latch11_an1 : a2_x2
2634 
    PORT MAP (
2635 
    vss => vss,
2636 
    vdd => vdd,
2637 
    q => rg4_latch11_o_an1,
2638 
    i1 => en_bufin,
2639 
    i0 => rg4_latch11_o_inv);
2640 
  rg4_latch11_an2 : a2_x2
2641 
    PORT MAP (
2642 
    vss => vss,
2643 
    vdd => vdd,
2644 
    q => rg4_latch11_o_an2,
2645 
    i1 => en_bufin,
2646 
    i0 => o2_11);
2647 
  rg4_latch11_nor1 : no3_x4
2648 
    PORT MAP (
2649 
    vss => vss,
2650 
    vdd => vdd,
2651 
    nq => data64in(11),
2652 
    i2 => rg4_latch11_o_nor2,
2653 
    i1 => netops1414,
2654 
    i0 => rg4_latch11_o_an1);
2655 
  rg4_latch11_nor2 : no2_x4
2656 
    PORT MAP (
2657 
    vss => vss,
2658 
    vdd => vdd,
2659 
    nq => rg4_latch11_o_nor2,
2660 
    i1 => rg4_latch11_o_an2,
2661 
    i0 => data64in(11));
2662 
  rg4_latch12_inv : inv_x2
2663 
    PORT MAP (
2664 
    vss => vss,
2665 
    vdd => vdd,
2666 
    nq => rg4_latch12_o_inv,
2667 
    i => o2_12);
2668 
  rg4_latch12_an1 : a2_x2
2669 
    PORT MAP (
2670 
    vss => vss,
2671 
    vdd => vdd,
2672 
    q => rg4_latch12_o_an1,
2673 
    i1 => en_bufin,
2674 
    i0 => rg4_latch12_o_inv);
2675 
  rg4_latch12_an2 : a2_x2
2676 
    PORT MAP (
2677 
    vss => vss,
2678 
    vdd => vdd,
2679 
    q => rg4_latch12_o_an2,
2680 
    i1 => en_bufin,
2681 
    i0 => o2_12);
2682 
  rg4_latch12_nor1 : no3_x4
2683 
    PORT MAP (
2684 
    vss => vss,
2685 
    vdd => vdd,
2686 
    nq => data64in(12),
2687 
    i2 => rg4_latch12_o_nor2,
2688 
    i1 => netops1414,
2689 
    i0 => rg4_latch12_o_an1);
2690 
  rg4_latch12_nor2 : no2_x4
2691 
    PORT MAP (
2692 
    vss => vss,
2693 
    vdd => vdd,
2694 
    nq => rg4_latch12_o_nor2,
2695 
    i1 => rg4_latch12_o_an2,
2696 
    i0 => data64in(12));
2697 
  rg4_latch13_inv : inv_x2
2698 
    PORT MAP (
2699 
    vss => vss,
2700 
    vdd => vdd,
2701 
    nq => rg4_latch13_o_inv,
2702 
    i => o2_13);
2703 
  rg4_latch13_an1 : a2_x2
2704 
    PORT MAP (
2705 
    vss => vss,
2706 
    vdd => vdd,
2707 
    q => rg4_latch13_o_an1,
2708 
    i1 => en_bufin,
2709 
    i0 => rg4_latch13_o_inv);
2710 
  rg4_latch13_an2 : a2_x2
2711 
    PORT MAP (
2712 
    vss => vss,
2713 
    vdd => vdd,
2714 
    q => rg4_latch13_o_an2,
2715 
    i1 => en_bufin,
2716 
    i0 => o2_13);
2717 
  rg4_latch13_nor1 : no3_x4
2718 
    PORT MAP (
2719 
    vss => vss,
2720 
    vdd => vdd,
2721 
    nq => data64in(13),
2722 
    i2 => rg4_latch13_o_nor2,
2723 
    i1 => netops1414,
2724 
    i0 => rg4_latch13_o_an1);
2725 
  rg4_latch13_nor2 : no2_x4
2726 
    PORT MAP (
2727 
    vss => vss,
2728 
    vdd => vdd,
2729 
    nq => rg4_latch13_o_nor2,
2730 
    i1 => rg4_latch13_o_an2,
2731 
    i0 => data64in(13));
2732 
  rg4_latch14_inv : inv_x2
2733 
    PORT MAP (
2734 
    vss => vss,
2735 
    vdd => vdd,
2736 
    nq => rg4_latch14_o_inv,
2737 
    i => o2_14);
2738 
  rg4_latch14_an1 : a2_x2
2739 
    PORT MAP (
2740 
    vss => vss,
2741 
    vdd => vdd,
2742 
    q => rg4_latch14_o_an1,
2743 
    i1 => en_bufin,
2744 
    i0 => rg4_latch14_o_inv);
2745 
  rg4_latch14_an2 : a2_x2
2746 
    PORT MAP (
2747 
    vss => vss,
2748 
    vdd => vdd,
2749 
    q => rg4_latch14_o_an2,
2750 
    i1 => en_bufin,
2751 
    i0 => o2_14);
2752 
  rg4_latch14_nor1 : no3_x4
2753 
    PORT MAP (
2754 
    vss => vss,
2755 
    vdd => vdd,
2756 
    nq => data64in(14),
2757 
    i2 => rg4_latch14_o_nor2,
2758 
    i1 => netops1414,
2759 
    i0 => rg4_latch14_o_an1);
2760 
  rg4_latch14_nor2 : no2_x4
2761 
    PORT MAP (
2762 
    vss => vss,
2763 
    vdd => vdd,
2764 
    nq => rg4_latch14_o_nor2,
2765 
    i1 => rg4_latch14_o_an2,
2766 
    i0 => data64in(14));
2767 
  rg4_latch15_inv : inv_x2
2768 
    PORT MAP (
2769 
    vss => vss,
2770 
    vdd => vdd,
2771 
    nq => rg4_latch15_o_inv,
2772 
    i => o2_15);
2773 
  rg4_latch15_an1 : a2_x2
2774 
    PORT MAP (
2775 
    vss => vss,
2776 
    vdd => vdd,
2777 
    q => rg4_latch15_o_an1,
2778 
    i1 => en_bufin,
2779 
    i0 => rg4_latch15_o_inv);
2780 
  rg4_latch15_an2 : a2_x2
2781 
    PORT MAP (
2782 
    vss => vss,
2783 
    vdd => vdd,
2784 
    q => rg4_latch15_o_an2,
2785 
    i1 => en_bufin,
2786 
    i0 => o2_15);
2787 
  rg4_latch15_nor1 : no3_x4
2788 
    PORT MAP (
2789 
    vss => vss,
2790 
    vdd => vdd,
2791 
    nq => data64in(15),
2792 
    i2 => rg4_latch15_o_nor2,
2793 
    i1 => netops1414,
2794 
    i0 => rg4_latch15_o_an1);
2795 
  rg4_latch15_nor2 : no2_x4
2796 
    PORT MAP (
2797 
    vss => vss,
2798 
    vdd => vdd,
2799 
    nq => rg4_latch15_o_nor2,
2800 
    i1 => rg4_latch15_o_an2,
2801 
    i0 => data64in(15));
2802 
  dec12_o2_0 : a2_x2
2803 
    PORT MAP (
2804 
    vss => vss,
2805 
    vdd => vdd,
2806 
    q => o2_0,
2807 
    i1 => datain(0),
2808 
    i0 => n_block);
2809 
  dec12_o2_1 : a2_x2
2810 
    PORT MAP (
2811 
    vss => vss,
2812 
    vdd => vdd,
2813 
    q => o2_1,
2814 
    i1 => datain(1),
2815 
    i0 => n_block);
2816 
  dec12_o2_2 : a2_x2
2817 
    PORT MAP (
2818 
    vss => vss,
2819 
    vdd => vdd,
2820 
    q => o2_2,
2821 
    i1 => datain(2),
2822 
    i0 => n_block);
2823 
  dec12_o2_3 : a2_x2
2824 
    PORT MAP (
2825 
    vss => vss,
2826 
    vdd => vdd,
2827 
    q => o2_3,
2828 
    i1 => datain(3),
2829 
    i0 => n_block);
2830 
  dec12_o2_4 : a2_x2
2831 
    PORT MAP (
2832 
    vss => vss,
2833 
    vdd => vdd,
2834 
    q => o2_4,
2835 
    i1 => datain(4),
2836 
    i0 => n_block);
2837 
  dec12_o2_5 : a2_x2
2838 
    PORT MAP (
2839 
    vss => vss,
2840 
    vdd => vdd,
2841 
    q => o2_5,
2842 
    i1 => datain(5),
2843 
    i0 => n_block);
2844 
  dec12_o2_6 : a2_x2
2845 
    PORT MAP (
2846 
    vss => vss,
2847 
    vdd => vdd,
2848 
    q => o2_6,
2849 
    i1 => datain(6),
2850 
    i0 => n_block);
2851 
  dec12_o2_7 : a2_x2
2852 
    PORT MAP (
2853 
    vss => vss,
2854 
    vdd => vdd,
2855 
    q => o2_7,
2856 
    i1 => datain(7),
2857 
    i0 => n_block);
2858 
  dec12_o2_8 : a2_x2
2859 
    PORT MAP (
2860 
    vss => vss,
2861 
    vdd => vdd,
2862 
    q => o2_8,
2863 
    i1 => datain(8),
2864 
    i0 => n_block);
2865 
  dec12_o2_9 : a2_x2
2866 
    PORT MAP (
2867 
    vss => vss,
2868 
    vdd => vdd,
2869 
    q => o2_9,
2870 
    i1 => datain(9),
2871 
    i0 => n_block);
2872 
  dec12_o2_10 : a2_x2
2873 
    PORT MAP (
2874 
    vss => vss,
2875 
    vdd => vdd,
2876 
    q => o2_10,
2877 
    i1 => datain(10),
2878 
    i0 => n_block);
2879 
  dec12_o2_11 : a2_x2
2880 
    PORT MAP (
2881 
    vss => vss,
2882 
    vdd => vdd,
2883 
    q => o2_11,
2884 
    i1 => datain(11),
2885 
    i0 => n_block);
2886 
  dec12_o2_12 : a2_x2
2887 
    PORT MAP (
2888 
    vss => vss,
2889 
    vdd => vdd,
2890 
    q => o2_12,
2891 
    i1 => datain(12),
2892 
    i0 => n_block);
2893 
  dec12_o2_13 : a2_x2
2894 
    PORT MAP (
2895 
    vss => vss,
2896 
    vdd => vdd,
2897 
    q => o2_13,
2898 
    i1 => datain(13),
2899 
    i0 => n_block);
2900 
  dec12_o2_14 : a2_x2
2901 
    PORT MAP (
2902 
    vss => vss,
2903 
    vdd => vdd,
2904 
    q => o2_14,
2905 
    i1 => datain(14),
2906 
    i0 => n_block);
2907 
  dec12_o2_15 : a2_x2
2908 
    PORT MAP (
2909 
    vss => vss,
2910 
    vdd => vdd,
2911 
    q => o2_15,
2912 
    i1 => datain(15),
2913 
    i0 => n_block);
2914 
  dec12_o2_16 : a2_x2
2915 
    PORT MAP (
2916 
    vss => vss,
2917 
    vdd => vdd,
2918 
    q => o2_16,
2919 
    i1 => datain(16),
2920 
    i0 => n_block);
2921 
  dec12_o2_17 : a2_x2
2922 
    PORT MAP (
2923 
    vss => vss,
2924 
    vdd => vdd,
2925 
    q => o2_17,
2926 
    i1 => datain(17),
2927 
    i0 => n_block);
2928 
  dec12_o2_18 : a2_x2
2929 
    PORT MAP (
2930 
    vss => vss,
2931 
    vdd => vdd,
2932 
    q => o2_18,
2933 
    i1 => datain(18),
2934 
    i0 => n_block);
2935 
  dec12_o2_19 : a2_x2
2936 
    PORT MAP (
2937 
    vss => vss,
2938 
    vdd => vdd,
2939 
    q => o2_19,
2940 
    i1 => datain(19),
2941 
    i0 => n_block);
2942 
  dec12_o2_20 : a2_x2
2943 
    PORT MAP (
2944 
    vss => vss,
2945 
    vdd => vdd,
2946 
    q => o2_20,
2947 
    i1 => datain(20),
2948 
    i0 => n_block);
2949 
  dec12_o2_21 : a2_x2
2950 
    PORT MAP (
2951 
    vss => vss,
2952 
    vdd => vdd,
2953 
    q => o2_21,
2954 
    i1 => datain(21),
2955 
    i0 => n_block);
2956 
  dec12_o2_22 : a2_x2
2957 
    PORT MAP (
2958 
    vss => vss,
2959 
    vdd => vdd,
2960 
    q => o2_22,
2961 
    i1 => datain(22),
2962 
    i0 => n_block);
2963 
  dec12_o2_23 : a2_x2
2964 
    PORT MAP (
2965 
    vss => vss,
2966 
    vdd => vdd,
2967 
    q => o2_23,
2968 
    i1 => datain(23),
2969 
    i0 => n_block);
2970 
  dec12_o2_24 : a2_x2
2971 
    PORT MAP (
2972 
    vss => vss,
2973 
    vdd => vdd,
2974 
    q => o2_24,
2975 
    i1 => datain(24),
2976 
    i0 => n_block);
2977 
  dec12_o2_25 : a2_x2
2978 
    PORT MAP (
2979 
    vss => vss,
2980 
    vdd => vdd,
2981 
    q => o2_25,
2982 
    i1 => datain(25),
2983 
    i0 => n_block);
2984 
  dec12_o2_26 : a2_x2
2985 
    PORT MAP (
2986 
    vss => vss,
2987 
    vdd => vdd,
2988 
    q => o2_26,
2989 
    i1 => datain(26),
2990 
    i0 => n_block);
2991 
  dec12_o2_27 : a2_x2
2992 
    PORT MAP (
2993 
    vss => vss,
2994 
    vdd => vdd,
2995 
    q => o2_27,
2996 
    i1 => datain(27),
2997 
    i0 => n_block);
2998 
  dec12_o2_28 : a2_x2
2999 
    PORT MAP (
3000 
    vss => vss,
3001 
    vdd => vdd,
3002 
    q => o2_28,
3003 
    i1 => datain(28),
3004 
    i0 => n_block);
3005 
  dec12_o2_29 : a2_x2
3006 
    PORT MAP (
3007 
    vss => vss,
3008 
    vdd => vdd,
3009 
    q => o2_29,
3010 
    i1 => datain(29),
3011 
    i0 => n_block);
3012 
  dec12_o2_30 : a2_x2
3013 
    PORT MAP (
3014 
    vss => vss,
3015 
    vdd => vdd,
3016 
    q => o2_30,
3017 
    i1 => datain(30),
3018 
    i0 => n_block);
3019 
  dec12_o2_31 : a2_x2
3020 
    PORT MAP (
3021 
    vss => vss,
3022 
    vdd => vdd,
3023 
    q => o2_31,
3024 
    i1 => datain(31),
3025 
    i0 => n_block);
3026 
  dec12_o1_0 : a2_x2
3027 
    PORT MAP (
3028 
    vss => vss,
3029 
    vdd => vdd,
3030 
    q => o1_0,
3031 
    i1 => dec12_auxsc1,
3032 
    i0 => datain(0));
3033 
  dec12_o1_1 : a2_x2
3034 
    PORT MAP (
3035 
    vss => vss,
3036 
    vdd => vdd,
3037 
    q => o1_1,
3038 
    i1 => dec12_auxsc1,
3039 
    i0 => datain(1));
3040 
  dec12_o1_2 : a2_x2
3041 
    PORT MAP (
3042 
    vss => vss,
3043 
    vdd => vdd,
3044 
    q => o1_2,
3045 
    i1 => dec12_auxsc1,
3046 
    i0 => datain(2));
3047 
  dec12_o1_3 : a2_x2
3048 
    PORT MAP (
3049 
    vss => vss,
3050 
    vdd => vdd,
3051 
    q => o1_3,
3052 
    i1 => dec12_auxsc1,
3053 
    i0 => datain(3));
3054 
  dec12_o1_4 : a2_x2
3055 
    PORT MAP (
3056 
    vss => vss,
3057 
    vdd => vdd,
3058 
    q => o1_4,
3059 
    i1 => dec12_auxsc1,
3060 
    i0 => datain(4));
3061 
  dec12_o1_5 : a2_x2
3062 
    PORT MAP (
3063 
    vss => vss,
3064 
    vdd => vdd,
3065 
    q => o1_5,
3066 
    i1 => dec12_auxsc1,
3067 
    i0 => datain(5));
3068 
  dec12_o1_6 : a2_x2
3069 
    PORT MAP (
3070 
    vss => vss,
3071 
    vdd => vdd,
3072 
    q => o1_6,
3073 
    i1 => dec12_auxsc1,
3074 
    i0 => datain(6));
3075 
  dec12_o1_7 : a2_x2
3076 
    PORT MAP (
3077 
    vss => vss,
3078 
    vdd => vdd,
3079 
    q => o1_7,
3080 
    i1 => dec12_auxsc1,
3081 
    i0 => datain(7));
3082 
  dec12_o1_8 : a2_x2
3083 
    PORT MAP (
3084 
    vss => vss,
3085 
    vdd => vdd,
3086 
    q => o1_8,
3087 
    i1 => dec12_auxsc1,
3088 
    i0 => datain(8));
3089 
  dec12_o1_9 : a2_x2
3090 
    PORT MAP (
3091 
    vss => vss,
3092 
    vdd => vdd,
3093 
    q => o1_9,
3094 
    i1 => dec12_auxsc1,
3095 
    i0 => datain(9));
3096 
  dec12_o1_10 : a2_x2
3097 
    PORT MAP (
3098 
    vss => vss,
3099 
    vdd => vdd,
3100 
    q => o1_10,
3101 
    i1 => dec12_auxsc1,
3102 
    i0 => datain(10));
3103 
  dec12_o1_11 : a2_x2
3104 
    PORT MAP (
3105 
    vss => vss,
3106 
    vdd => vdd,
3107 
    q => o1_11,
3108 
    i1 => dec12_auxsc1,
3109 
    i0 => datain(11));
3110 
  dec12_o1_12 : a2_x2
3111 
    PORT MAP (
3112 
    vss => vss,
3113 
    vdd => vdd,
3114 
    q => o1_12,
3115 
    i1 => dec12_auxsc1,
3116 
    i0 => datain(12));
3117 
  dec12_o1_13 : a2_x2
3118 
    PORT MAP (
3119 
    vss => vss,
3120 
    vdd => vdd,
3121 
    q => o1_13,
3122 
    i1 => dec12_auxsc1,
3123 
    i0 => datain(13));
3124 
  dec12_o1_14 : a2_x2
3125 
    PORT MAP (
3126 
    vss => vss,
3127 
    vdd => vdd,
3128 
    q => o1_14,
3129 
    i1 => dec12_auxsc1,
3130 
    i0 => datain(14));
3131 
  dec12_o1_15 : a2_x2
3132 
    PORT MAP (
3133 
    vss => vss,
3134 
    vdd => vdd,
3135 
    q => o1_15,
3136 
    i1 => dec12_auxsc1,
3137 
    i0 => datain(15));
3138 
  dec12_o1_16 : a2_x2
3139 
    PORT MAP (
3140 
    vss => vss,
3141 
    vdd => vdd,
3142 
    q => o1_16,
3143 
    i1 => dec12_auxsc1,
3144 
    i0 => datain(16));
3145 
  dec12_o1_17 : a2_x2
3146 
    PORT MAP (
3147 
    vss => vss,
3148 
    vdd => vdd,
3149 
    q => o1_17,
3150 
    i1 => dec12_auxsc1,
3151 
    i0 => datain(17));
3152 
  dec12_o1_18 : a2_x2
3153 
    PORT MAP (
3154 
    vss => vss,
3155 
    vdd => vdd,
3156 
    q => o1_18,
3157 
    i1 => dec12_auxsc1,
3158 
    i0 => datain(18));
3159 
  dec12_o1_19 : a2_x2
3160 
    PORT MAP (
3161 
    vss => vss,
3162 
    vdd => vdd,
3163 
    q => o1_19,
3164 
    i1 => dec12_auxsc1,
3165 
    i0 => datain(19));
3166 
  dec12_o1_20 : a2_x2
3167 
    PORT MAP (
3168 
    vss => vss,
3169 
    vdd => vdd,
3170 
    q => o1_20,
3171 
    i1 => dec12_auxsc1,
3172 
    i0 => datain(20));
3173 
  dec12_o1_21 : a2_x2
3174 
    PORT MAP (
3175 
    vss => vss,
3176 
    vdd => vdd,
3177 
    q => o1_21,
3178 
    i1 => dec12_auxsc1,
3179 
    i0 => datain(21));
3180 
  dec12_o1_22 : a2_x2
3181 
    PORT MAP (
3182 
    vss => vss,
3183 
    vdd => vdd,
3184 
    q => o1_22,
3185 
    i1 => dec12_auxsc1,
3186 
    i0 => datain(22));
3187 
  dec12_o1_23 : a2_x2
3188 
    PORT MAP (
3189 
    vss => vss,
3190 
    vdd => vdd,
3191 
    q => o1_23,
3192 
    i1 => dec12_auxsc1,
3193 
    i0 => datain(23));
3194 
  dec12_o1_24 : a2_x2
3195 
    PORT MAP (
3196 
    vss => vss,
3197 
    vdd => vdd,
3198 
    q => o1_24,
3199 
    i1 => dec12_auxsc1,
3200 
    i0 => datain(24));
3201 
  dec12_o1_25 : a2_x2
3202 
    PORT MAP (
3203 
    vss => vss,
3204 
    vdd => vdd,
3205 
    q => o1_25,
3206 
    i1 => dec12_auxsc1,
3207 
    i0 => datain(25));
3208 
  dec12_o1_26 : a2_x2
3209 
    PORT MAP (
3210 
    vss => vss,
3211 
    vdd => vdd,
3212 
    q => o1_26,
3213 
    i1 => dec12_auxsc1,
3214 
    i0 => datain(26));
3215 
  dec12_o1_27 : a2_x2
3216 
    PORT MAP (
3217 
    vss => vss,
3218 
    vdd => vdd,
3219 
    q => o1_27,
3220 
    i1 => dec12_auxsc1,
3221 
    i0 => datain(27));
3222 
  dec12_o1_28 : a2_x2
3223 
    PORT MAP (
3224 
    vss => vss,
3225 
    vdd => vdd,
3226 
    q => o1_28,
3227 
    i1 => dec12_auxsc1,
3228 
    i0 => datain(28));
3229 
  dec12_o1_29 : a2_x2
3230 
    PORT MAP (
3231 
    vss => vss,
3232 
    vdd => vdd,
3233 
    q => o1_29,
3234 
    i1 => dec12_auxsc1,
3235 
    i0 => datain(29));
3236 
  dec12_o1_30 : a2_x2
3237 
    PORT MAP (
3238 
    vss => vss,
3239 
    vdd => vdd,
3240 
    q => o1_30,
3241 
    i1 => dec12_auxsc1,
3242 
    i0 => datain(30));
3243 
  dec12_o1_31 : a2_x2
3244 
    PORT MAP (
3245 
    vss => vss,
3246 
    vdd => vdd,
3247 
    q => o1_31,
3248 
    i1 => dec12_auxsc1,
3249 
    i0 => datain(31));
3250 
  dec12_auxsc1 : inv_x1
3251 
    PORT MAP (
3252 
    vss => vss,
3253 
    vdd => vdd,
3254 
    nq => dec12_auxsc1,
3255 
    i => n_block);
3256 
  ctrl_dtin_n_block : no4_x1
3257 
    PORT MAP (
3258 
    vss => vss,
3259 
    vdd => vdd,
3260 
    nq => n_block,
3261 
    i3 => ctrl_dtin_auxreg3,
3262 
    i2 => ctrl_dtin_auxsc22,
3263 
    i1 => ctrl_dtin_auxsc45,
3264 
    i0 => netops1414);
3265 
  ctrl_dtin_req_dt : ao22_x2
3266 
    PORT MAP (
3267 
    vss => vss,
3268 
    vdd => vdd,
3269 
    q => req_dt,
3270 
    i2 => ctrl_dtin_auxsc42,
3271 
    i1 => ctrl_dtin_auxsc18,
3272 
    i0 => ctrl_dtin_auxsc36);
3273 
  ctrl_dtin_auxsc3 : a2_x2
3274 
    PORT MAP (
3275 
    vss => vss,
3276 
    vdd => vdd,
3277 
    q => ctrl_dtin_auxsc3,
3278 
    i1 => ctrl_dtin_auxsc2,
3279 
    i0 => ctrl_dtin_auxsc1);
3280 
  ctrl_dtin_auxsc2 : xr2_x1
3281 
    PORT MAP (
3282 
    vss => vss,
3283 
    vdd => vdd,
3284 
    q => ctrl_dtin_auxsc2,
3285 
    i1 => ctrl_dtin_auxreg3,
3286 
    i0 => ctrl_dtin_auxreg1);
3287 
  ctrl_dtin_auxsc42 : o3_x2
3288 
    PORT MAP (
3289 
    vss => vss,
3290 
    vdd => vdd,
3291 
    q => ctrl_dtin_auxsc42,
3292 
    i2 => ctrl_dtin_auxsc41,
3293 
    i1 => ctrl_dtin_auxreg3,
3294 
    i0 => netops1414);
3295 
  ctrl_dtin_auxsc41 : nao22_x1
3296 
    PORT MAP (
3297 
    vss => vss,
3298 
    vdd => vdd,
3299 
    nq => ctrl_dtin_auxsc41,
3300 
    i2 => ctrl_dtin_auxsc40,
3301 
    i1 => ctrl_dtin_auxsc37,
3302 
    i0 => dt_sended);
3303 
  ctrl_dtin_auxsc40 : inv_x1
3304 
    PORT MAP (
3305 
    vss => vss,
3306 
    vdd => vdd,
3307 
    nq => ctrl_dtin_auxsc40,
3308 
    i => ctrl_dtin_auxsc39);
3309 
  ctrl_dtin_auxsc39 : an12_x1
3310 
    PORT MAP (
3311 
    vss => vss,
3312 
    vdd => vdd,
3313 
    q => ctrl_dtin_auxsc39,
3314 
    i1 => ctrl_dtin_auxreg2,
3315 
    i0 => ctrl_dtin_auxsc38);
3316 
  ctrl_dtin_auxsc38 : inv_x1
3317 
    PORT MAP (
3318 
    vss => vss,
3319 
    vdd => vdd,
3320 
    nq => ctrl_dtin_auxsc38,
3321 
    i => emp_buf);
3322 
  ctrl_dtin_auxsc37 : a2_x2
3323 
    PORT MAP (
3324 
    vss => vss,
3325 
    vdd => vdd,
3326 
    q => ctrl_dtin_auxsc37,
3327 
    i1 => ctrl_dtin_auxreg2,
3328 
    i0 => ctrl_dtin_auxsc22);
3329 
  ctrl_dtin_auxsc36 : o2_x2
3330 
    PORT MAP (
3331 
    vss => vss,
3332 
    vdd => vdd,
3333 
    q => ctrl_dtin_auxsc36,
3334 
    i1 => ctrl_dtin_auxsc22,
3335 
    i0 => netops1414);
3336 
  ctrl_dtin_auxsc45 : inv_x1
3337 
    PORT MAP (
3338 
    vss => vss,
3339 
    vdd => vdd,
3340 
    nq => ctrl_dtin_auxsc45,
3341 
    i => dt_sended);
3342 
  ctrl_dtin_auxsc21 : na2_x1
3343 
    PORT MAP (
3344 
    vss => vss,
3345 
    vdd => vdd,
3346 
    nq => ctrl_dtin_auxsc21,
3347 
    i1 => ctrl_dtin_auxreg2,
3348 
    i0 => ctrl_dtin_auxsc22);
3349 
  ctrl_dtin_auxsc22 : inv_x1
3350 
    PORT MAP (
3351 
    vss => vss,
3352 
    vdd => vdd,
3353 
    nq => ctrl_dtin_auxsc22,
3354 
    i => ctrl_dtin_auxreg1);
3355 
  ctrl_dtin_auxsc18 : inv_x1
3356 
    PORT MAP (
3357 
    vss => vss,
3358 
    vdd => vdd,
3359 
    nq => ctrl_dtin_auxsc18,
3360 
    i => ctrl_dtin_auxreg3);
3361 
  ctrl_dtin_auxsc16 : no3_x1
3362 
    PORT MAP (
3363 
    vss => vss,
3364 
    vdd => vdd,
3365 
    nq => ctrl_dtin_auxsc16,
3366 
    i2 => ctrl_dtin_auxsc15,
3367 
    i1 => ctrl_dtin_auxsc14,
3368 
    i0 => netops1414);
3369 
  ctrl_dtin_auxsc15 : o2_x2
3370 
    PORT MAP (
3371 
    vss => vss,
3372 
    vdd => vdd,
3373 
    q => ctrl_dtin_auxsc15,
3374 
    i1 => emp_buf,
3375 
    i0 => ctrl_dtin_auxreg3);
3376 
  ctrl_dtin_auxsc14 : inv_x1
3377 
    PORT MAP (
3378 
    vss => vss,
3379 
    vdd => vdd,
3380 
    nq => ctrl_dtin_auxsc14,
3381 
    i => ctrl_dtin_auxreg2);
3382 
  ctrl_dtin_auxsc13 : a2_x2
3383 
    PORT MAP (
3384 
    vss => vss,
3385 
    vdd => vdd,
3386 
    q => ctrl_dtin_auxsc13,
3387 
    i1 => ctrl_dtin_auxsc1,
3388 
    i0 => ctrl_dtin_auxreg3);
3389 
  ctrl_dtin_auxsc1 : inv_x1
3390 
    PORT MAP (
3391 
    vss => vss,
3392 
    vdd => vdd,
3393 
    nq => ctrl_dtin_auxsc1,
3394 
    i => netops1414);
3395 
  ctrl_dtin_auxinit1_a : oa22_x2
3396 
    PORT MAP (
3397 
    vss => vss,
3398 
    vdd => vdd,
3399 
    q => dt_ready,
3400 
    i2 => ctrl_dtin_auxsc16,
3401 
    i1 => ctrl_dtin_auxreg1,
3402 
    i0 => ctrl_dtin_auxsc13);
3403 
  ctrl_dtin_auxinit2_a : a4_x2
3404 
    PORT MAP (
3405 
    vss => vss,
3406 
    vdd => vdd,
3407 
    q => en_bufin,
3408 
    i3 => ctrl_dtin_auxsc21,
3409 
    i2 => ctrl_dtin_auxsc1,
3410 
    i1 => ctrl_dtin_auxsc18,
3411 
    i0 => dt_sended);
3412 
  ctrl_dtin_current_state_0 : sff1_x4
3413 
    PORT MAP (
3414 
    vss => vss,
3415 
    vdd => vdd,
3416 
    q => ctrl_dtin_auxreg1,
3417 
    i => ctrl_dtin_auxsc3,
3418 
    ck => clk);
3419 
  ctrl_dtin_current_state_1 : sff1_x4
3420 
    PORT MAP (
3421 
    vss => vss,
3422 
    vdd => vdd,
3423 
    q => ctrl_dtin_auxreg2,
3424 
    i => dt_ready,
3425 
    ck => clk);
3426 
  ctrl_dtin_current_state_2 : sff1_x4
3427 
    PORT MAP (
3428 
    vss => vss,
3429 
    vdd => vdd,
3430 
    q => ctrl_dtin_auxreg3,
3431 
    i => en_bufin,
3432 
    ck => clk);
3433 
  inv : inv_x1
3434 
    PORT MAP (
3435 
    vss => vss,
3436 
    vdd => vdd,
3437 
    nq => o_inv,
3438 
    i => n_block);
3439 
  an1 : a2_x2
3440 
    PORT MAP (
3441 
    vss => vss,
3442 
    vdd => vdd,
3443 
    q => en_bufin_c,
3444 
    i1 => en_bufin,
3445 
    i0 => o_inv);
3446 
  netopi1414 : buf_x2
3447 
    PORT MAP (
3448 
    vss => vss,
3449 
    vdd => vdd,
3450 
    q => netops1414,
3451 
    i => rst);
3452 
 
3453 
end VST;

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