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[/] [structural_vhdl/] [trunk/] [inout_port/] [in_key.vst] - Blame information for rev 4

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-- VHDL structural description generated from `in_key`
--              date : Sat Sep  1 20:10:41 2001
 
 
-- Entity Declaration
 
ENTITY in_key IS
  PORT (
  clk : in BIT; -- clk
  rst : in BIT; -- rst
  key_sended : in BIT;  -- key_sended
  en_bufin : inout BIT; -- en_bufin
  req_key : out BIT;    -- req_key
  ikey_ready : out BIT; -- ikey_ready
  n_block : out BIT;    -- n_block
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END in_key;
 
-- Architecture Declaration
 
ARCHITECTURE VST OF in_key IS
  COMPONENT no4_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    i3 : in BIT;        -- i3
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT o3_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT na3_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT o2_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT no3_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT nao22_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT a2_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT na2_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT inv_x1
    port (
    i : in BIT; -- i
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT ao22_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT a4_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    i3 : in BIT;        -- i3
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT sff1_x4
    port (
    ck : in BIT;        -- ck
    i : in BIT; -- i
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  SIGNAL auxsc2 : BIT;  -- auxsc2
  SIGNAL auxsc1 : BIT;  -- auxsc1
  SIGNAL auxsc10 : BIT; -- auxsc10
  SIGNAL auxsc30 : BIT; -- auxsc30
  SIGNAL auxsc24 : BIT; -- auxsc24
  SIGNAL auxsc32 : BIT; -- auxsc32
  SIGNAL auxsc36 : BIT; -- auxsc36
  SIGNAL auxsc11 : BIT; -- auxsc11
  SIGNAL auxsc12 : BIT; -- auxsc12
  SIGNAL auxsc13 : BIT; -- auxsc13
  SIGNAL auxsc8 : BIT;  -- auxsc8
  SIGNAL auxsc23 : BIT; -- auxsc23
  SIGNAL auxsc25 : BIT; -- auxsc25
  SIGNAL auxsc26 : BIT; -- auxsc26
  SIGNAL auxsc21 : BIT; -- auxsc21
  SIGNAL auxreg3 : BIT; -- auxreg3
  SIGNAL auxreg2 : BIT; -- auxreg2
  SIGNAL auxreg1 : BIT; -- auxreg1
 
BEGIN
 
  ikey_ready : no4_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => ikey_ready,
    i3 => auxreg3,
    i2 => auxsc24,
    i1 => auxsc2,
    i0 => rst);
  req_key : o3_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => req_key,
    i2 => auxreg3,
    i1 => auxsc36,
    i0 => rst);
  auxsc21 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc21,
    i2 => auxsc26,
    i1 => auxreg1,
    i0 => auxsc23);
  auxsc26 : o3_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc26,
    i2 => auxsc25,
    i1 => auxsc10,
    i0 => rst);
  auxsc25 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc25,
    i => auxsc24);
  auxsc23 : na3_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc23,
    i2 => auxsc1,
    i1 => auxsc10,
    i0 => auxreg2);
  auxsc8 : o2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc8,
    i1 => auxsc13,
    i0 => auxsc11);
  auxsc13 : no3_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc13,
    i2 => auxsc12,
    i1 => auxsc10,
    i0 => auxreg2);
  auxsc12 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc12,
    i => auxsc2);
  auxsc11 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc11,
    i2 => auxsc1,
    i1 => auxsc2,
    i0 => auxreg3);
  auxsc36 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc36,
    i1 => auxsc30,
    i0 => auxsc32);
  auxsc32 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc32,
    i => key_sended);
  auxsc24 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc24,
    i => auxreg2);
  auxsc30 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc30,
    i1 => auxreg2,
    i0 => auxreg1);
  auxsc10 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc10,
    i => auxreg3);
  auxsc1 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc1,
    i => rst);
  auxsc2 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc2,
    i => auxreg1);
  aux6_a : ao22_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => n_block,
    i2 => auxsc1,
    i1 => auxsc2,
    i0 => auxreg3);
  auxinit1_a : a4_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => en_bufin,
    i3 => auxsc30,
    i2 => auxsc1,
    i1 => auxsc10,
    i0 => key_sended);
  current_state_0 : sff1_x4
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxreg1,
    i => auxsc8,
    ck => clk);
  current_state_1 : sff1_x4
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxreg2,
    i => auxsc21,
    ck => clk);
  current_state_2 : sff1_x4
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxreg3,
    i => en_bufin,
    ck => clk);
 
end VST;

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Subversion Repositories structural_vhdl

[/] [structural_vhdl/] [trunk/] [inout_port/] [in_key.vst] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	marta	-- VHDL structural description generated from `in_key`
2			`-- date : Sat Sep 1 20:10:41 2001`
3
4
5			`-- Entity Declaration`
6
7			`ENTITY in_key IS`
8			`PORT (`
9			`clk : in BIT; -- clk`
10			`rst : in BIT; -- rst`
11			`key_sended : in BIT; -- key_sended`
12			`en_bufin : inout BIT; -- en_bufin`
13			`req_key : out BIT; -- req_key`
14			`ikey_ready : out BIT; -- ikey_ready`
15			`n_block : out BIT; -- n_block`
16			`vdd : in BIT; -- vdd`
17			`vss : in BIT -- vss`
18			`);`
19			`END in_key;`
20
21			`-- Architecture Declaration`
22
23			`ARCHITECTURE VST OF in_key IS`
24			`COMPONENT no4_x1`
25			`port (`
26			`i0 : in BIT; -- i0`
27			`i1 : in BIT; -- i1`
28			`i2 : in BIT; -- i2`
29			`i3 : in BIT; -- i3`
30			`nq : out BIT; -- nq`
31			`vdd : in BIT; -- vdd`
32			`vss : in BIT -- vss`
33			`);`
34			`END COMPONENT;`
35
36			`COMPONENT o3_x2`
37			`port (`
38			`i0 : in BIT; -- i0`
39			`i1 : in BIT; -- i1`
40			`i2 : in BIT; -- i2`
41			`q : out BIT; -- q`
42			`vdd : in BIT; -- vdd`
43			`vss : in BIT -- vss`
44			`);`
45			`END COMPONENT;`
46
47			`COMPONENT na3_x1`
48			`port (`
49			`i0 : in BIT; -- i0`
50			`i1 : in BIT; -- i1`
51			`i2 : in BIT; -- i2`
52			`nq : out BIT; -- nq`
53			`vdd : in BIT; -- vdd`
54			`vss : in BIT -- vss`
55			`);`
56			`END COMPONENT;`
57
58			`COMPONENT o2_x2`
59			`port (`
60			`i0 : in BIT; -- i0`
61			`i1 : in BIT; -- i1`
62			`q : out BIT; -- q`
63			`vdd : in BIT; -- vdd`
64			`vss : in BIT -- vss`
65			`);`
66			`END COMPONENT;`
67
68			`COMPONENT no3_x1`
69			`port (`
70			`i0 : in BIT; -- i0`
71			`i1 : in BIT; -- i1`
72			`i2 : in BIT; -- i2`
73			`nq : out BIT; -- nq`
74			`vdd : in BIT; -- vdd`
75			`vss : in BIT -- vss`
76			`);`
77			`END COMPONENT;`
78
79			`COMPONENT nao22_x1`
80			`port (`
81			`i0 : in BIT; -- i0`
82			`i1 : in BIT; -- i1`
83			`i2 : in BIT; -- i2`
84			`nq : out BIT; -- nq`
85			`vdd : in BIT; -- vdd`
86			`vss : in BIT -- vss`
87			`);`
88			`END COMPONENT;`
89
90			`COMPONENT a2_x2`
91			`port (`
92			`i0 : in BIT; -- i0`
93			`i1 : in BIT; -- i1`
94			`q : out BIT; -- q`
95			`vdd : in BIT; -- vdd`
96			`vss : in BIT -- vss`
97			`);`
98			`END COMPONENT;`
99
100			`COMPONENT na2_x1`
101			`port (`
102			`i0 : in BIT; -- i0`
103			`i1 : in BIT; -- i1`
104			`nq : out BIT; -- nq`
105			`vdd : in BIT; -- vdd`
106			`vss : in BIT -- vss`
107			`);`
108			`END COMPONENT;`
109
110			`COMPONENT inv_x1`
111			`port (`
112			`i : in BIT; -- i`
113			`nq : out BIT; -- nq`
114			`vdd : in BIT; -- vdd`
115			`vss : in BIT -- vss`
116			`);`
117			`END COMPONENT;`
118
119			`COMPONENT ao22_x2`
120			`port (`
121			`i0 : in BIT; -- i0`
122			`i1 : in BIT; -- i1`
123			`i2 : in BIT; -- i2`
124			`q : out BIT; -- q`
125			`vdd : in BIT; -- vdd`
126			`vss : in BIT -- vss`
127			`);`
128			`END COMPONENT;`
129
130			`COMPONENT a4_x2`
131			`port (`
132			`i0 : in BIT; -- i0`
133			`i1 : in BIT; -- i1`
134			`i2 : in BIT; -- i2`
135			`i3 : in BIT; -- i3`
136			`q : out BIT; -- q`
137			`vdd : in BIT; -- vdd`
138			`vss : in BIT -- vss`
139			`);`
140			`END COMPONENT;`
141
142			`COMPONENT sff1_x4`
143			`port (`
144			`ck : in BIT; -- ck`
145			`i : in BIT; -- i`
146			`q : out BIT; -- q`
147			`vdd : in BIT; -- vdd`
148			`vss : in BIT -- vss`
149			`);`
150			`END COMPONENT;`
151
152			`SIGNAL auxsc2 : BIT; -- auxsc2`
153			`SIGNAL auxsc1 : BIT; -- auxsc1`
154			`SIGNAL auxsc10 : BIT; -- auxsc10`
155			`SIGNAL auxsc30 : BIT; -- auxsc30`
156			`SIGNAL auxsc24 : BIT; -- auxsc24`
157			`SIGNAL auxsc32 : BIT; -- auxsc32`
158			`SIGNAL auxsc36 : BIT; -- auxsc36`
159			`SIGNAL auxsc11 : BIT; -- auxsc11`
160			`SIGNAL auxsc12 : BIT; -- auxsc12`
161			`SIGNAL auxsc13 : BIT; -- auxsc13`
162			`SIGNAL auxsc8 : BIT; -- auxsc8`
163			`SIGNAL auxsc23 : BIT; -- auxsc23`
164			`SIGNAL auxsc25 : BIT; -- auxsc25`
165			`SIGNAL auxsc26 : BIT; -- auxsc26`
166			`SIGNAL auxsc21 : BIT; -- auxsc21`
167			`SIGNAL auxreg3 : BIT; -- auxreg3`
168			`SIGNAL auxreg2 : BIT; -- auxreg2`
169			`SIGNAL auxreg1 : BIT; -- auxreg1`
170
171			`BEGIN`
172
173			`ikey_ready : no4_x1`
174			`PORT MAP (`
175			`vss => vss,`
176			`vdd => vdd,`
177			`nq => ikey_ready,`
178			`i3 => auxreg3,`
179			`i2 => auxsc24,`
180			`i1 => auxsc2,`
181			`i0 => rst);`
182			`req_key : o3_x2`
183			`PORT MAP (`
184			`vss => vss,`
185			`vdd => vdd,`
186			`q => req_key,`
187			`i2 => auxreg3,`
188			`i1 => auxsc36,`
189			`i0 => rst);`
190			`auxsc21 : nao22_x1`
191			`PORT MAP (`
192			`vss => vss,`
193			`vdd => vdd,`
194			`nq => auxsc21,`
195			`i2 => auxsc26,`
196			`i1 => auxreg1,`
197			`i0 => auxsc23);`
198			`auxsc26 : o3_x2`
199			`PORT MAP (`
200			`vss => vss,`
201			`vdd => vdd,`
202			`q => auxsc26,`
203			`i2 => auxsc25,`
204			`i1 => auxsc10,`
205			`i0 => rst);`
206			`auxsc25 : inv_x1`
207			`PORT MAP (`
208			`vss => vss,`
209			`vdd => vdd,`
210			`nq => auxsc25,`
211			`i => auxsc24);`
212			`auxsc23 : na3_x1`
213			`PORT MAP (`
214			`vss => vss,`
215			`vdd => vdd,`
216			`nq => auxsc23,`
217			`i2 => auxsc1,`
218			`i1 => auxsc10,`
219			`i0 => auxreg2);`
220			`auxsc8 : o2_x2`
221			`PORT MAP (`
222			`vss => vss,`
223			`vdd => vdd,`
224			`q => auxsc8,`
225			`i1 => auxsc13,`
226			`i0 => auxsc11);`
227			`auxsc13 : no3_x1`
228			`PORT MAP (`
229			`vss => vss,`
230			`vdd => vdd,`
231			`nq => auxsc13,`
232			`i2 => auxsc12,`
233			`i1 => auxsc10,`
234			`i0 => auxreg2);`
235			`auxsc12 : inv_x1`
236			`PORT MAP (`
237			`vss => vss,`
238			`vdd => vdd,`
239			`nq => auxsc12,`
240			`i => auxsc2);`
241			`auxsc11 : nao22_x1`
242			`PORT MAP (`
243			`vss => vss,`
244			`vdd => vdd,`
245			`nq => auxsc11,`
246			`i2 => auxsc1,`
247			`i1 => auxsc2,`
248			`i0 => auxreg3);`
249			`auxsc36 : a2_x2`
250			`PORT MAP (`
251			`vss => vss,`
252			`vdd => vdd,`
253			`q => auxsc36,`
254			`i1 => auxsc30,`
255			`i0 => auxsc32);`
256			`auxsc32 : inv_x1`
257			`PORT MAP (`
258			`vss => vss,`
259			`vdd => vdd,`
260			`nq => auxsc32,`
261			`i => key_sended);`
262			`auxsc24 : inv_x1`
263			`PORT MAP (`
264			`vss => vss,`
265			`vdd => vdd,`
266			`nq => auxsc24,`
267			`i => auxreg2);`
268			`auxsc30 : na2_x1`
269			`PORT MAP (`
270			`vss => vss,`
271			`vdd => vdd,`
272			`nq => auxsc30,`
273			`i1 => auxreg2,`
274			`i0 => auxreg1);`
275			`auxsc10 : inv_x1`
276			`PORT MAP (`
277			`vss => vss,`
278			`vdd => vdd,`
279			`nq => auxsc10,`
280			`i => auxreg3);`
281			`auxsc1 : inv_x1`
282			`PORT MAP (`
283			`vss => vss,`
284			`vdd => vdd,`
285			`nq => auxsc1,`
286			`i => rst);`
287			`auxsc2 : inv_x1`
288			`PORT MAP (`
289			`vss => vss,`
290			`vdd => vdd,`
291			`nq => auxsc2,`
292			`i => auxreg1);`
293			`aux6_a : ao22_x2`
294			`PORT MAP (`
295			`vss => vss,`
296			`vdd => vdd,`
297			`q => n_block,`
298			`i2 => auxsc1,`
299			`i1 => auxsc2,`
300			`i0 => auxreg3);`
301			`auxinit1_a : a4_x2`
302			`PORT MAP (`
303			`vss => vss,`
304			`vdd => vdd,`
305			`q => en_bufin,`
306			`i3 => auxsc30,`
307			`i2 => auxsc1,`
308			`i1 => auxsc10,`
309			`i0 => key_sended);`
310			`current_state_0 : sff1_x4`
311			`PORT MAP (`
312			`vss => vss,`
313			`vdd => vdd,`
314			`q => auxreg1,`
315			`i => auxsc8,`
316			`ck => clk);`
317			`current_state_1 : sff1_x4`
318			`PORT MAP (`
319			`vss => vss,`
320			`vdd => vdd,`
321			`q => auxreg2,`
322			`i => auxsc21,`
323			`ck => clk);`
324			`current_state_2 : sff1_x4`
325			`PORT MAP (`
326			`vss => vss,`
327			`vdd => vdd,`
328			`q => auxreg3,`
329			`i => en_bufin,`
330			`ck => clk);`
331
332			`end VST;`