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[/] [structural_vhdl/] [trunk/] [inout_port/] [mux2to1.vst] - Blame information for rev 4

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1 2 marta 
-- VHDL structural description generated from `mux2to1`
2 
--              date : Mon Aug 27 06:31:58 2001
3 
 
4 
 
5 
-- Entity Declaration
6 
 
7 
ENTITY mux2to1 IS
8 
  PORT (
9 
  y : in BIT_VECTOR (63 DOWNTO 0);      -- y
10 
  sel : in BIT; -- sel
11 
  clk : in BIT; -- clk
12 
  rst : in BIT; -- rst
13 
  cp : out BIT_VECTOR (31 DOWNTO 0);    -- cp
14 
  vdd : in BIT; -- vdd
15 
  vss : in BIT  -- vss
16 
  );
17 
END mux2to1;
18 
 
19 
-- Architecture Declaration
20 
 
21 
ARCHITECTURE VST OF mux2to1 IS
22 
  COMPONENT na2_x1
23 
    port (
24 
    i0 : in BIT;        -- i0
25 
    i1 : in BIT;        -- i1
26 
    nq : out BIT;       -- nq
27 
    vdd : in BIT;       -- vdd
28 
    vss : in BIT        -- vss
29 
    );
30 
  END COMPONENT;
31 
 
32 
  COMPONENT o2_x2
33 
    port (
34 
    i0 : in BIT;        -- i0
35 
    i1 : in BIT;        -- i1
36 
    q : out BIT;        -- q
37 
    vdd : in BIT;       -- vdd
38 
    vss : in BIT        -- vss
39 
    );
40 
  END COMPONENT;
41 
 
42 
  COMPONENT a2_x2
43 
    port (
44 
    i0 : in BIT;        -- i0
45 
    i1 : in BIT;        -- i1
46 
    q : out BIT;        -- q
47 
    vdd : in BIT;       -- vdd
48 
    vss : in BIT        -- vss
49 
    );
50 
  END COMPONENT;
51 
 
52 
  COMPONENT nao22_x1
53 
    port (
54 
    i0 : in BIT;        -- i0
55 
    i1 : in BIT;        -- i1
56 
    i2 : in BIT;        -- i2
57 
    nq : out BIT;       -- nq
58 
    vdd : in BIT;       -- vdd
59 
    vss : in BIT        -- vss
60 
    );
61 
  END COMPONENT;
62 
 
63 
  COMPONENT inv_x1
64 
    port (
65 
    i : in BIT; -- i
66 
    nq : out BIT;       -- nq
67 
    vdd : in BIT;       -- vdd
68 
    vss : in BIT        -- vss
69 
    );
70 
  END COMPONENT;
71 
 
72 
  COMPONENT no2_x1
73 
    port (
74 
    i0 : in BIT;        -- i0
75 
    i1 : in BIT;        -- i1
76 
    nq : out BIT;       -- nq
77 
    vdd : in BIT;       -- vdd
78 
    vss : in BIT        -- vss
79 
    );
80 
  END COMPONENT;
81 
 
82 
  COMPONENT sff1_x4
83 
    port (
84 
    ck : in BIT;        -- ck
85 
    i : in BIT; -- i
86 
    q : out BIT;        -- q
87 
    vdd : in BIT;       -- vdd
88 
    vss : in BIT        -- vss
89 
    );
90 
  END COMPONENT;
91 
 
92 
  SIGNAL aux11_a : BIT; -- aux11_a
93 
  SIGNAL auxsc5 : BIT;  -- auxsc5
94 
  SIGNAL auxsc4 : BIT;  -- auxsc4
95 
  SIGNAL auxsc12 : BIT; -- auxsc12
96 
  SIGNAL auxsc1 : BIT;  -- auxsc1
97 
  SIGNAL auxsc13 : BIT; -- auxsc13
98 
  SIGNAL auxsc9 : BIT;  -- auxsc9
99 
  SIGNAL auxsc23 : BIT; -- auxsc23
100 
  SIGNAL auxsc17 : BIT; -- auxsc17
101 
  SIGNAL auxsc24 : BIT; -- auxsc24
102 
  SIGNAL auxsc21 : BIT; -- auxsc21
103 
  SIGNAL auxsc25 : BIT; -- auxsc25
104 
  SIGNAL auxsc31 : BIT; -- auxsc31
105 
  SIGNAL auxsc29 : BIT; -- auxsc29
106 
  SIGNAL auxsc32 : BIT; -- auxsc32
107 
  SIGNAL auxsc38 : BIT; -- auxsc38
108 
  SIGNAL auxsc36 : BIT; -- auxsc36
109 
  SIGNAL auxsc50 : BIT; -- auxsc50
110 
  SIGNAL auxsc39 : BIT; -- auxsc39
111 
  SIGNAL auxsc51 : BIT; -- auxsc51
112 
  SIGNAL auxsc47 : BIT; -- auxsc47
113 
  SIGNAL auxsc52 : BIT; -- auxsc52
114 
  SIGNAL auxsc58 : BIT; -- auxsc58
115 
  SIGNAL auxsc56 : BIT; -- auxsc56
116 
  SIGNAL auxsc59 : BIT; -- auxsc59
117 
  SIGNAL auxsc65 : BIT; -- auxsc65
118 
  SIGNAL auxsc63 : BIT; -- auxsc63
119 
  SIGNAL auxsc66 : BIT; -- auxsc66
120 
  SIGNAL auxsc72 : BIT; -- auxsc72
121 
  SIGNAL auxsc70 : BIT; -- auxsc70
122 
  SIGNAL auxsc84 : BIT; -- auxsc84
123 
  SIGNAL auxsc73 : BIT; -- auxsc73
124 
  SIGNAL auxsc85 : BIT; -- auxsc85
125 
  SIGNAL auxsc81 : BIT; -- auxsc81
126 
  SIGNAL auxsc86 : BIT; -- auxsc86
127 
  SIGNAL auxsc92 : BIT; -- auxsc92
128 
  SIGNAL auxsc90 : BIT; -- auxsc90
129 
  SIGNAL auxsc93 : BIT; -- auxsc93
130 
  SIGNAL auxsc99 : BIT; -- auxsc99
131 
  SIGNAL auxsc97 : BIT; -- auxsc97
132 
  SIGNAL auxsc100 : BIT;        -- auxsc100
133 
  SIGNAL auxsc106 : BIT;        -- auxsc106
134 
  SIGNAL auxsc104 : BIT;        -- auxsc104
135 
  SIGNAL auxsc118 : BIT;        -- auxsc118
136 
  SIGNAL auxsc107 : BIT;        -- auxsc107
137 
  SIGNAL auxsc119 : BIT;        -- auxsc119
138 
  SIGNAL auxsc115 : BIT;        -- auxsc115
139 
  SIGNAL auxsc120 : BIT;        -- auxsc120
140 
  SIGNAL auxsc126 : BIT;        -- auxsc126
141 
  SIGNAL auxsc124 : BIT;        -- auxsc124
142 
  SIGNAL auxsc127 : BIT;        -- auxsc127
143 
  SIGNAL auxsc133 : BIT;        -- auxsc133
144 
  SIGNAL auxsc131 : BIT;        -- auxsc131
145 
  SIGNAL auxsc134 : BIT;        -- auxsc134
146 
  SIGNAL auxsc140 : BIT;        -- auxsc140
147 
  SIGNAL auxsc138 : BIT;        -- auxsc138
148 
  SIGNAL auxsc152 : BIT;        -- auxsc152
149 
  SIGNAL auxsc141 : BIT;        -- auxsc141
150 
  SIGNAL auxsc153 : BIT;        -- auxsc153
151 
  SIGNAL auxsc149 : BIT;        -- auxsc149
152 
  SIGNAL auxsc154 : BIT;        -- auxsc154
153 
  SIGNAL auxsc160 : BIT;        -- auxsc160
154 
  SIGNAL auxsc158 : BIT;        -- auxsc158
155 
  SIGNAL auxsc161 : BIT;        -- auxsc161
156 
  SIGNAL auxsc167 : BIT;        -- auxsc167
157 
  SIGNAL auxsc165 : BIT;        -- auxsc165
158 
  SIGNAL auxsc168 : BIT;        -- auxsc168
159 
  SIGNAL auxsc174 : BIT;        -- auxsc174
160 
  SIGNAL auxsc172 : BIT;        -- auxsc172
161 
  SIGNAL auxsc186 : BIT;        -- auxsc186
162 
  SIGNAL auxsc175 : BIT;        -- auxsc175
163 
  SIGNAL auxsc187 : BIT;        -- auxsc187
164 
  SIGNAL auxsc183 : BIT;        -- auxsc183
165 
  SIGNAL auxsc188 : BIT;        -- auxsc188
166 
  SIGNAL auxsc194 : BIT;        -- auxsc194
167 
  SIGNAL auxsc192 : BIT;        -- auxsc192
168 
  SIGNAL auxsc195 : BIT;        -- auxsc195
169 
  SIGNAL auxsc201 : BIT;        -- auxsc201
170 
  SIGNAL auxsc199 : BIT;        -- auxsc199
171 
  SIGNAL auxsc202 : BIT;        -- auxsc202
172 
  SIGNAL auxsc208 : BIT;        -- auxsc208
173 
  SIGNAL auxsc206 : BIT;        -- auxsc206
174 
  SIGNAL auxsc220 : BIT;        -- auxsc220
175 
  SIGNAL auxsc209 : BIT;        -- auxsc209
176 
  SIGNAL auxsc221 : BIT;        -- auxsc221
177 
  SIGNAL auxsc217 : BIT;        -- auxsc217
178 
  SIGNAL auxsc222 : BIT;        -- auxsc222
179 
  SIGNAL auxsc228 : BIT;        -- auxsc228
180 
  SIGNAL auxsc226 : BIT;        -- auxsc226
181 
  SIGNAL auxsc229 : BIT;        -- auxsc229
182 
  SIGNAL auxsc235 : BIT;        -- auxsc235
183 
  SIGNAL auxsc233 : BIT;        -- auxsc233
184 
  SIGNAL auxsc236 : BIT;        -- auxsc236
185 
  SIGNAL auxsc242 : BIT;        -- auxsc242
186 
  SIGNAL auxsc240 : BIT;        -- auxsc240
187 
  SIGNAL auxsc254 : BIT;        -- auxsc254
188 
  SIGNAL auxsc243 : BIT;        -- auxsc243
189 
  SIGNAL auxsc255 : BIT;        -- auxsc255
190 
  SIGNAL auxsc251 : BIT;        -- auxsc251
191 
  SIGNAL auxsc256 : BIT;        -- auxsc256
192 
  SIGNAL auxsc262 : BIT;        -- auxsc262
193 
  SIGNAL auxsc260 : BIT;        -- auxsc260
194 
  SIGNAL auxsc263 : BIT;        -- auxsc263
195 
  SIGNAL auxsc269 : BIT;        -- auxsc269
196 
  SIGNAL auxsc267 : BIT;        -- auxsc267
197 
  SIGNAL auxsc270 : BIT;        -- auxsc270
198 
  SIGNAL auxsc276 : BIT;        -- auxsc276
199 
  SIGNAL auxsc274 : BIT;        -- auxsc274
200 
  SIGNAL auxreg32 : BIT;        -- auxreg32
201 
  SIGNAL auxreg31 : BIT;        -- auxreg31
202 
  SIGNAL auxreg30 : BIT;        -- auxreg30
203 
  SIGNAL auxreg29 : BIT;        -- auxreg29
204 
  SIGNAL auxreg28 : BIT;        -- auxreg28
205 
  SIGNAL auxreg27 : BIT;        -- auxreg27
206 
  SIGNAL auxreg26 : BIT;        -- auxreg26
207 
  SIGNAL auxreg25 : BIT;        -- auxreg25
208 
  SIGNAL auxreg24 : BIT;        -- auxreg24
209 
  SIGNAL auxreg23 : BIT;        -- auxreg23
210 
  SIGNAL auxreg22 : BIT;        -- auxreg22
211 
  SIGNAL auxreg21 : BIT;        -- auxreg21
212 
  SIGNAL auxreg20 : BIT;        -- auxreg20
213 
  SIGNAL auxreg19 : BIT;        -- auxreg19
214 
  SIGNAL auxreg18 : BIT;        -- auxreg18
215 
  SIGNAL auxreg17 : BIT;        -- auxreg17
216 
  SIGNAL auxreg16 : BIT;        -- auxreg16
217 
  SIGNAL auxreg15 : BIT;        -- auxreg15
218 
  SIGNAL auxreg14 : BIT;        -- auxreg14
219 
  SIGNAL auxreg13 : BIT;        -- auxreg13
220 
  SIGNAL auxreg12 : BIT;        -- auxreg12
221 
  SIGNAL auxreg11 : BIT;        -- auxreg11
222 
  SIGNAL auxreg10 : BIT;        -- auxreg10
223 
  SIGNAL auxreg9 : BIT; -- auxreg9
224 
  SIGNAL auxreg8 : BIT; -- auxreg8
225 
  SIGNAL auxreg7 : BIT; -- auxreg7
226 
  SIGNAL auxreg6 : BIT; -- auxreg6
227 
  SIGNAL auxreg5 : BIT; -- auxreg5
228 
  SIGNAL auxreg4 : BIT; -- auxreg4
229 
  SIGNAL auxreg3 : BIT; -- auxreg3
230 
  SIGNAL auxreg2 : BIT; -- auxreg2
231 
  SIGNAL auxreg1 : BIT; -- auxreg1
232 
 
233 
BEGIN
234 
 
235 
  cp_0 : inv_x1
236 
    PORT MAP (
237 
    vss => vss,
238 
    vdd => vdd,
239 
    nq => cp(0),
240 
    i => auxreg1);
241 
  cp_1 : inv_x1
242 
    PORT MAP (
243 
    vss => vss,
244 
    vdd => vdd,
245 
    nq => cp(1),
246 
    i => auxreg2);
247 
  cp_2 : inv_x1
248 
    PORT MAP (
249 
    vss => vss,
250 
    vdd => vdd,
251 
    nq => cp(2),
252 
    i => auxreg3);
253 
  cp_3 : inv_x1
254 
    PORT MAP (
255 
    vss => vss,
256 
    vdd => vdd,
257 
    nq => cp(3),
258 
    i => auxreg4);
259 
  cp_4 : inv_x1
260 
    PORT MAP (
261 
    vss => vss,
262 
    vdd => vdd,
263 
    nq => cp(4),
264 
    i => auxreg5);
265 
  cp_5 : inv_x1
266 
    PORT MAP (
267 
    vss => vss,
268 
    vdd => vdd,
269 
    nq => cp(5),
270 
    i => auxreg6);
271 
  cp_6 : inv_x1
272 
    PORT MAP (
273 
    vss => vss,
274 
    vdd => vdd,
275 
    nq => cp(6),
276 
    i => auxreg7);
277 
  cp_7 : inv_x1
278 
    PORT MAP (
279 
    vss => vss,
280 
    vdd => vdd,
281 
    nq => cp(7),
282 
    i => auxreg8);
283 
  cp_8 : inv_x1
284 
    PORT MAP (
285 
    vss => vss,
286 
    vdd => vdd,
287 
    nq => cp(8),
288 
    i => auxreg9);
289 
  cp_9 : inv_x1
290 
    PORT MAP (
291 
    vss => vss,
292 
    vdd => vdd,
293 
    nq => cp(9),
294 
    i => auxreg10);
295 
  cp_10 : inv_x1
296 
    PORT MAP (
297 
    vss => vss,
298 
    vdd => vdd,
299 
    nq => cp(10),
300 
    i => auxreg11);
301 
  cp_11 : inv_x1
302 
    PORT MAP (
303 
    vss => vss,
304 
    vdd => vdd,
305 
    nq => cp(11),
306 
    i => auxreg12);
307 
  cp_12 : inv_x1
308 
    PORT MAP (
309 
    vss => vss,
310 
    vdd => vdd,
311 
    nq => cp(12),
312 
    i => auxreg13);
313 
  cp_13 : inv_x1
314 
    PORT MAP (
315 
    vss => vss,
316 
    vdd => vdd,
317 
    nq => cp(13),
318 
    i => auxreg14);
319 
  cp_14 : inv_x1
320 
    PORT MAP (
321 
    vss => vss,
322 
    vdd => vdd,
323 
    nq => cp(14),
324 
    i => auxreg15);
325 
  cp_15 : inv_x1
326 
    PORT MAP (
327 
    vss => vss,
328 
    vdd => vdd,
329 
    nq => cp(15),
330 
    i => auxreg16);
331 
  cp_16 : inv_x1
332 
    PORT MAP (
333 
    vss => vss,
334 
    vdd => vdd,
335 
    nq => cp(16),
336 
    i => auxreg17);
337 
  cp_17 : inv_x1
338 
    PORT MAP (
339 
    vss => vss,
340 
    vdd => vdd,
341 
    nq => cp(17),
342 
    i => auxreg18);
343 
  cp_18 : inv_x1
344 
    PORT MAP (
345 
    vss => vss,
346 
    vdd => vdd,
347 
    nq => cp(18),
348 
    i => auxreg19);
349 
  cp_19 : inv_x1
350 
    PORT MAP (
351 
    vss => vss,
352 
    vdd => vdd,
353 
    nq => cp(19),
354 
    i => auxreg20);
355 
  cp_20 : inv_x1
356 
    PORT MAP (
357 
    vss => vss,
358 
    vdd => vdd,
359 
    nq => cp(20),
360 
    i => auxreg21);
361 
  cp_21 : inv_x1
362 
    PORT MAP (
363 
    vss => vss,
364 
    vdd => vdd,
365 
    nq => cp(21),
366 
    i => auxreg22);
367 
  cp_22 : inv_x1
368 
    PORT MAP (
369 
    vss => vss,
370 
    vdd => vdd,
371 
    nq => cp(22),
372 
    i => auxreg23);
373 
  cp_23 : inv_x1
374 
    PORT MAP (
375 
    vss => vss,
376 
    vdd => vdd,
377 
    nq => cp(23),
378 
    i => auxreg24);
379 
  cp_24 : inv_x1
380 
    PORT MAP (
381 
    vss => vss,
382 
    vdd => vdd,
383 
    nq => cp(24),
384 
    i => auxreg25);
385 
  cp_25 : inv_x1
386 
    PORT MAP (
387 
    vss => vss,
388 
    vdd => vdd,
389 
    nq => cp(25),
390 
    i => auxreg26);
391 
  cp_26 : inv_x1
392 
    PORT MAP (
393 
    vss => vss,
394 
    vdd => vdd,
395 
    nq => cp(26),
396 
    i => auxreg27);
397 
  cp_27 : inv_x1
398 
    PORT MAP (
399 
    vss => vss,
400 
    vdd => vdd,
401 
    nq => cp(27),
402 
    i => auxreg28);
403 
  cp_28 : inv_x1
404 
    PORT MAP (
405 
    vss => vss,
406 
    vdd => vdd,
407 
    nq => cp(28),
408 
    i => auxreg29);
409 
  cp_29 : inv_x1
410 
    PORT MAP (
411 
    vss => vss,
412 
    vdd => vdd,
413 
    nq => cp(29),
414 
    i => auxreg30);
415 
  cp_30 : inv_x1
416 
    PORT MAP (
417 
    vss => vss,
418 
    vdd => vdd,
419 
    nq => cp(30),
420 
    i => auxreg31);
421 
  cp_31 : inv_x1
422 
    PORT MAP (
423 
    vss => vss,
424 
    vdd => vdd,
425 
    nq => cp(31),
426 
    i => auxreg32);
427 
  auxsc274 : nao22_x1
428 
    PORT MAP (
429 
    vss => vss,
430 
    vdd => vdd,
431 
    nq => auxsc274,
432 
    i2 => auxsc276,
433 
    i1 => auxsc23,
434 
    i0 => y(31));
435 
  auxsc276 : na2_x1
436 
    PORT MAP (
437 
    vss => vss,
438 
    vdd => vdd,
439 
    nq => auxsc276,
440 
    i1 => aux11_a,
441 
    i0 => auxsc270);
442 
  auxsc270 : inv_x1
443 
    PORT MAP (
444 
    vss => vss,
445 
    vdd => vdd,
446 
    nq => auxsc270,
447 
    i => y(63));
448 
  auxsc267 : nao22_x1
449 
    PORT MAP (
450 
    vss => vss,
451 
    vdd => vdd,
452 
    nq => auxsc267,
453 
    i2 => auxsc269,
454 
    i1 => auxsc23,
455 
    i0 => y(30));
456 
  auxsc269 : na2_x1
457 
    PORT MAP (
458 
    vss => vss,
459 
    vdd => vdd,
460 
    nq => auxsc269,
461 
    i1 => aux11_a,
462 
    i0 => auxsc263);
463 
  auxsc263 : inv_x1
464 
    PORT MAP (
465 
    vss => vss,
466 
    vdd => vdd,
467 
    nq => auxsc263,
468 
    i => y(62));
469 
  auxsc260 : nao22_x1
470 
    PORT MAP (
471 
    vss => vss,
472 
    vdd => vdd,
473 
    nq => auxsc260,
474 
    i2 => auxsc262,
475 
    i1 => auxsc23,
476 
    i0 => y(29));
477 
  auxsc262 : na2_x1
478 
    PORT MAP (
479 
    vss => vss,
480 
    vdd => vdd,
481 
    nq => auxsc262,
482 
    i1 => aux11_a,
483 
    i0 => auxsc256);
484 
  auxsc256 : inv_x1
485 
    PORT MAP (
486 
    vss => vss,
487 
    vdd => vdd,
488 
    nq => auxsc256,
489 
    i => y(61));
490 
  auxsc251 : o2_x2
491 
    PORT MAP (
492 
    vss => vss,
493 
    vdd => vdd,
494 
    q => auxsc251,
495 
    i1 => auxsc255,
496 
    i0 => auxsc254);
497 
  auxsc255 : a2_x2
498 
    PORT MAP (
499 
    vss => vss,
500 
    vdd => vdd,
501 
    q => auxsc255,
502 
    i1 => auxsc243,
503 
    i0 => auxsc5);
504 
  auxsc243 : inv_x1
505 
    PORT MAP (
506 
    vss => vss,
507 
    vdd => vdd,
508 
    nq => auxsc243,
509 
    i => y(60));
510 
  auxsc254 : nao22_x1
511 
    PORT MAP (
512 
    vss => vss,
513 
    vdd => vdd,
514 
    nq => auxsc254,
515 
    i2 => auxsc4,
516 
    i1 => auxsc5,
517 
    i0 => y(28));
518 
  auxsc240 : nao22_x1
519 
    PORT MAP (
520 
    vss => vss,
521 
    vdd => vdd,
522 
    nq => auxsc240,
523 
    i2 => auxsc242,
524 
    i1 => auxsc23,
525 
    i0 => y(27));
526 
  auxsc242 : na2_x1
527 
    PORT MAP (
528 
    vss => vss,
529 
    vdd => vdd,
530 
    nq => auxsc242,
531 
    i1 => aux11_a,
532 
    i0 => auxsc236);
533 
  auxsc236 : inv_x1
534 
    PORT MAP (
535 
    vss => vss,
536 
    vdd => vdd,
537 
    nq => auxsc236,
538 
    i => y(59));
539 
  auxsc233 : nao22_x1
540 
    PORT MAP (
541 
    vss => vss,
542 
    vdd => vdd,
543 
    nq => auxsc233,
544 
    i2 => auxsc235,
545 
    i1 => auxsc23,
546 
    i0 => y(26));
547 
  auxsc235 : na2_x1
548 
    PORT MAP (
549 
    vss => vss,
550 
    vdd => vdd,
551 
    nq => auxsc235,
552 
    i1 => aux11_a,
553 
    i0 => auxsc229);
554 
  auxsc229 : inv_x1
555 
    PORT MAP (
556 
    vss => vss,
557 
    vdd => vdd,
558 
    nq => auxsc229,
559 
    i => y(58));
560 
  auxsc226 : nao22_x1
561 
    PORT MAP (
562 
    vss => vss,
563 
    vdd => vdd,
564 
    nq => auxsc226,
565 
    i2 => auxsc228,
566 
    i1 => auxsc23,
567 
    i0 => y(25));
568 
  auxsc228 : na2_x1
569 
    PORT MAP (
570 
    vss => vss,
571 
    vdd => vdd,
572 
    nq => auxsc228,
573 
    i1 => aux11_a,
574 
    i0 => auxsc222);
575 
  auxsc222 : inv_x1
576 
    PORT MAP (
577 
    vss => vss,
578 
    vdd => vdd,
579 
    nq => auxsc222,
580 
    i => y(57));
581 
  auxsc217 : o2_x2
582 
    PORT MAP (
583 
    vss => vss,
584 
    vdd => vdd,
585 
    q => auxsc217,
586 
    i1 => auxsc221,
587 
    i0 => auxsc220);
588 
  auxsc221 : a2_x2
589 
    PORT MAP (
590 
    vss => vss,
591 
    vdd => vdd,
592 
    q => auxsc221,
593 
    i1 => auxsc209,
594 
    i0 => auxsc5);
595 
  auxsc209 : inv_x1
596 
    PORT MAP (
597 
    vss => vss,
598 
    vdd => vdd,
599 
    nq => auxsc209,
600 
    i => y(56));
601 
  auxsc220 : nao22_x1
602 
    PORT MAP (
603 
    vss => vss,
604 
    vdd => vdd,
605 
    nq => auxsc220,
606 
    i2 => auxsc4,
607 
    i1 => auxsc5,
608 
    i0 => y(24));
609 
  auxsc206 : nao22_x1
610 
    PORT MAP (
611 
    vss => vss,
612 
    vdd => vdd,
613 
    nq => auxsc206,
614 
    i2 => auxsc208,
615 
    i1 => auxsc23,
616 
    i0 => y(23));
617 
  auxsc208 : na2_x1
618 
    PORT MAP (
619 
    vss => vss,
620 
    vdd => vdd,
621 
    nq => auxsc208,
622 
    i1 => aux11_a,
623 
    i0 => auxsc202);
624 
  auxsc202 : inv_x1
625 
    PORT MAP (
626 
    vss => vss,
627 
    vdd => vdd,
628 
    nq => auxsc202,
629 
    i => y(55));
630 
  auxsc199 : nao22_x1
631 
    PORT MAP (
632 
    vss => vss,
633 
    vdd => vdd,
634 
    nq => auxsc199,
635 
    i2 => auxsc201,
636 
    i1 => auxsc23,
637 
    i0 => y(22));
638 
  auxsc201 : na2_x1
639 
    PORT MAP (
640 
    vss => vss,
641 
    vdd => vdd,
642 
    nq => auxsc201,
643 
    i1 => aux11_a,
644 
    i0 => auxsc195);
645 
  auxsc195 : inv_x1
646 
    PORT MAP (
647 
    vss => vss,
648 
    vdd => vdd,
649 
    nq => auxsc195,
650 
    i => y(54));
651 
  auxsc192 : nao22_x1
652 
    PORT MAP (
653 
    vss => vss,
654 
    vdd => vdd,
655 
    nq => auxsc192,
656 
    i2 => auxsc194,
657 
    i1 => auxsc23,
658 
    i0 => y(21));
659 
  auxsc194 : na2_x1
660 
    PORT MAP (
661 
    vss => vss,
662 
    vdd => vdd,
663 
    nq => auxsc194,
664 
    i1 => aux11_a,
665 
    i0 => auxsc188);
666 
  auxsc188 : inv_x1
667 
    PORT MAP (
668 
    vss => vss,
669 
    vdd => vdd,
670 
    nq => auxsc188,
671 
    i => y(53));
672 
  auxsc183 : o2_x2
673 
    PORT MAP (
674 
    vss => vss,
675 
    vdd => vdd,
676 
    q => auxsc183,
677 
    i1 => auxsc187,
678 
    i0 => auxsc186);
679 
  auxsc187 : a2_x2
680 
    PORT MAP (
681 
    vss => vss,
682 
    vdd => vdd,
683 
    q => auxsc187,
684 
    i1 => auxsc175,
685 
    i0 => auxsc5);
686 
  auxsc175 : inv_x1
687 
    PORT MAP (
688 
    vss => vss,
689 
    vdd => vdd,
690 
    nq => auxsc175,
691 
    i => y(52));
692 
  auxsc186 : nao22_x1
693 
    PORT MAP (
694 
    vss => vss,
695 
    vdd => vdd,
696 
    nq => auxsc186,
697 
    i2 => auxsc4,
698 
    i1 => auxsc5,
699 
    i0 => y(20));
700 
  auxsc172 : nao22_x1
701 
    PORT MAP (
702 
    vss => vss,
703 
    vdd => vdd,
704 
    nq => auxsc172,
705 
    i2 => auxsc174,
706 
    i1 => auxsc23,
707 
    i0 => y(19));
708 
  auxsc174 : na2_x1
709 
    PORT MAP (
710 
    vss => vss,
711 
    vdd => vdd,
712 
    nq => auxsc174,
713 
    i1 => aux11_a,
714 
    i0 => auxsc168);
715 
  auxsc168 : inv_x1
716 
    PORT MAP (
717 
    vss => vss,
718 
    vdd => vdd,
719 
    nq => auxsc168,
720 
    i => y(51));
721 
  auxsc165 : nao22_x1
722 
    PORT MAP (
723 
    vss => vss,
724 
    vdd => vdd,
725 
    nq => auxsc165,
726 
    i2 => auxsc167,
727 
    i1 => auxsc23,
728 
    i0 => y(18));
729 
  auxsc167 : na2_x1
730 
    PORT MAP (
731 
    vss => vss,
732 
    vdd => vdd,
733 
    nq => auxsc167,
734 
    i1 => aux11_a,
735 
    i0 => auxsc161);
736 
  auxsc161 : inv_x1
737 
    PORT MAP (
738 
    vss => vss,
739 
    vdd => vdd,
740 
    nq => auxsc161,
741 
    i => y(50));
742 
  auxsc158 : nao22_x1
743 
    PORT MAP (
744 
    vss => vss,
745 
    vdd => vdd,
746 
    nq => auxsc158,
747 
    i2 => auxsc160,
748 
    i1 => auxsc23,
749 
    i0 => y(17));
750 
  auxsc160 : na2_x1
751 
    PORT MAP (
752 
    vss => vss,
753 
    vdd => vdd,
754 
    nq => auxsc160,
755 
    i1 => aux11_a,
756 
    i0 => auxsc154);
757 
  auxsc154 : inv_x1
758 
    PORT MAP (
759 
    vss => vss,
760 
    vdd => vdd,
761 
    nq => auxsc154,
762 
    i => y(49));
763 
  auxsc149 : o2_x2
764 
    PORT MAP (
765 
    vss => vss,
766 
    vdd => vdd,
767 
    q => auxsc149,
768 
    i1 => auxsc153,
769 
    i0 => auxsc152);
770 
  auxsc153 : a2_x2
771 
    PORT MAP (
772 
    vss => vss,
773 
    vdd => vdd,
774 
    q => auxsc153,
775 
    i1 => auxsc141,
776 
    i0 => auxsc5);
777 
  auxsc141 : inv_x1
778 
    PORT MAP (
779 
    vss => vss,
780 
    vdd => vdd,
781 
    nq => auxsc141,
782 
    i => y(48));
783 
  auxsc152 : nao22_x1
784 
    PORT MAP (
785 
    vss => vss,
786 
    vdd => vdd,
787 
    nq => auxsc152,
788 
    i2 => auxsc4,
789 
    i1 => auxsc5,
790 
    i0 => y(16));
791 
  auxsc138 : nao22_x1
792 
    PORT MAP (
793 
    vss => vss,
794 
    vdd => vdd,
795 
    nq => auxsc138,
796 
    i2 => auxsc140,
797 
    i1 => auxsc23,
798 
    i0 => y(15));
799 
  auxsc140 : na2_x1
800 
    PORT MAP (
801 
    vss => vss,
802 
    vdd => vdd,
803 
    nq => auxsc140,
804 
    i1 => aux11_a,
805 
    i0 => auxsc134);
806 
  auxsc134 : inv_x1
807 
    PORT MAP (
808 
    vss => vss,
809 
    vdd => vdd,
810 
    nq => auxsc134,
811 
    i => y(47));
812 
  auxsc131 : nao22_x1
813 
    PORT MAP (
814 
    vss => vss,
815 
    vdd => vdd,
816 
    nq => auxsc131,
817 
    i2 => auxsc133,
818 
    i1 => auxsc23,
819 
    i0 => y(14));
820 
  auxsc133 : na2_x1
821 
    PORT MAP (
822 
    vss => vss,
823 
    vdd => vdd,
824 
    nq => auxsc133,
825 
    i1 => aux11_a,
826 
    i0 => auxsc127);
827 
  auxsc127 : inv_x1
828 
    PORT MAP (
829 
    vss => vss,
830 
    vdd => vdd,
831 
    nq => auxsc127,
832 
    i => y(46));
833 
  auxsc124 : nao22_x1
834 
    PORT MAP (
835 
    vss => vss,
836 
    vdd => vdd,
837 
    nq => auxsc124,
838 
    i2 => auxsc126,
839 
    i1 => auxsc23,
840 
    i0 => y(13));
841 
  auxsc126 : na2_x1
842 
    PORT MAP (
843 
    vss => vss,
844 
    vdd => vdd,
845 
    nq => auxsc126,
846 
    i1 => aux11_a,
847 
    i0 => auxsc120);
848 
  auxsc120 : inv_x1
849 
    PORT MAP (
850 
    vss => vss,
851 
    vdd => vdd,
852 
    nq => auxsc120,
853 
    i => y(45));
854 
  auxsc115 : o2_x2
855 
    PORT MAP (
856 
    vss => vss,
857 
    vdd => vdd,
858 
    q => auxsc115,
859 
    i1 => auxsc119,
860 
    i0 => auxsc118);
861 
  auxsc119 : a2_x2
862 
    PORT MAP (
863 
    vss => vss,
864 
    vdd => vdd,
865 
    q => auxsc119,
866 
    i1 => auxsc107,
867 
    i0 => auxsc5);
868 
  auxsc107 : inv_x1
869 
    PORT MAP (
870 
    vss => vss,
871 
    vdd => vdd,
872 
    nq => auxsc107,
873 
    i => y(44));
874 
  auxsc118 : nao22_x1
875 
    PORT MAP (
876 
    vss => vss,
877 
    vdd => vdd,
878 
    nq => auxsc118,
879 
    i2 => auxsc4,
880 
    i1 => auxsc5,
881 
    i0 => y(12));
882 
  auxsc104 : nao22_x1
883 
    PORT MAP (
884 
    vss => vss,
885 
    vdd => vdd,
886 
    nq => auxsc104,
887 
    i2 => auxsc106,
888 
    i1 => auxsc23,
889 
    i0 => y(11));
890 
  auxsc106 : na2_x1
891 
    PORT MAP (
892 
    vss => vss,
893 
    vdd => vdd,
894 
    nq => auxsc106,
895 
    i1 => aux11_a,
896 
    i0 => auxsc100);
897 
  auxsc100 : inv_x1
898 
    PORT MAP (
899 
    vss => vss,
900 
    vdd => vdd,
901 
    nq => auxsc100,
902 
    i => y(43));
903 
  auxsc97 : nao22_x1
904 
    PORT MAP (
905 
    vss => vss,
906 
    vdd => vdd,
907 
    nq => auxsc97,
908 
    i2 => auxsc99,
909 
    i1 => auxsc23,
910 
    i0 => y(10));
911 
  auxsc99 : na2_x1
912 
    PORT MAP (
913 
    vss => vss,
914 
    vdd => vdd,
915 
    nq => auxsc99,
916 
    i1 => aux11_a,
917 
    i0 => auxsc93);
918 
  auxsc93 : inv_x1
919 
    PORT MAP (
920 
    vss => vss,
921 
    vdd => vdd,
922 
    nq => auxsc93,
923 
    i => y(42));
924 
  auxsc90 : nao22_x1
925 
    PORT MAP (
926 
    vss => vss,
927 
    vdd => vdd,
928 
    nq => auxsc90,
929 
    i2 => auxsc92,
930 
    i1 => auxsc23,
931 
    i0 => y(9));
932 
  auxsc92 : na2_x1
933 
    PORT MAP (
934 
    vss => vss,
935 
    vdd => vdd,
936 
    nq => auxsc92,
937 
    i1 => aux11_a,
938 
    i0 => auxsc86);
939 
  auxsc86 : inv_x1
940 
    PORT MAP (
941 
    vss => vss,
942 
    vdd => vdd,
943 
    nq => auxsc86,
944 
    i => y(41));
945 
  auxsc81 : o2_x2
946 
    PORT MAP (
947 
    vss => vss,
948 
    vdd => vdd,
949 
    q => auxsc81,
950 
    i1 => auxsc85,
951 
    i0 => auxsc84);
952 
  auxsc85 : a2_x2
953 
    PORT MAP (
954 
    vss => vss,
955 
    vdd => vdd,
956 
    q => auxsc85,
957 
    i1 => auxsc73,
958 
    i0 => auxsc5);
959 
  auxsc73 : inv_x1
960 
    PORT MAP (
961 
    vss => vss,
962 
    vdd => vdd,
963 
    nq => auxsc73,
964 
    i => y(40));
965 
  auxsc84 : nao22_x1
966 
    PORT MAP (
967 
    vss => vss,
968 
    vdd => vdd,
969 
    nq => auxsc84,
970 
    i2 => auxsc4,
971 
    i1 => auxsc5,
972 
    i0 => y(8));
973 
  auxsc70 : nao22_x1
974 
    PORT MAP (
975 
    vss => vss,
976 
    vdd => vdd,
977 
    nq => auxsc70,
978 
    i2 => auxsc72,
979 
    i1 => auxsc23,
980 
    i0 => y(7));
981 
  auxsc72 : na2_x1
982 
    PORT MAP (
983 
    vss => vss,
984 
    vdd => vdd,
985 
    nq => auxsc72,
986 
    i1 => aux11_a,
987 
    i0 => auxsc66);
988 
  auxsc66 : inv_x1
989 
    PORT MAP (
990 
    vss => vss,
991 
    vdd => vdd,
992 
    nq => auxsc66,
993 
    i => y(39));
994 
  auxsc63 : nao22_x1
995 
    PORT MAP (
996 
    vss => vss,
997 
    vdd => vdd,
998 
    nq => auxsc63,
999 
    i2 => auxsc65,
1000 
    i1 => auxsc23,
1001 
    i0 => y(6));
1002 
  auxsc65 : na2_x1
1003 
    PORT MAP (
1004 
    vss => vss,
1005 
    vdd => vdd,
1006 
    nq => auxsc65,
1007 
    i1 => aux11_a,
1008 
    i0 => auxsc59);
1009 
  auxsc59 : inv_x1
1010 
    PORT MAP (
1011 
    vss => vss,
1012 
    vdd => vdd,
1013 
    nq => auxsc59,
1014 
    i => y(38));
1015 
  auxsc56 : nao22_x1
1016 
    PORT MAP (
1017 
    vss => vss,
1018 
    vdd => vdd,
1019 
    nq => auxsc56,
1020 
    i2 => auxsc58,
1021 
    i1 => auxsc23,
1022 
    i0 => y(5));
1023 
  auxsc58 : na2_x1
1024 
    PORT MAP (
1025 
    vss => vss,
1026 
    vdd => vdd,
1027 
    nq => auxsc58,
1028 
    i1 => aux11_a,
1029 
    i0 => auxsc52);
1030 
  auxsc52 : inv_x1
1031 
    PORT MAP (
1032 
    vss => vss,
1033 
    vdd => vdd,
1034 
    nq => auxsc52,
1035 
    i => y(37));
1036 
  auxsc47 : o2_x2
1037 
    PORT MAP (
1038 
    vss => vss,
1039 
    vdd => vdd,
1040 
    q => auxsc47,
1041 
    i1 => auxsc51,
1042 
    i0 => auxsc50);
1043 
  auxsc51 : a2_x2
1044 
    PORT MAP (
1045 
    vss => vss,
1046 
    vdd => vdd,
1047 
    q => auxsc51,
1048 
    i1 => auxsc39,
1049 
    i0 => auxsc5);
1050 
  auxsc39 : inv_x1
1051 
    PORT MAP (
1052 
    vss => vss,
1053 
    vdd => vdd,
1054 
    nq => auxsc39,
1055 
    i => y(36));
1056 
  auxsc50 : nao22_x1
1057 
    PORT MAP (
1058 
    vss => vss,
1059 
    vdd => vdd,
1060 
    nq => auxsc50,
1061 
    i2 => auxsc4,
1062 
    i1 => auxsc5,
1063 
    i0 => y(4));
1064 
  auxsc36 : nao22_x1
1065 
    PORT MAP (
1066 
    vss => vss,
1067 
    vdd => vdd,
1068 
    nq => auxsc36,
1069 
    i2 => auxsc38,
1070 
    i1 => auxsc23,
1071 
    i0 => y(3));
1072 
  auxsc38 : na2_x1
1073 
    PORT MAP (
1074 
    vss => vss,
1075 
    vdd => vdd,
1076 
    nq => auxsc38,
1077 
    i1 => aux11_a,
1078 
    i0 => auxsc32);
1079 
  auxsc32 : inv_x1
1080 
    PORT MAP (
1081 
    vss => vss,
1082 
    vdd => vdd,
1083 
    nq => auxsc32,
1084 
    i => y(35));
1085 
  auxsc29 : nao22_x1
1086 
    PORT MAP (
1087 
    vss => vss,
1088 
    vdd => vdd,
1089 
    nq => auxsc29,
1090 
    i2 => auxsc31,
1091 
    i1 => auxsc23,
1092 
    i0 => y(2));
1093 
  auxsc31 : na2_x1
1094 
    PORT MAP (
1095 
    vss => vss,
1096 
    vdd => vdd,
1097 
    nq => auxsc31,
1098 
    i1 => aux11_a,
1099 
    i0 => auxsc25);
1100 
  auxsc25 : inv_x1
1101 
    PORT MAP (
1102 
    vss => vss,
1103 
    vdd => vdd,
1104 
    nq => auxsc25,
1105 
    i => y(34));
1106 
  auxsc21 : nao22_x1
1107 
    PORT MAP (
1108 
    vss => vss,
1109 
    vdd => vdd,
1110 
    nq => auxsc21,
1111 
    i2 => auxsc24,
1112 
    i1 => auxsc23,
1113 
    i0 => y(1));
1114 
  auxsc24 : na2_x1
1115 
    PORT MAP (
1116 
    vss => vss,
1117 
    vdd => vdd,
1118 
    nq => auxsc24,
1119 
    i1 => aux11_a,
1120 
    i0 => auxsc17);
1121 
  auxsc17 : inv_x1
1122 
    PORT MAP (
1123 
    vss => vss,
1124 
    vdd => vdd,
1125 
    nq => auxsc17,
1126 
    i => y(33));
1127 
  auxsc23 : na2_x1
1128 
    PORT MAP (
1129 
    vss => vss,
1130 
    vdd => vdd,
1131 
    nq => auxsc23,
1132 
    i1 => auxsc4,
1133 
    i0 => sel);
1134 
  auxsc9 : o2_x2
1135 
    PORT MAP (
1136 
    vss => vss,
1137 
    vdd => vdd,
1138 
    q => auxsc9,
1139 
    i1 => auxsc13,
1140 
    i0 => auxsc12);
1141 
  auxsc13 : a2_x2
1142 
    PORT MAP (
1143 
    vss => vss,
1144 
    vdd => vdd,
1145 
    q => auxsc13,
1146 
    i1 => auxsc1,
1147 
    i0 => auxsc5);
1148 
  auxsc1 : inv_x1
1149 
    PORT MAP (
1150 
    vss => vss,
1151 
    vdd => vdd,
1152 
    nq => auxsc1,
1153 
    i => y(32));
1154 
  auxsc12 : nao22_x1
1155 
    PORT MAP (
1156 
    vss => vss,
1157 
    vdd => vdd,
1158 
    nq => auxsc12,
1159 
    i2 => auxsc4,
1160 
    i1 => auxsc5,
1161 
    i0 => y(0));
1162 
  auxsc4 : inv_x1
1163 
    PORT MAP (
1164 
    vss => vss,
1165 
    vdd => vdd,
1166 
    nq => auxsc4,
1167 
    i => rst);
1168 
  auxsc5 : inv_x1
1169 
    PORT MAP (
1170 
    vss => vss,
1171 
    vdd => vdd,
1172 
    nq => auxsc5,
1173 
    i => sel);
1174 
  aux11_a : no2_x1
1175 
    PORT MAP (
1176 
    vss => vss,
1177 
    vdd => vdd,
1178 
    nq => aux11_a,
1179 
    i1 => sel,
1180 
    i0 => rst);
1181 
  reg_0 : sff1_x4
1182 
    PORT MAP (
1183 
    vss => vss,
1184 
    vdd => vdd,
1185 
    q => auxreg1,
1186 
    i => auxsc9,
1187 
    ck => clk);
1188 
  reg_1 : sff1_x4
1189 
    PORT MAP (
1190 
    vss => vss,
1191 
    vdd => vdd,
1192 
    q => auxreg2,
1193 
    i => auxsc21,
1194 
    ck => clk);
1195 
  reg_2 : sff1_x4
1196 
    PORT MAP (
1197 
    vss => vss,
1198 
    vdd => vdd,
1199 
    q => auxreg3,
1200 
    i => auxsc29,
1201 
    ck => clk);
1202 
  reg_3 : sff1_x4
1203 
    PORT MAP (
1204 
    vss => vss,
1205 
    vdd => vdd,
1206 
    q => auxreg4,
1207 
    i => auxsc36,
1208 
    ck => clk);
1209 
  reg_4 : sff1_x4
1210 
    PORT MAP (
1211 
    vss => vss,
1212 
    vdd => vdd,
1213 
    q => auxreg5,
1214 
    i => auxsc47,
1215 
    ck => clk);
1216 
  reg_5 : sff1_x4
1217 
    PORT MAP (
1218 
    vss => vss,
1219 
    vdd => vdd,
1220 
    q => auxreg6,
1221 
    i => auxsc56,
1222 
    ck => clk);
1223 
  reg_6 : sff1_x4
1224 
    PORT MAP (
1225 
    vss => vss,
1226 
    vdd => vdd,
1227 
    q => auxreg7,
1228 
    i => auxsc63,
1229 
    ck => clk);
1230 
  reg_7 : sff1_x4
1231 
    PORT MAP (
1232 
    vss => vss,
1233 
    vdd => vdd,
1234 
    q => auxreg8,
1235 
    i => auxsc70,
1236 
    ck => clk);
1237 
  reg_8 : sff1_x4
1238 
    PORT MAP (
1239 
    vss => vss,
1240 
    vdd => vdd,
1241 
    q => auxreg9,
1242 
    i => auxsc81,
1243 
    ck => clk);
1244 
  reg_9 : sff1_x4
1245 
    PORT MAP (
1246 
    vss => vss,
1247 
    vdd => vdd,
1248 
    q => auxreg10,
1249 
    i => auxsc90,
1250 
    ck => clk);
1251 
  reg_10 : sff1_x4
1252 
    PORT MAP (
1253 
    vss => vss,
1254 
    vdd => vdd,
1255 
    q => auxreg11,
1256 
    i => auxsc97,
1257 
    ck => clk);
1258 
  reg_11 : sff1_x4
1259 
    PORT MAP (
1260 
    vss => vss,
1261 
    vdd => vdd,
1262 
    q => auxreg12,
1263 
    i => auxsc104,
1264 
    ck => clk);
1265 
  reg_12 : sff1_x4
1266 
    PORT MAP (
1267 
    vss => vss,
1268 
    vdd => vdd,
1269 
    q => auxreg13,
1270 
    i => auxsc115,
1271 
    ck => clk);
1272 
  reg_13 : sff1_x4
1273 
    PORT MAP (
1274 
    vss => vss,
1275 
    vdd => vdd,
1276 
    q => auxreg14,
1277 
    i => auxsc124,
1278 
    ck => clk);
1279 
  reg_14 : sff1_x4
1280 
    PORT MAP (
1281 
    vss => vss,
1282 
    vdd => vdd,
1283 
    q => auxreg15,
1284 
    i => auxsc131,
1285 
    ck => clk);
1286 
  reg_15 : sff1_x4
1287 
    PORT MAP (
1288 
    vss => vss,
1289 
    vdd => vdd,
1290 
    q => auxreg16,
1291 
    i => auxsc138,
1292 
    ck => clk);
1293 
  reg_16 : sff1_x4
1294 
    PORT MAP (
1295 
    vss => vss,
1296 
    vdd => vdd,
1297 
    q => auxreg17,
1298 
    i => auxsc149,
1299 
    ck => clk);
1300 
  reg_17 : sff1_x4
1301 
    PORT MAP (
1302 
    vss => vss,
1303 
    vdd => vdd,
1304 
    q => auxreg18,
1305 
    i => auxsc158,
1306 
    ck => clk);
1307 
  reg_18 : sff1_x4
1308 
    PORT MAP (
1309 
    vss => vss,
1310 
    vdd => vdd,
1311 
    q => auxreg19,
1312 
    i => auxsc165,
1313 
    ck => clk);
1314 
  reg_19 : sff1_x4
1315 
    PORT MAP (
1316 
    vss => vss,
1317 
    vdd => vdd,
1318 
    q => auxreg20,
1319 
    i => auxsc172,
1320 
    ck => clk);
1321 
  reg_20 : sff1_x4
1322 
    PORT MAP (
1323 
    vss => vss,
1324 
    vdd => vdd,
1325 
    q => auxreg21,
1326 
    i => auxsc183,
1327 
    ck => clk);
1328 
  reg_21 : sff1_x4
1329 
    PORT MAP (
1330 
    vss => vss,
1331 
    vdd => vdd,
1332 
    q => auxreg22,
1333 
    i => auxsc192,
1334 
    ck => clk);
1335 
  reg_22 : sff1_x4
1336 
    PORT MAP (
1337 
    vss => vss,
1338 
    vdd => vdd,
1339 
    q => auxreg23,
1340 
    i => auxsc199,
1341 
    ck => clk);
1342 
  reg_23 : sff1_x4
1343 
    PORT MAP (
1344 
    vss => vss,
1345 
    vdd => vdd,
1346 
    q => auxreg24,
1347 
    i => auxsc206,
1348 
    ck => clk);
1349 
  reg_24 : sff1_x4
1350 
    PORT MAP (
1351 
    vss => vss,
1352 
    vdd => vdd,
1353 
    q => auxreg25,
1354 
    i => auxsc217,
1355 
    ck => clk);
1356 
  reg_25 : sff1_x4
1357 
    PORT MAP (
1358 
    vss => vss,
1359 
    vdd => vdd,
1360 
    q => auxreg26,
1361 
    i => auxsc226,
1362 
    ck => clk);
1363 
  reg_26 : sff1_x4
1364 
    PORT MAP (
1365 
    vss => vss,
1366 
    vdd => vdd,
1367 
    q => auxreg27,
1368 
    i => auxsc233,
1369 
    ck => clk);
1370 
  reg_27 : sff1_x4
1371 
    PORT MAP (
1372 
    vss => vss,
1373 
    vdd => vdd,
1374 
    q => auxreg28,
1375 
    i => auxsc240,
1376 
    ck => clk);
1377 
  reg_28 : sff1_x4
1378 
    PORT MAP (
1379 
    vss => vss,
1380 
    vdd => vdd,
1381 
    q => auxreg29,
1382 
    i => auxsc251,
1383 
    ck => clk);
1384 
  reg_29 : sff1_x4
1385 
    PORT MAP (
1386 
    vss => vss,
1387 
    vdd => vdd,
1388 
    q => auxreg30,
1389 
    i => auxsc260,
1390 
    ck => clk);
1391 
  reg_30 : sff1_x4
1392 
    PORT MAP (
1393 
    vss => vss,
1394 
    vdd => vdd,
1395 
    q => auxreg31,
1396 
    i => auxsc267,
1397 
    ck => clk);
1398 
  reg_31 : sff1_x4
1399 
    PORT MAP (
1400 
    vss => vss,
1401 
    vdd => vdd,
1402 
    q => auxreg32,
1403 
    i => auxsc274,
1404 
    ck => clk);
1405 
 
1406 
end VST;

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