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[/] [structural_vhdl/] [trunk/] [key_regulator/] [adder01.vst] - Blame information for rev 4

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1 2 marta 
-- VHDL structural description generated from `adder01`
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--              date : Mon Jul 30 22:16:42 2001
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-- Entity Declaration
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ENTITY adder01 IS
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  PORT (
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  a : in BIT;   -- a
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  b : in BIT;   -- b
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  cin : in BIT; -- cin
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  sum : out BIT;        -- sum
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  cout : out BIT;       -- cout
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  vdd : in BIT; -- vdd
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  vss : in BIT  -- vss
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  );
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END adder01;
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-- Architecture Declaration
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ARCHITECTURE VST OF adder01 IS
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  COMPONENT o2_x2
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    port (
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    i0 : in BIT;        -- i0
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    i1 : in BIT;        -- i1
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    q : out BIT;        -- q
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  COMPONENT xr2_x1
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    port (
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    i0 : in BIT;        -- i0
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    i1 : in BIT;        -- i1
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    q : out BIT;        -- q
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  COMPONENT a2_x2
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    port (
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    i0 : in BIT;        -- i0
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    i1 : in BIT;        -- i1
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    q : out BIT;        -- q
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  COMPONENT ao22_x2
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    port (
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    i0 : in BIT;        -- i0
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    i1 : in BIT;        -- i1
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    i2 : in BIT;        -- i2
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    q : out BIT;        -- q
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  SIGNAL auxsc4 : BIT;  -- auxsc4
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  SIGNAL auxsc2 : BIT;  -- auxsc2
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  SIGNAL auxsc1 : BIT;  -- auxsc1
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BEGIN
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  cout : o2_x2
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => cout,
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    i1 => auxsc2,
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    i0 => auxsc4);
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  sum : xr2_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => sum,
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    i1 => auxsc1,
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    i0 => cin);
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  auxsc1 : xr2_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => auxsc1,
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    i1 => a,
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    i0 => b);
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  auxsc2 : a2_x2
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => auxsc2,
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    i1 => a,
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    i0 => b);
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  auxsc4 : ao22_x2
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => auxsc4,
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    i2 => cin,
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    i1 => a,
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    i0 => b);
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end VST;

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