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[/] [structural_vhdl/] [trunk/] [key_regulator/] [comparator.vst] - Blame information for rev 4

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1 2 marta 
-- VHDL structural description generated from `comparator`
2 
--              date : Tue Jul 31 10:46:19 2001
3 
 
4 
 
5 
-- Entity Declaration
6 
 
7 
ENTITY comparator IS
8 
  PORT (
9 
  a : in BIT_VECTOR (15 DOWNTO 0);      -- a
10 
  o : inout BIT_VECTOR (16 DOWNTO 0);   -- o
11 
  vdd : in BIT; -- vdd
12 
  vss : in BIT  -- vss
13 
  );
14 
END comparator;
15 
 
16 
-- Architecture Declaration
17 
 
18 
ARCHITECTURE VST OF comparator IS
19 
  COMPONENT nao2o22_x1
20 
    port (
21 
    i0 : in BIT;        -- i0
22 
    i1 : in BIT;        -- i1
23 
    i2 : in BIT;        -- i2
24 
    i3 : in BIT;        -- i3
25 
    nq : out BIT;       -- nq
26 
    vdd : in BIT;       -- vdd
27 
    vss : in BIT        -- vss
28 
    );
29 
  END COMPONENT;
30 
 
31 
  COMPONENT o3_x2
32 
    port (
33 
    i0 : in BIT;        -- i0
34 
    i1 : in BIT;        -- i1
35 
    i2 : in BIT;        -- i2
36 
    q : out BIT;        -- q
37 
    vdd : in BIT;       -- vdd
38 
    vss : in BIT        -- vss
39 
    );
40 
  END COMPONENT;
41 
 
42 
  COMPONENT o2_x2
43 
    port (
44 
    i0 : in BIT;        -- i0
45 
    i1 : in BIT;        -- i1
46 
    q : out BIT;        -- q
47 
    vdd : in BIT;       -- vdd
48 
    vss : in BIT        -- vss
49 
    );
50 
  END COMPONENT;
51 
 
52 
  COMPONENT o4_x2
53 
    port (
54 
    i0 : in BIT;        -- i0
55 
    i1 : in BIT;        -- i1
56 
    i2 : in BIT;        -- i2
57 
    i3 : in BIT;        -- i3
58 
    q : out BIT;        -- q
59 
    vdd : in BIT;       -- vdd
60 
    vss : in BIT        -- vss
61 
    );
62 
  END COMPONENT;
63 
 
64 
  COMPONENT a4_x2
65 
    port (
66 
    i0 : in BIT;        -- i0
67 
    i1 : in BIT;        -- i1
68 
    i2 : in BIT;        -- i2
69 
    i3 : in BIT;        -- i3
70 
    q : out BIT;        -- q
71 
    vdd : in BIT;       -- vdd
72 
    vss : in BIT        -- vss
73 
    );
74 
  END COMPONENT;
75 
 
76 
  COMPONENT no4_x1
77 
    port (
78 
    i0 : in BIT;        -- i0
79 
    i1 : in BIT;        -- i1
80 
    i2 : in BIT;        -- i2
81 
    i3 : in BIT;        -- i3
82 
    nq : out BIT;       -- nq
83 
    vdd : in BIT;       -- vdd
84 
    vss : in BIT        -- vss
85 
    );
86 
  END COMPONENT;
87 
 
88 
  COMPONENT inv_x1
89 
    port (
90 
    i : in BIT; -- i
91 
    nq : out BIT;       -- nq
92 
    vdd : in BIT;       -- vdd
93 
    vss : in BIT        -- vss
94 
    );
95 
  END COMPONENT;
96 
 
97 
  SIGNAL auxsc1 : BIT;  -- auxsc1
98 
  SIGNAL auxsc37 : BIT; -- auxsc37
99 
  SIGNAL auxsc38 : BIT; -- auxsc38
100 
  SIGNAL auxsc39 : BIT; -- auxsc39
101 
  SIGNAL auxsc40 : BIT; -- auxsc40
102 
  SIGNAL auxsc52 : BIT; -- auxsc52
103 
  SIGNAL auxsc51 : BIT; -- auxsc51
104 
  SIGNAL auxsc50 : BIT; -- auxsc50
105 
  SIGNAL auxsc57 : BIT; -- auxsc57
106 
  SIGNAL auxsc54 : BIT; -- auxsc54
107 
  SIGNAL auxsc58 : BIT; -- auxsc58
108 
  SIGNAL auxsc2 : BIT;  -- auxsc2
109 
  SIGNAL auxsc106 : BIT;        -- auxsc106
110 
  SIGNAL auxsc3 : BIT;  -- auxsc3
111 
  SIGNAL auxsc154 : BIT;        -- auxsc154
112 
  SIGNAL auxsc4 : BIT;  -- auxsc4
113 
  SIGNAL auxsc202 : BIT;        -- auxsc202
114 
  SIGNAL auxsc5 : BIT;  -- auxsc5
115 
  SIGNAL auxsc250 : BIT;        -- auxsc250
116 
  SIGNAL auxsc6 : BIT;  -- auxsc6
117 
  SIGNAL auxsc298 : BIT;        -- auxsc298
118 
  SIGNAL auxsc7 : BIT;  -- auxsc7
119 
  SIGNAL auxsc346 : BIT;        -- auxsc346
120 
  SIGNAL auxsc8 : BIT;  -- auxsc8
121 
  SIGNAL auxsc394 : BIT;        -- auxsc394
122 
  SIGNAL auxsc9 : BIT;  -- auxsc9
123 
  SIGNAL auxsc442 : BIT;        -- auxsc442
124 
  SIGNAL auxsc10 : BIT; -- auxsc10
125 
  SIGNAL auxsc490 : BIT;        -- auxsc490
126 
  SIGNAL auxsc11 : BIT; -- auxsc11
127 
  SIGNAL auxsc538 : BIT;        -- auxsc538
128 
  SIGNAL auxsc12 : BIT; -- auxsc12
129 
  SIGNAL auxsc586 : BIT;        -- auxsc586
130 
  SIGNAL auxsc13 : BIT; -- auxsc13
131 
  SIGNAL auxsc634 : BIT;        -- auxsc634
132 
  SIGNAL auxsc14 : BIT; -- auxsc14
133 
  SIGNAL auxsc682 : BIT;        -- auxsc682
134 
  SIGNAL auxsc15 : BIT; -- auxsc15
135 
  SIGNAL auxsc730 : BIT;        -- auxsc730
136 
  SIGNAL auxsc16 : BIT; -- auxsc16
137 
  SIGNAL auxsc778 : BIT;        -- auxsc778
138 
 
139 
BEGIN
140 
 
141 
  o_0 : nao2o22_x1
142 
    PORT MAP (
143 
    vss => vss,
144 
    vdd => vdd,
145 
    nq => o(0),
146 
    i3 => auxsc58,
147 
    i2 => auxsc57,
148 
    i1 => o(16),
149 
    i0 => auxsc1);
150 
  o_1 : nao2o22_x1
151 
    PORT MAP (
152 
    vss => vss,
153 
    vdd => vdd,
154 
    nq => o(1),
155 
    i3 => auxsc106,
156 
    i2 => auxsc57,
157 
    i1 => o(16),
158 
    i0 => auxsc2);
159 
  o_2 : nao2o22_x1
160 
    PORT MAP (
161 
    vss => vss,
162 
    vdd => vdd,
163 
    nq => o(2),
164 
    i3 => auxsc154,
165 
    i2 => auxsc57,
166 
    i1 => o(16),
167 
    i0 => auxsc3);
168 
  o_3 : nao2o22_x1
169 
    PORT MAP (
170 
    vss => vss,
171 
    vdd => vdd,
172 
    nq => o(3),
173 
    i3 => auxsc202,
174 
    i2 => auxsc57,
175 
    i1 => o(16),
176 
    i0 => auxsc4);
177 
  o_4 : nao2o22_x1
178 
    PORT MAP (
179 
    vss => vss,
180 
    vdd => vdd,
181 
    nq => o(4),
182 
    i3 => auxsc250,
183 
    i2 => auxsc57,
184 
    i1 => o(16),
185 
    i0 => auxsc5);
186 
  o_5 : nao2o22_x1
187 
    PORT MAP (
188 
    vss => vss,
189 
    vdd => vdd,
190 
    nq => o(5),
191 
    i3 => auxsc298,
192 
    i2 => auxsc57,
193 
    i1 => o(16),
194 
    i0 => auxsc6);
195 
  o_6 : nao2o22_x1
196 
    PORT MAP (
197 
    vss => vss,
198 
    vdd => vdd,
199 
    nq => o(6),
200 
    i3 => auxsc346,
201 
    i2 => auxsc57,
202 
    i1 => o(16),
203 
    i0 => auxsc7);
204 
  o_7 : nao2o22_x1
205 
    PORT MAP (
206 
    vss => vss,
207 
    vdd => vdd,
208 
    nq => o(7),
209 
    i3 => auxsc394,
210 
    i2 => auxsc57,
211 
    i1 => o(16),
212 
    i0 => auxsc8);
213 
  o_8 : nao2o22_x1
214 
    PORT MAP (
215 
    vss => vss,
216 
    vdd => vdd,
217 
    nq => o(8),
218 
    i3 => auxsc442,
219 
    i2 => auxsc57,
220 
    i1 => o(16),
221 
    i0 => auxsc9);
222 
  o_9 : nao2o22_x1
223 
    PORT MAP (
224 
    vss => vss,
225 
    vdd => vdd,
226 
    nq => o(9),
227 
    i3 => auxsc490,
228 
    i2 => auxsc57,
229 
    i1 => o(16),
230 
    i0 => auxsc10);
231 
  o_10 : nao2o22_x1
232 
    PORT MAP (
233 
    vss => vss,
234 
    vdd => vdd,
235 
    nq => o(10),
236 
    i3 => auxsc538,
237 
    i2 => auxsc57,
238 
    i1 => o(16),
239 
    i0 => auxsc11);
240 
  o_11 : nao2o22_x1
241 
    PORT MAP (
242 
    vss => vss,
243 
    vdd => vdd,
244 
    nq => o(11),
245 
    i3 => auxsc586,
246 
    i2 => auxsc57,
247 
    i1 => o(16),
248 
    i0 => auxsc12);
249 
  o_12 : nao2o22_x1
250 
    PORT MAP (
251 
    vss => vss,
252 
    vdd => vdd,
253 
    nq => o(12),
254 
    i3 => auxsc634,
255 
    i2 => auxsc57,
256 
    i1 => o(16),
257 
    i0 => auxsc13);
258 
  o_13 : nao2o22_x1
259 
    PORT MAP (
260 
    vss => vss,
261 
    vdd => vdd,
262 
    nq => o(13),
263 
    i3 => auxsc682,
264 
    i2 => auxsc57,
265 
    i1 => o(16),
266 
    i0 => auxsc14);
267 
  o_14 : nao2o22_x1
268 
    PORT MAP (
269 
    vss => vss,
270 
    vdd => vdd,
271 
    nq => o(14),
272 
    i3 => auxsc730,
273 
    i2 => auxsc57,
274 
    i1 => o(16),
275 
    i0 => auxsc15);
276 
  o_15 : nao2o22_x1
277 
    PORT MAP (
278 
    vss => vss,
279 
    vdd => vdd,
280 
    nq => o(15),
281 
    i3 => auxsc778,
282 
    i2 => auxsc57,
283 
    i1 => o(16),
284 
    i0 => auxsc16);
285 
  auxsc778 : o3_x2
286 
    PORT MAP (
287 
    vss => vss,
288 
    vdd => vdd,
289 
    q => auxsc778,
290 
    i2 => auxsc54,
291 
    i1 => auxsc16,
292 
    i0 => a(2));
293 
  auxsc16 : inv_x1
294 
    PORT MAP (
295 
    vss => vss,
296 
    vdd => vdd,
297 
    nq => auxsc16,
298 
    i => a(15));
299 
  auxsc730 : o3_x2
300 
    PORT MAP (
301 
    vss => vss,
302 
    vdd => vdd,
303 
    q => auxsc730,
304 
    i2 => auxsc15,
305 
    i1 => auxsc54,
306 
    i0 => a(2));
307 
  auxsc15 : inv_x1
308 
    PORT MAP (
309 
    vss => vss,
310 
    vdd => vdd,
311 
    nq => auxsc15,
312 
    i => a(14));
313 
  auxsc682 : o3_x2
314 
    PORT MAP (
315 
    vss => vss,
316 
    vdd => vdd,
317 
    q => auxsc682,
318 
    i2 => auxsc14,
319 
    i1 => auxsc54,
320 
    i0 => a(2));
321 
  auxsc14 : inv_x1
322 
    PORT MAP (
323 
    vss => vss,
324 
    vdd => vdd,
325 
    nq => auxsc14,
326 
    i => a(13));
327 
  auxsc634 : o3_x2
328 
    PORT MAP (
329 
    vss => vss,
330 
    vdd => vdd,
331 
    q => auxsc634,
332 
    i2 => auxsc13,
333 
    i1 => auxsc54,
334 
    i0 => a(2));
335 
  auxsc13 : inv_x1
336 
    PORT MAP (
337 
    vss => vss,
338 
    vdd => vdd,
339 
    nq => auxsc13,
340 
    i => a(12));
341 
  auxsc586 : o3_x2
342 
    PORT MAP (
343 
    vss => vss,
344 
    vdd => vdd,
345 
    q => auxsc586,
346 
    i2 => auxsc12,
347 
    i1 => auxsc54,
348 
    i0 => a(2));
349 
  auxsc12 : inv_x1
350 
    PORT MAP (
351 
    vss => vss,
352 
    vdd => vdd,
353 
    nq => auxsc12,
354 
    i => a(11));
355 
  auxsc538 : o3_x2
356 
    PORT MAP (
357 
    vss => vss,
358 
    vdd => vdd,
359 
    q => auxsc538,
360 
    i2 => auxsc11,
361 
    i1 => auxsc54,
362 
    i0 => a(2));
363 
  auxsc11 : inv_x1
364 
    PORT MAP (
365 
    vss => vss,
366 
    vdd => vdd,
367 
    nq => auxsc11,
368 
    i => a(10));
369 
  auxsc490 : o3_x2
370 
    PORT MAP (
371 
    vss => vss,
372 
    vdd => vdd,
373 
    q => auxsc490,
374 
    i2 => auxsc10,
375 
    i1 => auxsc54,
376 
    i0 => a(2));
377 
  auxsc10 : inv_x1
378 
    PORT MAP (
379 
    vss => vss,
380 
    vdd => vdd,
381 
    nq => auxsc10,
382 
    i => a(9));
383 
  auxsc442 : o3_x2
384 
    PORT MAP (
385 
    vss => vss,
386 
    vdd => vdd,
387 
    q => auxsc442,
388 
    i2 => auxsc9,
389 
    i1 => auxsc54,
390 
    i0 => a(2));
391 
  auxsc9 : inv_x1
392 
    PORT MAP (
393 
    vss => vss,
394 
    vdd => vdd,
395 
    nq => auxsc9,
396 
    i => a(8));
397 
  auxsc394 : o3_x2
398 
    PORT MAP (
399 
    vss => vss,
400 
    vdd => vdd,
401 
    q => auxsc394,
402 
    i2 => auxsc54,
403 
    i1 => auxsc8,
404 
    i0 => a(2));
405 
  auxsc8 : inv_x1
406 
    PORT MAP (
407 
    vss => vss,
408 
    vdd => vdd,
409 
    nq => auxsc8,
410 
    i => a(7));
411 
  auxsc346 : o3_x2
412 
    PORT MAP (
413 
    vss => vss,
414 
    vdd => vdd,
415 
    q => auxsc346,
416 
    i2 => auxsc54,
417 
    i1 => auxsc7,
418 
    i0 => a(2));
419 
  auxsc7 : inv_x1
420 
    PORT MAP (
421 
    vss => vss,
422 
    vdd => vdd,
423 
    nq => auxsc7,
424 
    i => a(6));
425 
  auxsc298 : o3_x2
426 
    PORT MAP (
427 
    vss => vss,
428 
    vdd => vdd,
429 
    q => auxsc298,
430 
    i2 => auxsc54,
431 
    i1 => auxsc6,
432 
    i0 => a(2));
433 
  auxsc6 : inv_x1
434 
    PORT MAP (
435 
    vss => vss,
436 
    vdd => vdd,
437 
    nq => auxsc6,
438 
    i => a(5));
439 
  auxsc250 : o3_x2
440 
    PORT MAP (
441 
    vss => vss,
442 
    vdd => vdd,
443 
    q => auxsc250,
444 
    i2 => auxsc54,
445 
    i1 => auxsc5,
446 
    i0 => a(2));
447 
  auxsc5 : inv_x1
448 
    PORT MAP (
449 
    vss => vss,
450 
    vdd => vdd,
451 
    nq => auxsc5,
452 
    i => a(4));
453 
  auxsc202 : o3_x2
454 
    PORT MAP (
455 
    vss => vss,
456 
    vdd => vdd,
457 
    q => auxsc202,
458 
    i2 => auxsc54,
459 
    i1 => auxsc4,
460 
    i0 => a(2));
461 
  auxsc4 : inv_x1
462 
    PORT MAP (
463 
    vss => vss,
464 
    vdd => vdd,
465 
    nq => auxsc4,
466 
    i => a(3));
467 
  auxsc154 : o3_x2
468 
    PORT MAP (
469 
    vss => vss,
470 
    vdd => vdd,
471 
    q => auxsc154,
472 
    i2 => auxsc54,
473 
    i1 => auxsc3,
474 
    i0 => a(2));
475 
  auxsc3 : inv_x1
476 
    PORT MAP (
477 
    vss => vss,
478 
    vdd => vdd,
479 
    nq => auxsc3,
480 
    i => a(2));
481 
  auxsc106 : o3_x2
482 
    PORT MAP (
483 
    vss => vss,
484 
    vdd => vdd,
485 
    q => auxsc106,
486 
    i2 => auxsc54,
487 
    i1 => auxsc2,
488 
    i0 => a(2));
489 
  auxsc2 : inv_x1
490 
    PORT MAP (
491 
    vss => vss,
492 
    vdd => vdd,
493 
    nq => auxsc2,
494 
    i => a(1));
495 
  auxsc58 : o3_x2
496 
    PORT MAP (
497 
    vss => vss,
498 
    vdd => vdd,
499 
    q => auxsc58,
500 
    i2 => auxsc1,
501 
    i1 => auxsc54,
502 
    i0 => a(2));
503 
  auxsc54 : o2_x2
504 
    PORT MAP (
505 
    vss => vss,
506 
    vdd => vdd,
507 
    q => auxsc54,
508 
    i1 => a(1),
509 
    i0 => a(0));
510 
  auxsc57 : o4_x2
511 
    PORT MAP (
512 
    vss => vss,
513 
    vdd => vdd,
514 
    q => auxsc57,
515 
    i3 => auxsc50,
516 
    i2 => auxsc51,
517 
    i1 => auxsc52,
518 
    i0 => a(15));
519 
  auxsc50 : o4_x2
520 
    PORT MAP (
521 
    vss => vss,
522 
    vdd => vdd,
523 
    q => auxsc50,
524 
    i3 => a(6),
525 
    i2 => a(5),
526 
    i1 => a(4),
527 
    i0 => a(3));
528 
  auxsc51 : o4_x2
529 
    PORT MAP (
530 
    vss => vss,
531 
    vdd => vdd,
532 
    q => auxsc51,
533 
    i3 => a(10),
534 
    i2 => a(9),
535 
    i1 => a(8),
536 
    i0 => a(7));
537 
  auxsc52 : o4_x2
538 
    PORT MAP (
539 
    vss => vss,
540 
    vdd => vdd,
541 
    q => auxsc52,
542 
    i3 => a(14),
543 
    i2 => a(13),
544 
    i1 => a(12),
545 
    i0 => a(11));
546 
  auxsc17 : a4_x2
547 
    PORT MAP (
548 
    vss => vss,
549 
    vdd => vdd,
550 
    q => o(16),
551 
    i3 => auxsc40,
552 
    i2 => auxsc39,
553 
    i1 => auxsc38,
554 
    i0 => auxsc37);
555 
  auxsc40 : no4_x1
556 
    PORT MAP (
557 
    vss => vss,
558 
    vdd => vdd,
559 
    nq => auxsc40,
560 
    i3 => a(3),
561 
    i2 => a(2),
562 
    i1 => a(1),
563 
    i0 => a(0));
564 
  auxsc39 : no4_x1
565 
    PORT MAP (
566 
    vss => vss,
567 
    vdd => vdd,
568 
    nq => auxsc39,
569 
    i3 => a(7),
570 
    i2 => a(6),
571 
    i1 => a(5),
572 
    i0 => a(4));
573 
  auxsc38 : no4_x1
574 
    PORT MAP (
575 
    vss => vss,
576 
    vdd => vdd,
577 
    nq => auxsc38,
578 
    i3 => a(11),
579 
    i2 => a(10),
580 
    i1 => a(9),
581 
    i0 => a(8));
582 
  auxsc37 : no4_x1
583 
    PORT MAP (
584 
    vss => vss,
585 
    vdd => vdd,
586 
    nq => auxsc37,
587 
    i3 => a(15),
588 
    i2 => a(14),
589 
    i1 => a(13),
590 
    i0 => a(12));
591 
  auxsc1 : inv_x1
592 
    PORT MAP (
593 
    vss => vss,
594 
    vdd => vdd,
595 
    nq => auxsc1,
596 
    i => a(0));
597 
 
598 
end VST;

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