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[/] [structural_vhdl/] [trunk/] [key_regulator/] [count3.vst] - Blame information for rev 4

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-- VHDL structural description generated from `count3`
--              date : Thu Aug  2 09:53:14 2001
 
 
-- Entity Declaration
 
ENTITY count3 IS
  PORT (
  clk : in BIT; -- clk
  rst : in BIT; -- rst
  q : out BIT_VECTOR (2 DOWNTO 0);      -- q
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END count3;
 
-- Architecture Declaration
 
ARCHITECTURE VST OF count3 IS
  COMPONENT no2_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT a2_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT a3_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT nxr2_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT na2_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT xr2_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT an12_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT inv_x1
    port (
    i : in BIT; -- i
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT o2_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT sff1_x4
    port (
    ck : in BIT;        -- ck
    i : in BIT; -- i
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  SIGNAL aux9_a : BIT;  -- aux9_a
  SIGNAL auxsc12 : BIT; -- auxsc12
  SIGNAL auxsc13 : BIT; -- auxsc13
  SIGNAL auxsc6 : BIT;  -- auxsc6
  SIGNAL auxsc26 : BIT; -- auxsc26
  SIGNAL auxsc25 : BIT; -- auxsc25
  SIGNAL auxsc31 : BIT; -- auxsc31
  SIGNAL auxsc29 : BIT; -- auxsc29
  SIGNAL auxsc7 : BIT;  -- auxsc7
  SIGNAL auxsc9 : BIT;  -- auxsc9
  SIGNAL auxsc3 : BIT;  -- auxsc3
  SIGNAL auxsc14 : BIT; -- auxsc14
  SIGNAL auxsc15 : BIT; -- auxsc15
  SIGNAL auxsc18 : BIT; -- auxsc18
  SIGNAL auxreg3 : BIT; -- auxreg3
  SIGNAL auxreg2 : BIT; -- auxreg2
  SIGNAL auxreg1 : BIT; -- auxreg1
 
BEGIN
 
  q_0 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => q(0),
    i1 => auxreg3,
    i0 => rst);
  q_1 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => q(1),
    i1 => auxsc25,
    i0 => auxsc13);
  q_2 : a3_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => q(2),
    i2 => auxsc29,
    i1 => auxsc31,
    i0 => auxsc13);
  auxsc18 : o2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc18,
    i1 => rst,
    i0 => auxsc12);
  auxsc15 : a3_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc15,
    i2 => aux9_a,
    i1 => auxsc14,
    i0 => auxsc13);
  auxsc14 : o2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc14,
    i1 => auxreg3,
    i0 => auxreg2);
  auxsc3 : o2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc3,
    i1 => auxsc9,
    i0 => rst);
  auxsc9 : nxr2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc9,
    i1 => auxsc7,
    i0 => auxreg2);
  auxsc7 : nxr2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc7,
    i1 => auxreg3,
    i0 => auxsc6);
  auxsc29 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc29,
    i1 => auxreg2,
    i0 => auxsc12);
  auxsc31 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc31,
    i1 => auxreg1,
    i0 => auxreg3);
  auxsc25 : xr2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc25,
    i1 => auxsc26,
    i0 => auxsc6);
  auxsc26 : an12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc26,
    i1 => auxreg2,
    i0 => auxsc12);
  auxsc6 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc6,
    i => auxreg1);
  auxsc13 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc13,
    i => rst);
  auxsc12 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc12,
    i => auxreg3);
  aux9_a : o2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => aux9_a,
    i1 => auxreg1,
    i0 => auxsc12);
  current_state_0 : sff1_x4
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxreg1,
    i => auxsc3,
    ck => clk);
  current_state_1 : sff1_x4
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxreg2,
    i => auxsc15,
    ck => clk);
  current_state_2 : sff1_x4
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxreg3,
    i => auxsc18,
    ck => clk);
 
end VST;

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Subversion Repositories structural_vhdl

[/] [structural_vhdl/] [trunk/] [key_regulator/] [count3.vst] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	marta	-- VHDL structural description generated from `count3`
2			`-- date : Thu Aug 2 09:53:14 2001`
3
4
5			`-- Entity Declaration`
6
7			`ENTITY count3 IS`
8			`PORT (`
9			`clk : in BIT; -- clk`
10			`rst : in BIT; -- rst`
11			`q : out BIT_VECTOR (2 DOWNTO 0); -- q`
12			`vdd : in BIT; -- vdd`
13			`vss : in BIT -- vss`
14			`);`
15			`END count3;`
16
17			`-- Architecture Declaration`
18
19			`ARCHITECTURE VST OF count3 IS`
20			`COMPONENT no2_x1`
21			`port (`
22			`i0 : in BIT; -- i0`
23			`i1 : in BIT; -- i1`
24			`nq : out BIT; -- nq`
25			`vdd : in BIT; -- vdd`
26			`vss : in BIT -- vss`
27			`);`
28			`END COMPONENT;`
29
30			`COMPONENT a2_x2`
31			`port (`
32			`i0 : in BIT; -- i0`
33			`i1 : in BIT; -- i1`
34			`q : out BIT; -- q`
35			`vdd : in BIT; -- vdd`
36			`vss : in BIT -- vss`
37			`);`
38			`END COMPONENT;`
39
40			`COMPONENT a3_x2`
41			`port (`
42			`i0 : in BIT; -- i0`
43			`i1 : in BIT; -- i1`
44			`i2 : in BIT; -- i2`
45			`q : out BIT; -- q`
46			`vdd : in BIT; -- vdd`
47			`vss : in BIT -- vss`
48			`);`
49			`END COMPONENT;`
50
51			`COMPONENT nxr2_x1`
52			`port (`
53			`i0 : in BIT; -- i0`
54			`i1 : in BIT; -- i1`
55			`nq : out BIT; -- nq`
56			`vdd : in BIT; -- vdd`
57			`vss : in BIT -- vss`
58			`);`
59			`END COMPONENT;`
60
61			`COMPONENT na2_x1`
62			`port (`
63			`i0 : in BIT; -- i0`
64			`i1 : in BIT; -- i1`
65			`nq : out BIT; -- nq`
66			`vdd : in BIT; -- vdd`
67			`vss : in BIT -- vss`
68			`);`
69			`END COMPONENT;`
70
71			`COMPONENT xr2_x1`
72			`port (`
73			`i0 : in BIT; -- i0`
74			`i1 : in BIT; -- i1`
75			`q : out BIT; -- q`
76			`vdd : in BIT; -- vdd`
77			`vss : in BIT -- vss`
78			`);`
79			`END COMPONENT;`
80
81			`COMPONENT an12_x1`
82			`port (`
83			`i0 : in BIT; -- i0`
84			`i1 : in BIT; -- i1`
85			`q : out BIT; -- q`
86			`vdd : in BIT; -- vdd`
87			`vss : in BIT -- vss`
88			`);`
89			`END COMPONENT;`
90
91			`COMPONENT inv_x1`
92			`port (`
93			`i : in BIT; -- i`
94			`nq : out BIT; -- nq`
95			`vdd : in BIT; -- vdd`
96			`vss : in BIT -- vss`
97			`);`
98			`END COMPONENT;`
99
100			`COMPONENT o2_x2`
101			`port (`
102			`i0 : in BIT; -- i0`
103			`i1 : in BIT; -- i1`
104			`q : out BIT; -- q`
105			`vdd : in BIT; -- vdd`
106			`vss : in BIT -- vss`
107			`);`
108			`END COMPONENT;`
109
110			`COMPONENT sff1_x4`
111			`port (`
112			`ck : in BIT; -- ck`
113			`i : in BIT; -- i`
114			`q : out BIT; -- q`
115			`vdd : in BIT; -- vdd`
116			`vss : in BIT -- vss`
117			`);`
118			`END COMPONENT;`
119
120			`SIGNAL aux9_a : BIT; -- aux9_a`
121			`SIGNAL auxsc12 : BIT; -- auxsc12`
122			`SIGNAL auxsc13 : BIT; -- auxsc13`
123			`SIGNAL auxsc6 : BIT; -- auxsc6`
124			`SIGNAL auxsc26 : BIT; -- auxsc26`
125			`SIGNAL auxsc25 : BIT; -- auxsc25`
126			`SIGNAL auxsc31 : BIT; -- auxsc31`
127			`SIGNAL auxsc29 : BIT; -- auxsc29`
128			`SIGNAL auxsc7 : BIT; -- auxsc7`
129			`SIGNAL auxsc9 : BIT; -- auxsc9`
130			`SIGNAL auxsc3 : BIT; -- auxsc3`
131			`SIGNAL auxsc14 : BIT; -- auxsc14`
132			`SIGNAL auxsc15 : BIT; -- auxsc15`
133			`SIGNAL auxsc18 : BIT; -- auxsc18`
134			`SIGNAL auxreg3 : BIT; -- auxreg3`
135			`SIGNAL auxreg2 : BIT; -- auxreg2`
136			`SIGNAL auxreg1 : BIT; -- auxreg1`
137
138			`BEGIN`
139
140			`q_0 : no2_x1`
141			`PORT MAP (`
142			`vss => vss,`
143			`vdd => vdd,`
144			`nq => q(0),`
145			`i1 => auxreg3,`
146			`i0 => rst);`
147			`q_1 : a2_x2`
148			`PORT MAP (`
149			`vss => vss,`
150			`vdd => vdd,`
151			`q => q(1),`
152			`i1 => auxsc25,`
153			`i0 => auxsc13);`
154			`q_2 : a3_x2`
155			`PORT MAP (`
156			`vss => vss,`
157			`vdd => vdd,`
158			`q => q(2),`
159			`i2 => auxsc29,`
160			`i1 => auxsc31,`
161			`i0 => auxsc13);`
162			`auxsc18 : o2_x2`
163			`PORT MAP (`
164			`vss => vss,`
165			`vdd => vdd,`
166			`q => auxsc18,`
167			`i1 => rst,`
168			`i0 => auxsc12);`
169			`auxsc15 : a3_x2`
170			`PORT MAP (`
171			`vss => vss,`
172			`vdd => vdd,`
173			`q => auxsc15,`
174			`i2 => aux9_a,`
175			`i1 => auxsc14,`
176			`i0 => auxsc13);`
177			`auxsc14 : o2_x2`
178			`PORT MAP (`
179			`vss => vss,`
180			`vdd => vdd,`
181			`q => auxsc14,`
182			`i1 => auxreg3,`
183			`i0 => auxreg2);`
184			`auxsc3 : o2_x2`
185			`PORT MAP (`
186			`vss => vss,`
187			`vdd => vdd,`
188			`q => auxsc3,`
189			`i1 => auxsc9,`
190			`i0 => rst);`
191			`auxsc9 : nxr2_x1`
192			`PORT MAP (`
193			`vss => vss,`
194			`vdd => vdd,`
195			`nq => auxsc9,`
196			`i1 => auxsc7,`
197			`i0 => auxreg2);`
198			`auxsc7 : nxr2_x1`
199			`PORT MAP (`
200			`vss => vss,`
201			`vdd => vdd,`
202			`nq => auxsc7,`
203			`i1 => auxreg3,`
204			`i0 => auxsc6);`
205			`auxsc29 : na2_x1`
206			`PORT MAP (`
207			`vss => vss,`
208			`vdd => vdd,`
209			`nq => auxsc29,`
210			`i1 => auxreg2,`
211			`i0 => auxsc12);`
212			`auxsc31 : na2_x1`
213			`PORT MAP (`
214			`vss => vss,`
215			`vdd => vdd,`
216			`nq => auxsc31,`
217			`i1 => auxreg1,`
218			`i0 => auxreg3);`
219			`auxsc25 : xr2_x1`
220			`PORT MAP (`
221			`vss => vss,`
222			`vdd => vdd,`
223			`q => auxsc25,`
224			`i1 => auxsc26,`
225			`i0 => auxsc6);`
226			`auxsc26 : an12_x1`
227			`PORT MAP (`
228			`vss => vss,`
229			`vdd => vdd,`
230			`q => auxsc26,`
231			`i1 => auxreg2,`
232			`i0 => auxsc12);`
233			`auxsc6 : inv_x1`
234			`PORT MAP (`
235			`vss => vss,`
236			`vdd => vdd,`
237			`nq => auxsc6,`
238			`i => auxreg1);`
239			`auxsc13 : inv_x1`
240			`PORT MAP (`
241			`vss => vss,`
242			`vdd => vdd,`
243			`nq => auxsc13,`
244			`i => rst);`
245			`auxsc12 : inv_x1`
246			`PORT MAP (`
247			`vss => vss,`
248			`vdd => vdd,`
249			`nq => auxsc12,`
250			`i => auxreg3);`
251			`aux9_a : o2_x2`
252			`PORT MAP (`
253			`vss => vss,`
254			`vdd => vdd,`
255			`q => aux9_a,`
256			`i1 => auxreg1,`
257			`i0 => auxsc12);`
258			`current_state_0 : sff1_x4`
259			`PORT MAP (`
260			`vss => vss,`
261			`vdd => vdd,`
262			`q => auxreg1,`
263			`i => auxsc3,`
264			`ck => clk);`
265			`current_state_1 : sff1_x4`
266			`PORT MAP (`
267			`vss => vss,`
268			`vdd => vdd,`
269			`q => auxreg2,`
270			`i => auxsc15,`
271			`ck => clk);`
272			`current_state_2 : sff1_x4`
273			`PORT MAP (`
274			`vss => vss,`
275			`vdd => vdd,`
276			`q => auxreg3,`
277			`i => auxsc18,`
278			`ck => clk);`
279
280			`end VST;`