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[/] [structural_vhdl/] [trunk/] [key_regulator/] [count5_latch.vst] - Blame information for rev 4

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-- VHDL structural description generated from `count5_latch`
--              date : Thu Aug  2 10:04:30 2001
 
 
-- Entity Declaration
 
ENTITY count5_latch IS
  PORT (
  clk : in BIT; -- clk
  en : in BIT;  -- en
  rst : in BIT; -- rst
  q : out BIT_VECTOR (4 DOWNTO 0);      -- q
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END count5_latch;
 
-- Architecture Declaration
 
ARCHITECTURE VST OF count5_latch IS
  COMPONENT count5
    port (
    clk : in BIT;       -- clk
    rst : in BIT;       -- rst
    q : out BIT_VECTOR(4 DOWNTO 0);     -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT latch
    port (
    a : in BIT; -- a
    en : in BIT;        -- en
    b : inout BIT;      -- b
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  SIGNAL p_0 : BIT;     -- p 0
  SIGNAL p_1 : BIT;     -- p 1
  SIGNAL p_2 : BIT;     -- p 2
  SIGNAL p_3 : BIT;     -- p 3
  SIGNAL p_4 : BIT;     -- p 4
  SIGNAL vd : BIT;      -- vd
 
BEGIN
 
  count1 : count5
    PORT MAP (
    vss => vss,
    vdd => vd,
    q => p_4& p_3& p_2& p_1& p_0,
    rst => rst,
    clk => clk);
  latch0 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => q(0),
    en => en,
    a => p_0);
  latch1 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => q(1),
    en => en,
    a => p_1);
  latch2 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => q(2),
    en => en,
    a => p_2);
  latch3 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => q(3),
    en => en,
    a => p_3);
  latch4 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => q(4),
    en => en,
    a => p_4);
 
end VST;

Line No.	Rev	Author	Line
1	2	marta	-- VHDL structural description generated from `count5_latch`
2			`-- date : Thu Aug 2 10:04:30 2001`
3
4
5			`-- Entity Declaration`
6
7			`ENTITY count5_latch IS`
8			`PORT (`
9			`clk : in BIT; -- clk`
10			`en : in BIT; -- en`
11			`rst : in BIT; -- rst`
12			`q : out BIT_VECTOR (4 DOWNTO 0); -- q`
13			`vdd : in BIT; -- vdd`
14			`vss : in BIT -- vss`
15			`);`
16			`END count5_latch;`
17
18			`-- Architecture Declaration`
19
20			`ARCHITECTURE VST OF count5_latch IS`
21			`COMPONENT count5`
22			`port (`
23			`clk : in BIT; -- clk`
24			`rst : in BIT; -- rst`
25			`q : out BIT_VECTOR(4 DOWNTO 0); -- q`
26			`vdd : in BIT; -- vdd`
27			`vss : in BIT -- vss`
28			`);`
29			`END COMPONENT;`
30
31			`COMPONENT latch`
32			`port (`
33			`a : in BIT; -- a`
34			`en : in BIT; -- en`
35			`b : inout BIT; -- b`
36			`vdd : in BIT; -- vdd`
37			`vss : in BIT -- vss`
38			`);`
39			`END COMPONENT;`
40
41			`SIGNAL p_0 : BIT; -- p 0`
42			`SIGNAL p_1 : BIT; -- p 1`
43			`SIGNAL p_2 : BIT; -- p 2`
44			`SIGNAL p_3 : BIT; -- p 3`
45			`SIGNAL p_4 : BIT; -- p 4`
46			`SIGNAL vd : BIT; -- vd`
47
48			`BEGIN`
49
50			`count1 : count5`
51			`PORT MAP (`
52			`vss => vss,`
53			`vdd => vd,`
54			`q => p_4& p_3& p_2& p_1& p_0,`
55			`rst => rst,`
56			`clk => clk);`
57			`latch0 : latch`
58			`PORT MAP (`
59			`vss => vss,`
60			`vdd => vdd,`
61			`b => q(0),`
62			`en => en,`
63			`a => p_0);`
64			`latch1 : latch`
65			`PORT MAP (`
66			`vss => vss,`
67			`vdd => vdd,`
68			`b => q(1),`
69			`en => en,`
70			`a => p_1);`
71			`latch2 : latch`
72			`PORT MAP (`
73			`vss => vss,`
74			`vdd => vdd,`
75			`b => q(2),`
76			`en => en,`
77			`a => p_2);`
78			`latch3 : latch`
79			`PORT MAP (`
80			`vss => vss,`
81			`vdd => vdd,`
82			`b => q(3),`
83			`en => en,`
84			`a => p_3);`
85			`latch4 : latch`
86			`PORT MAP (`
87			`vss => vss,`
88			`vdd => vdd,`
89			`b => q(4),`
90			`en => en,`
91			`a => p_4);`
92
93			`end VST;`

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[/] [structural_vhdl/] [trunk/] [key_regulator/] [count5_latch.vst] - Blame information for rev 4