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[/] [structural_vhdl/] [trunk/] [key_regulator/] [ctr_enkey.vst] - Blame information for rev 4

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-- VHDL structural description generated from `ctr_enkey`
--              date : Tue Jul 31 14:22:06 2001
 
 
-- Entity Declaration
 
ENTITY ctr_enkey IS
  PORT (
  clk : in BIT; -- clk
  rst : in BIT; -- rst
  start : in BIT;       -- start
  count : in BIT_VECTOR (2 DOWNTO 0);   -- count
  en_shft : out BIT;    -- en_shft
  en_count : inout BIT; -- en_count
  sel1 : out BIT;       -- sel1
  sel2 : out BIT;       -- sel2
  c_count : out BIT;    -- c_count
  finish : out BIT;     -- finish
  en_out : out BIT;     -- en_out
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END ctr_enkey;
 
-- Architecture Declaration
 
ARCHITECTURE VST OF ctr_enkey IS
  COMPONENT zero_x0
    port (
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT no3_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT no4_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    i3 : in BIT;        -- i3
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT o4_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    i3 : in BIT;        -- i3
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT an12_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT o3_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT na3_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT nao22_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT na2_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT on12_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT no2_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT inv_x1
    port (
    i : in BIT; -- i
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT oa22_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT o2_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT a2_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT a3_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT a4_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    i3 : in BIT;        -- i3
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT sff1_x4
    port (
    ck : in BIT;        -- ck
    i : in BIT; -- i
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  SIGNAL aux40_a : BIT; -- aux40_a
  SIGNAL aux32_a : BIT; -- aux32_a
  SIGNAL aux33_a : BIT; -- aux33_a
  SIGNAL aux35_a : BIT; -- aux35_a
  SIGNAL aux38_a : BIT; -- aux38_a
  SIGNAL aux44_a : BIT; -- aux44_a
  SIGNAL auxsc58 : BIT; -- auxsc58
  SIGNAL auxsc1 : BIT;  -- auxsc1
  SIGNAL auxsc16 : BIT; -- auxsc16
  SIGNAL auxsc39 : BIT; -- auxsc39
  SIGNAL auxsc15 : BIT; -- auxsc15
  SIGNAL auxsc38 : BIT; -- auxsc38
  SIGNAL auxsc65 : BIT; -- auxsc65
  SIGNAL auxsc3 : BIT;  -- auxsc3
  SIGNAL auxsc83 : BIT; -- auxsc83
  SIGNAL auxsc69 : BIT; -- auxsc69
  SIGNAL auxsc80 : BIT; -- auxsc80
  SIGNAL auxsc81 : BIT; -- auxsc81
  SIGNAL auxsc78 : BIT; -- auxsc78
  SIGNAL auxsc79 : BIT; -- auxsc79
  SIGNAL auxsc82 : BIT; -- auxsc82
  SIGNAL auxsc77 : BIT; -- auxsc77
  SIGNAL auxsc89 : BIT; -- auxsc89
  SIGNAL auxsc85 : BIT; -- auxsc85
  SIGNAL auxsc42 : BIT; -- auxsc42
  SIGNAL auxsc88 : BIT; -- auxsc88
  SIGNAL auxsc26 : BIT; -- auxsc26
  SIGNAL auxsc100 : BIT;        -- auxsc100
  SIGNAL auxsc95 : BIT; -- auxsc95
  SIGNAL auxsc101 : BIT;        -- auxsc101
  SIGNAL auxsc97 : BIT; -- auxsc97
  SIGNAL auxsc119 : BIT;        -- auxsc119
  SIGNAL auxsc120 : BIT;        -- auxsc120
  SIGNAL auxsc118 : BIT;        -- auxsc118
  SIGNAL auxsc121 : BIT;        -- auxsc121
  SIGNAL auxsc35 : BIT; -- auxsc35
  SIGNAL auxsc111 : BIT;        -- auxsc111
  SIGNAL auxsc112 : BIT;        -- auxsc112
  SIGNAL auxsc109 : BIT;        -- auxsc109
  SIGNAL auxsc9 : BIT;  -- auxsc9
  SIGNAL auxsc10 : BIT; -- auxsc10
  SIGNAL auxsc4 : BIT;  -- auxsc4
  SIGNAL auxsc11 : BIT; -- auxsc11
  SIGNAL auxsc12 : BIT; -- auxsc12
  SIGNAL auxsc13 : BIT; -- auxsc13
  SIGNAL auxsc31 : BIT; -- auxsc31
  SIGNAL auxsc27 : BIT; -- auxsc27
  SIGNAL auxsc28 : BIT; -- auxsc28
  SIGNAL auxsc32 : BIT; -- auxsc32
  SIGNAL auxsc29 : BIT; -- auxsc29
  SIGNAL auxsc30 : BIT; -- auxsc30
  SIGNAL auxsc33 : BIT; -- auxsc33
  SIGNAL auxsc34 : BIT; -- auxsc34
  SIGNAL auxsc49 : BIT; -- auxsc49
  SIGNAL auxsc50 : BIT; -- auxsc50
  SIGNAL auxsc51 : BIT; -- auxsc51
  SIGNAL auxsc46 : BIT; -- auxsc46
  SIGNAL auxsc52 : BIT; -- auxsc52
  SIGNAL auxsc59 : BIT; -- auxsc59
  SIGNAL auxsc64 : BIT; -- auxsc64
  SIGNAL auxreg4 : BIT; -- auxreg4
  SIGNAL auxreg3 : BIT; -- auxreg3
  SIGNAL auxreg2 : BIT; -- auxreg2
  SIGNAL auxreg1 : BIT; -- auxreg1
 
BEGIN
 
  en_out : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => en_out,
    i1 => auxsc88,
    i0 => auxsc65);
  finish : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => finish,
    i1 => auxsc97,
    i0 => auxsc65);
  c_count : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => c_count,
    i1 => auxsc118,
    i0 => auxsc65);
  sel2 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => sel2,
    i => auxsc121);
  sel1 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => sel1);
  en_shft : a3_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => en_shft,
    i2 => auxsc109,
    i1 => auxsc95,
    i0 => auxsc65);
  auxsc64 : o4_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc64,
    i3 => auxreg3,
    i2 => aux44_a,
    i1 => auxsc59,
    i0 => rst);
  auxsc59 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc59,
    i1 => auxreg1,
    i0 => auxreg4);
  auxsc52 : an12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc52,
    i1 => auxsc46,
    i0 => rst);
  auxsc46 : o3_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc46,
    i2 => auxsc51,
    i1 => auxsc50,
    i0 => auxsc49);
  auxsc51 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc51,
    i1 => auxsc42,
    i0 => auxreg3);
  auxsc50 : an12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc50,
    i1 => aux33_a,
    i0 => auxsc3);
  auxsc49 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc49,
    i1 => auxsc3,
    i0 => aux32_a);
  auxsc34 : no4_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc34,
    i3 => auxsc33,
    i2 => auxsc32,
    i1 => auxsc31,
    i0 => rst);
  auxsc33 : a3_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc33,
    i2 => auxreg1,
    i1 => auxsc30,
    i0 => auxsc26);
  auxsc30 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc30,
    i => auxsc29);
  auxsc29 : an12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc29,
    i1 => auxreg4,
    i0 => auxreg3);
  auxsc32 : no3_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc32,
    i2 => auxreg1,
    i1 => auxsc28,
    i0 => auxreg4);
  auxsc28 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc28,
    i1 => auxsc27,
    i0 => auxsc26);
  auxsc27 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc27,
    i => auxreg3);
  auxsc31 : no4_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc31,
    i3 => auxreg1,
    i2 => aux40_a,
    i1 => aux38_a,
    i0 => auxsc1);
  auxsc13 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc13,
    i1 => auxsc12,
    i0 => rst);
  auxsc12 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc12,
    i2 => auxsc11,
    i1 => auxsc4,
    i0 => auxsc10);
  auxsc11 : o4_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc11,
    i3 => aux38_a,
    i2 => aux35_a,
    i1 => auxsc1,
    i0 => auxreg1);
  auxsc4 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc4,
    i1 => auxsc1,
    i0 => auxreg2);
  auxsc10 : o2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc10,
    i1 => auxreg3,
    i0 => auxsc3);
  auxsc9 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc9,
    i => clk);
  auxsc109 : oa22_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc109,
    i2 => auxsc112,
    i1 => auxsc1,
    i0 => auxsc26);
  auxsc112 : an12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc112,
    i1 => auxreg4,
    i0 => auxsc111);
  auxsc111 : o3_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc111,
    i2 => auxsc80,
    i1 => auxsc58,
    i0 => auxsc35);
  auxsc35 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc35,
    i => count(0));
  auxsc121 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc121,
    i => en_count);
  auxsc118 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc118,
    i2 => auxsc120,
    i1 => auxsc119,
    i0 => auxreg1);
  auxsc120 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc120,
    i1 => auxreg4,
    i0 => auxreg1);
  auxsc119 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc119,
    i2 => auxreg3,
    i1 => auxreg4,
    i0 => auxsc26);
  auxsc97 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc97,
    i2 => auxsc101,
    i1 => auxreg4,
    i0 => auxsc100);
  auxsc101 : na3_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc101,
    i2 => auxreg4,
    i1 => auxsc95,
    i0 => aux35_a);
  auxsc95 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc95,
    i1 => auxreg3,
    i0 => auxreg1);
  auxsc100 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc100,
    i1 => auxsc26,
    i0 => auxreg1);
  auxsc26 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc26,
    i => auxreg2);
  auxsc88 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc88,
    i2 => auxsc42,
    i1 => auxsc85,
    i0 => auxsc89);
  auxsc42 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc42,
    i1 => auxreg2,
    i0 => auxsc1);
  auxsc85 : o2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc85,
    i1 => auxreg3,
    i0 => auxreg1);
  auxsc89 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc89,
    i1 => auxsc38,
    i0 => auxsc16);
  auxsc77 : o2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc77,
    i1 => auxsc82,
    i0 => auxsc81);
  auxsc82 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc82,
    i1 => auxreg4,
    i0 => auxsc79);
  auxsc79 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc79,
    i => auxsc78);
  auxsc78 : on12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc78,
    i1 => auxreg3,
    i0 => auxsc3);
  auxsc81 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc81,
    i1 => auxsc80,
    i0 => auxsc58);
  auxsc80 : o2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc80,
    i1 => count(2),
    i0 => count(1));
  auxsc69 : o2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc69,
    i1 => auxreg4,
    i0 => auxsc83);
  auxsc83 : o2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc83,
    i1 => auxreg2,
    i0 => auxsc3);
  auxsc3 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc3,
    i => auxreg1);
  auxsc65 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc65,
    i => rst);
  auxsc38 : a4_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc38,
    i3 => auxsc15,
    i2 => auxsc39,
    i1 => start,
    i0 => auxreg4);
  auxsc15 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc15,
    i => count(2));
  auxsc39 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc39,
    i => count(0));
  auxsc16 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc16,
    i => count(1));
  auxsc1 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc1,
    i => auxreg4);
  auxsc58 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc58,
    i => start);
  aux44_a : oa22_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => aux44_a,
    i2 => auxreg2,
    i1 => auxsc58,
    i0 => auxreg4);
  aux38_a : o2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => aux38_a,
    i1 => auxreg3,
    i0 => auxreg2);
  aux35_a : a4_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => aux35_a,
    i3 => start,
    i2 => count(2),
    i1 => count(1),
    i0 => count(0));
  aux33_a : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => aux33_a,
    i1 => auxsc1,
    i0 => auxreg2);
  aux32_a : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => aux32_a,
    i1 => auxsc38,
    i0 => auxsc16);
  auxinit1_a : a3_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => en_count,
    i2 => auxsc77,
    i1 => auxsc69,
    i0 => auxsc65);
  aux40_a : a4_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => aux40_a,
    i3 => auxsc15,
    i2 => auxsc16,
    i1 => start,
    i0 => count(0));
  current_state_0 : sff1_x4
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxreg1,
    i => auxsc13,
    ck => auxsc9);
  current_state_1 : sff1_x4
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxreg2,
    i => auxsc34,
    ck => auxsc9);
  current_state_2 : sff1_x4
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxreg3,
    i => auxsc52,
    ck => auxsc9);
  current_state_3 : sff1_x4
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxreg4,
    i => auxsc64,
    ck => auxsc9);
 
end VST;

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[/] [structural_vhdl/] [trunk/] [key_regulator/] [ctr_enkey.vst] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	marta	-- VHDL structural description generated from `ctr_enkey`
2			`-- date : Tue Jul 31 14:22:06 2001`
3
4
5			`-- Entity Declaration`
6
7			`ENTITY ctr_enkey IS`
8			`PORT (`
9			`clk : in BIT; -- clk`
10			`rst : in BIT; -- rst`
11			`start : in BIT; -- start`
12			`count : in BIT_VECTOR (2 DOWNTO 0); -- count`
13			`en_shft : out BIT; -- en_shft`
14			`en_count : inout BIT; -- en_count`
15			`sel1 : out BIT; -- sel1`
16			`sel2 : out BIT; -- sel2`
17			`c_count : out BIT; -- c_count`
18			`finish : out BIT; -- finish`
19			`en_out : out BIT; -- en_out`
20			`vdd : in BIT; -- vdd`
21			`vss : in BIT -- vss`
22			`);`
23			`END ctr_enkey;`
24
25			`-- Architecture Declaration`
26
27			`ARCHITECTURE VST OF ctr_enkey IS`
28			`COMPONENT zero_x0`
29			`port (`
30			`nq : out BIT; -- nq`
31			`vdd : in BIT; -- vdd`
32			`vss : in BIT -- vss`
33			`);`
34			`END COMPONENT;`
35
36			`COMPONENT no3_x1`
37			`port (`
38			`i0 : in BIT; -- i0`
39			`i1 : in BIT; -- i1`
40			`i2 : in BIT; -- i2`
41			`nq : out BIT; -- nq`
42			`vdd : in BIT; -- vdd`
43			`vss : in BIT -- vss`
44			`);`
45			`END COMPONENT;`
46
47			`COMPONENT no4_x1`
48			`port (`
49			`i0 : in BIT; -- i0`
50			`i1 : in BIT; -- i1`
51			`i2 : in BIT; -- i2`
52			`i3 : in BIT; -- i3`
53			`nq : out BIT; -- nq`
54			`vdd : in BIT; -- vdd`
55			`vss : in BIT -- vss`
56			`);`
57			`END COMPONENT;`
58
59			`COMPONENT o4_x2`
60			`port (`
61			`i0 : in BIT; -- i0`
62			`i1 : in BIT; -- i1`
63			`i2 : in BIT; -- i2`
64			`i3 : in BIT; -- i3`
65			`q : out BIT; -- q`
66			`vdd : in BIT; -- vdd`
67			`vss : in BIT -- vss`
68			`);`
69			`END COMPONENT;`
70
71			`COMPONENT an12_x1`
72			`port (`
73			`i0 : in BIT; -- i0`
74			`i1 : in BIT; -- i1`
75			`q : out BIT; -- q`
76			`vdd : in BIT; -- vdd`
77			`vss : in BIT -- vss`
78			`);`
79			`END COMPONENT;`
80
81			`COMPONENT o3_x2`
82			`port (`
83			`i0 : in BIT; -- i0`
84			`i1 : in BIT; -- i1`
85			`i2 : in BIT; -- i2`
86			`q : out BIT; -- q`
87			`vdd : in BIT; -- vdd`
88			`vss : in BIT -- vss`
89			`);`
90			`END COMPONENT;`
91
92			`COMPONENT na3_x1`
93			`port (`
94			`i0 : in BIT; -- i0`
95			`i1 : in BIT; -- i1`
96			`i2 : in BIT; -- i2`
97			`nq : out BIT; -- nq`
98			`vdd : in BIT; -- vdd`
99			`vss : in BIT -- vss`
100			`);`
101			`END COMPONENT;`
102
103			`COMPONENT nao22_x1`
104			`port (`
105			`i0 : in BIT; -- i0`
106			`i1 : in BIT; -- i1`
107			`i2 : in BIT; -- i2`
108			`nq : out BIT; -- nq`
109			`vdd : in BIT; -- vdd`
110			`vss : in BIT -- vss`
111			`);`
112			`END COMPONENT;`
113
114			`COMPONENT na2_x1`
115			`port (`
116			`i0 : in BIT; -- i0`
117			`i1 : in BIT; -- i1`
118			`nq : out BIT; -- nq`
119			`vdd : in BIT; -- vdd`
120			`vss : in BIT -- vss`
121			`);`
122			`END COMPONENT;`
123
124			`COMPONENT on12_x1`
125			`port (`
126			`i0 : in BIT; -- i0`
127			`i1 : in BIT; -- i1`
128			`q : out BIT; -- q`
129			`vdd : in BIT; -- vdd`
130			`vss : in BIT -- vss`
131			`);`
132			`END COMPONENT;`
133
134			`COMPONENT no2_x1`
135			`port (`
136			`i0 : in BIT; -- i0`
137			`i1 : in BIT; -- i1`
138			`nq : out BIT; -- nq`
139			`vdd : in BIT; -- vdd`
140			`vss : in BIT -- vss`
141			`);`
142			`END COMPONENT;`
143
144			`COMPONENT inv_x1`
145			`port (`
146			`i : in BIT; -- i`
147			`nq : out BIT; -- nq`
148			`vdd : in BIT; -- vdd`
149			`vss : in BIT -- vss`
150			`);`
151			`END COMPONENT;`
152
153			`COMPONENT oa22_x2`
154			`port (`
155			`i0 : in BIT; -- i0`
156			`i1 : in BIT; -- i1`
157			`i2 : in BIT; -- i2`
158			`q : out BIT; -- q`
159			`vdd : in BIT; -- vdd`
160			`vss : in BIT -- vss`
161			`);`
162			`END COMPONENT;`
163
164			`COMPONENT o2_x2`
165			`port (`
166			`i0 : in BIT; -- i0`
167			`i1 : in BIT; -- i1`
168			`q : out BIT; -- q`
169			`vdd : in BIT; -- vdd`
170			`vss : in BIT -- vss`
171			`);`
172			`END COMPONENT;`
173
174			`COMPONENT a2_x2`
175			`port (`
176			`i0 : in BIT; -- i0`
177			`i1 : in BIT; -- i1`
178			`q : out BIT; -- q`
179			`vdd : in BIT; -- vdd`
180			`vss : in BIT -- vss`
181			`);`
182			`END COMPONENT;`
183
184			`COMPONENT a3_x2`
185			`port (`
186			`i0 : in BIT; -- i0`
187			`i1 : in BIT; -- i1`
188			`i2 : in BIT; -- i2`
189			`q : out BIT; -- q`
190			`vdd : in BIT; -- vdd`
191			`vss : in BIT -- vss`
192			`);`
193			`END COMPONENT;`
194
195			`COMPONENT a4_x2`
196			`port (`
197			`i0 : in BIT; -- i0`
198			`i1 : in BIT; -- i1`
199			`i2 : in BIT; -- i2`
200			`i3 : in BIT; -- i3`
201			`q : out BIT; -- q`
202			`vdd : in BIT; -- vdd`
203			`vss : in BIT -- vss`
204			`);`
205			`END COMPONENT;`
206
207			`COMPONENT sff1_x4`
208			`port (`
209			`ck : in BIT; -- ck`
210			`i : in BIT; -- i`
211			`q : out BIT; -- q`
212			`vdd : in BIT; -- vdd`
213			`vss : in BIT -- vss`
214			`);`
215			`END COMPONENT;`
216
217			`SIGNAL aux40_a : BIT; -- aux40_a`
218			`SIGNAL aux32_a : BIT; -- aux32_a`
219			`SIGNAL aux33_a : BIT; -- aux33_a`
220			`SIGNAL aux35_a : BIT; -- aux35_a`
221			`SIGNAL aux38_a : BIT; -- aux38_a`
222			`SIGNAL aux44_a : BIT; -- aux44_a`
223			`SIGNAL auxsc58 : BIT; -- auxsc58`
224			`SIGNAL auxsc1 : BIT; -- auxsc1`
225			`SIGNAL auxsc16 : BIT; -- auxsc16`
226			`SIGNAL auxsc39 : BIT; -- auxsc39`
227			`SIGNAL auxsc15 : BIT; -- auxsc15`
228			`SIGNAL auxsc38 : BIT; -- auxsc38`
229			`SIGNAL auxsc65 : BIT; -- auxsc65`
230			`SIGNAL auxsc3 : BIT; -- auxsc3`
231			`SIGNAL auxsc83 : BIT; -- auxsc83`
232			`SIGNAL auxsc69 : BIT; -- auxsc69`
233			`SIGNAL auxsc80 : BIT; -- auxsc80`
234			`SIGNAL auxsc81 : BIT; -- auxsc81`
235			`SIGNAL auxsc78 : BIT; -- auxsc78`
236			`SIGNAL auxsc79 : BIT; -- auxsc79`
237			`SIGNAL auxsc82 : BIT; -- auxsc82`
238			`SIGNAL auxsc77 : BIT; -- auxsc77`
239			`SIGNAL auxsc89 : BIT; -- auxsc89`
240			`SIGNAL auxsc85 : BIT; -- auxsc85`
241			`SIGNAL auxsc42 : BIT; -- auxsc42`
242			`SIGNAL auxsc88 : BIT; -- auxsc88`
243			`SIGNAL auxsc26 : BIT; -- auxsc26`
244			`SIGNAL auxsc100 : BIT; -- auxsc100`
245			`SIGNAL auxsc95 : BIT; -- auxsc95`
246			`SIGNAL auxsc101 : BIT; -- auxsc101`
247			`SIGNAL auxsc97 : BIT; -- auxsc97`
248			`SIGNAL auxsc119 : BIT; -- auxsc119`
249			`SIGNAL auxsc120 : BIT; -- auxsc120`
250			`SIGNAL auxsc118 : BIT; -- auxsc118`
251			`SIGNAL auxsc121 : BIT; -- auxsc121`
252			`SIGNAL auxsc35 : BIT; -- auxsc35`
253			`SIGNAL auxsc111 : BIT; -- auxsc111`
254			`SIGNAL auxsc112 : BIT; -- auxsc112`
255			`SIGNAL auxsc109 : BIT; -- auxsc109`
256			`SIGNAL auxsc9 : BIT; -- auxsc9`
257			`SIGNAL auxsc10 : BIT; -- auxsc10`
258			`SIGNAL auxsc4 : BIT; -- auxsc4`
259			`SIGNAL auxsc11 : BIT; -- auxsc11`
260			`SIGNAL auxsc12 : BIT; -- auxsc12`
261			`SIGNAL auxsc13 : BIT; -- auxsc13`
262			`SIGNAL auxsc31 : BIT; -- auxsc31`
263			`SIGNAL auxsc27 : BIT; -- auxsc27`
264			`SIGNAL auxsc28 : BIT; -- auxsc28`
265			`SIGNAL auxsc32 : BIT; -- auxsc32`
266			`SIGNAL auxsc29 : BIT; -- auxsc29`
267			`SIGNAL auxsc30 : BIT; -- auxsc30`
268			`SIGNAL auxsc33 : BIT; -- auxsc33`
269			`SIGNAL auxsc34 : BIT; -- auxsc34`
270			`SIGNAL auxsc49 : BIT; -- auxsc49`
271			`SIGNAL auxsc50 : BIT; -- auxsc50`
272			`SIGNAL auxsc51 : BIT; -- auxsc51`
273			`SIGNAL auxsc46 : BIT; -- auxsc46`
274			`SIGNAL auxsc52 : BIT; -- auxsc52`
275			`SIGNAL auxsc59 : BIT; -- auxsc59`
276			`SIGNAL auxsc64 : BIT; -- auxsc64`
277			`SIGNAL auxreg4 : BIT; -- auxreg4`
278			`SIGNAL auxreg3 : BIT; -- auxreg3`
279			`SIGNAL auxreg2 : BIT; -- auxreg2`
280			`SIGNAL auxreg1 : BIT; -- auxreg1`
281
282			`BEGIN`
283
284			`en_out : a2_x2`
285			`PORT MAP (`
286			`vss => vss,`
287			`vdd => vdd,`
288			`q => en_out,`
289			`i1 => auxsc88,`
290			`i0 => auxsc65);`
291			`finish : a2_x2`
292			`PORT MAP (`
293			`vss => vss,`
294			`vdd => vdd,`
295			`q => finish,`
296			`i1 => auxsc97,`
297			`i0 => auxsc65);`
298			`c_count : a2_x2`
299			`PORT MAP (`
300			`vss => vss,`
301			`vdd => vdd,`
302			`q => c_count,`
303			`i1 => auxsc118,`
304			`i0 => auxsc65);`
305			`sel2 : inv_x1`
306			`PORT MAP (`
307			`vss => vss,`
308			`vdd => vdd,`
309			`nq => sel2,`
310			`i => auxsc121);`
311			`sel1 : zero_x0`
312			`PORT MAP (`
313			`vss => vss,`
314			`vdd => vdd,`
315			`nq => sel1);`
316			`en_shft : a3_x2`
317			`PORT MAP (`
318			`vss => vss,`
319			`vdd => vdd,`
320			`q => en_shft,`
321			`i2 => auxsc109,`
322			`i1 => auxsc95,`
323			`i0 => auxsc65);`
324			`auxsc64 : o4_x2`
325			`PORT MAP (`
326			`vss => vss,`
327			`vdd => vdd,`
328			`q => auxsc64,`
329			`i3 => auxreg3,`
330			`i2 => aux44_a,`
331			`i1 => auxsc59,`
332			`i0 => rst);`
333			`auxsc59 : a2_x2`
334			`PORT MAP (`
335			`vss => vss,`
336			`vdd => vdd,`
337			`q => auxsc59,`
338			`i1 => auxreg1,`
339			`i0 => auxreg4);`
340			`auxsc52 : an12_x1`
341			`PORT MAP (`
342			`vss => vss,`
343			`vdd => vdd,`
344			`q => auxsc52,`
345			`i1 => auxsc46,`
346			`i0 => rst);`
347			`auxsc46 : o3_x2`
348			`PORT MAP (`
349			`vss => vss,`
350			`vdd => vdd,`
351			`q => auxsc46,`
352			`i2 => auxsc51,`
353			`i1 => auxsc50,`
354			`i0 => auxsc49);`
355			`auxsc51 : a2_x2`
356			`PORT MAP (`
357			`vss => vss,`
358			`vdd => vdd,`
359			`q => auxsc51,`
360			`i1 => auxsc42,`
361			`i0 => auxreg3);`
362			`auxsc50 : an12_x1`
363			`PORT MAP (`
364			`vss => vss,`
365			`vdd => vdd,`
366			`q => auxsc50,`
367			`i1 => aux33_a,`
368			`i0 => auxsc3);`
369			`auxsc49 : a2_x2`
370			`PORT MAP (`
371			`vss => vss,`
372			`vdd => vdd,`
373			`q => auxsc49,`
374			`i1 => auxsc3,`
375			`i0 => aux32_a);`
376			`auxsc34 : no4_x1`
377			`PORT MAP (`
378			`vss => vss,`
379			`vdd => vdd,`
380			`nq => auxsc34,`
381			`i3 => auxsc33,`
382			`i2 => auxsc32,`
383			`i1 => auxsc31,`
384			`i0 => rst);`
385			`auxsc33 : a3_x2`
386			`PORT MAP (`
387			`vss => vss,`
388			`vdd => vdd,`
389			`q => auxsc33,`
390			`i2 => auxreg1,`
391			`i1 => auxsc30,`
392			`i0 => auxsc26);`
393			`auxsc30 : inv_x1`
394			`PORT MAP (`
395			`vss => vss,`
396			`vdd => vdd,`
397			`nq => auxsc30,`
398			`i => auxsc29);`
399			`auxsc29 : an12_x1`
400			`PORT MAP (`
401			`vss => vss,`
402			`vdd => vdd,`
403			`q => auxsc29,`
404			`i1 => auxreg4,`
405			`i0 => auxreg3);`
406			`auxsc32 : no3_x1`
407			`PORT MAP (`
408			`vss => vss,`
409			`vdd => vdd,`
410			`nq => auxsc32,`
411			`i2 => auxreg1,`
412			`i1 => auxsc28,`
413			`i0 => auxreg4);`
414			`auxsc28 : a2_x2`
415			`PORT MAP (`
416			`vss => vss,`
417			`vdd => vdd,`
418			`q => auxsc28,`
419			`i1 => auxsc27,`
420			`i0 => auxsc26);`
421			`auxsc27 : inv_x1`
422			`PORT MAP (`
423			`vss => vss,`
424			`vdd => vdd,`
425			`nq => auxsc27,`
426			`i => auxreg3);`
427			`auxsc31 : no4_x1`
428			`PORT MAP (`
429			`vss => vss,`
430			`vdd => vdd,`
431			`nq => auxsc31,`
432			`i3 => auxreg1,`
433			`i2 => aux40_a,`
434			`i1 => aux38_a,`
435			`i0 => auxsc1);`
436			`auxsc13 : no2_x1`
437			`PORT MAP (`
438			`vss => vss,`
439			`vdd => vdd,`
440			`nq => auxsc13,`
441			`i1 => auxsc12,`
442			`i0 => rst);`
443			`auxsc12 : nao22_x1`
444			`PORT MAP (`
445			`vss => vss,`
446			`vdd => vdd,`
447			`nq => auxsc12,`
448			`i2 => auxsc11,`
449			`i1 => auxsc4,`
450			`i0 => auxsc10);`
451			`auxsc11 : o4_x2`
452			`PORT MAP (`
453			`vss => vss,`
454			`vdd => vdd,`
455			`q => auxsc11,`
456			`i3 => aux38_a,`
457			`i2 => aux35_a,`
458			`i1 => auxsc1,`
459			`i0 => auxreg1);`
460			`auxsc4 : na2_x1`
461			`PORT MAP (`
462			`vss => vss,`
463			`vdd => vdd,`
464			`nq => auxsc4,`
465			`i1 => auxsc1,`
466			`i0 => auxreg2);`
467			`auxsc10 : o2_x2`
468			`PORT MAP (`
469			`vss => vss,`
470			`vdd => vdd,`
471			`q => auxsc10,`
472			`i1 => auxreg3,`
473			`i0 => auxsc3);`
474			`auxsc9 : inv_x1`
475			`PORT MAP (`
476			`vss => vss,`
477			`vdd => vdd,`
478			`nq => auxsc9,`
479			`i => clk);`
480			`auxsc109 : oa22_x2`
481			`PORT MAP (`
482			`vss => vss,`
483			`vdd => vdd,`
484			`q => auxsc109,`
485			`i2 => auxsc112,`
486			`i1 => auxsc1,`
487			`i0 => auxsc26);`
488			`auxsc112 : an12_x1`
489			`PORT MAP (`
490			`vss => vss,`
491			`vdd => vdd,`
492			`q => auxsc112,`
493			`i1 => auxreg4,`
494			`i0 => auxsc111);`
495			`auxsc111 : o3_x2`
496			`PORT MAP (`
497			`vss => vss,`
498			`vdd => vdd,`
499			`q => auxsc111,`
500			`i2 => auxsc80,`
501			`i1 => auxsc58,`
502			`i0 => auxsc35);`
503			`auxsc35 : inv_x1`
504			`PORT MAP (`
505			`vss => vss,`
506			`vdd => vdd,`
507			`nq => auxsc35,`
508			`i => count(0));`
509			`auxsc121 : inv_x1`
510			`PORT MAP (`
511			`vss => vss,`
512			`vdd => vdd,`
513			`nq => auxsc121,`
514			`i => en_count);`
515			`auxsc118 : nao22_x1`
516			`PORT MAP (`
517			`vss => vss,`
518			`vdd => vdd,`
519			`nq => auxsc118,`
520			`i2 => auxsc120,`
521			`i1 => auxsc119,`
522			`i0 => auxreg1);`
523			`auxsc120 : na2_x1`
524			`PORT MAP (`
525			`vss => vss,`
526			`vdd => vdd,`
527			`nq => auxsc120,`
528			`i1 => auxreg4,`
529			`i0 => auxreg1);`
530			`auxsc119 : nao22_x1`
531			`PORT MAP (`
532			`vss => vss,`
533			`vdd => vdd,`
534			`nq => auxsc119,`
535			`i2 => auxreg3,`
536			`i1 => auxreg4,`
537			`i0 => auxsc26);`
538			`auxsc97 : nao22_x1`
539			`PORT MAP (`
540			`vss => vss,`
541			`vdd => vdd,`
542			`nq => auxsc97,`
543			`i2 => auxsc101,`
544			`i1 => auxreg4,`
545			`i0 => auxsc100);`
546			`auxsc101 : na3_x1`
547			`PORT MAP (`
548			`vss => vss,`
549			`vdd => vdd,`
550			`nq => auxsc101,`
551			`i2 => auxreg4,`
552			`i1 => auxsc95,`
553			`i0 => aux35_a);`
554			`auxsc95 : no2_x1`
555			`PORT MAP (`
556			`vss => vss,`
557			`vdd => vdd,`
558			`nq => auxsc95,`
559			`i1 => auxreg3,`
560			`i0 => auxreg1);`
561			`auxsc100 : na2_x1`
562			`PORT MAP (`
563			`vss => vss,`
564			`vdd => vdd,`
565			`nq => auxsc100,`
566			`i1 => auxsc26,`
567			`i0 => auxreg1);`
568			`auxsc26 : inv_x1`
569			`PORT MAP (`
570			`vss => vss,`
571			`vdd => vdd,`
572			`nq => auxsc26,`
573			`i => auxreg2);`
574			`auxsc88 : nao22_x1`
575			`PORT MAP (`
576			`vss => vss,`
577			`vdd => vdd,`
578			`nq => auxsc88,`
579			`i2 => auxsc42,`
580			`i1 => auxsc85,`
581			`i0 => auxsc89);`
582			`auxsc42 : na2_x1`
583			`PORT MAP (`
584			`vss => vss,`
585			`vdd => vdd,`
586			`nq => auxsc42,`
587			`i1 => auxreg2,`
588			`i0 => auxsc1);`
589			`auxsc85 : o2_x2`
590			`PORT MAP (`
591			`vss => vss,`
592			`vdd => vdd,`
593			`q => auxsc85,`
594			`i1 => auxreg3,`
595			`i0 => auxreg1);`
596			`auxsc89 : na2_x1`
597			`PORT MAP (`
598			`vss => vss,`
599			`vdd => vdd,`
600			`nq => auxsc89,`
601			`i1 => auxsc38,`
602			`i0 => auxsc16);`
603			`auxsc77 : o2_x2`
604			`PORT MAP (`
605			`vss => vss,`
606			`vdd => vdd,`
607			`q => auxsc77,`
608			`i1 => auxsc82,`
609			`i0 => auxsc81);`
610			`auxsc82 : na2_x1`
611			`PORT MAP (`
612			`vss => vss,`
613			`vdd => vdd,`
614			`nq => auxsc82,`
615			`i1 => auxreg4,`
616			`i0 => auxsc79);`
617			`auxsc79 : inv_x1`
618			`PORT MAP (`
619			`vss => vss,`
620			`vdd => vdd,`
621			`nq => auxsc79,`
622			`i => auxsc78);`
623			`auxsc78 : on12_x1`
624			`PORT MAP (`
625			`vss => vss,`
626			`vdd => vdd,`
627			`q => auxsc78,`
628			`i1 => auxreg3,`
629			`i0 => auxsc3);`
630			`auxsc81 : no2_x1`
631			`PORT MAP (`
632			`vss => vss,`
633			`vdd => vdd,`
634			`nq => auxsc81,`
635			`i1 => auxsc80,`
636			`i0 => auxsc58);`
637			`auxsc80 : o2_x2`
638			`PORT MAP (`
639			`vss => vss,`
640			`vdd => vdd,`
641			`q => auxsc80,`
642			`i1 => count(2),`
643			`i0 => count(1));`
644			`auxsc69 : o2_x2`
645			`PORT MAP (`
646			`vss => vss,`
647			`vdd => vdd,`
648			`q => auxsc69,`
649			`i1 => auxreg4,`
650			`i0 => auxsc83);`
651			`auxsc83 : o2_x2`
652			`PORT MAP (`
653			`vss => vss,`
654			`vdd => vdd,`
655			`q => auxsc83,`
656			`i1 => auxreg2,`
657			`i0 => auxsc3);`
658			`auxsc3 : inv_x1`
659			`PORT MAP (`
660			`vss => vss,`
661			`vdd => vdd,`
662			`nq => auxsc3,`
663			`i => auxreg1);`
664			`auxsc65 : inv_x1`
665			`PORT MAP (`
666			`vss => vss,`
667			`vdd => vdd,`
668			`nq => auxsc65,`
669			`i => rst);`
670			`auxsc38 : a4_x2`
671			`PORT MAP (`
672			`vss => vss,`
673			`vdd => vdd,`
674			`q => auxsc38,`
675			`i3 => auxsc15,`
676			`i2 => auxsc39,`
677			`i1 => start,`
678			`i0 => auxreg4);`
679			`auxsc15 : inv_x1`
680			`PORT MAP (`
681			`vss => vss,`
682			`vdd => vdd,`
683			`nq => auxsc15,`
684			`i => count(2));`
685			`auxsc39 : inv_x1`
686			`PORT MAP (`
687			`vss => vss,`
688			`vdd => vdd,`
689			`nq => auxsc39,`
690			`i => count(0));`
691			`auxsc16 : inv_x1`
692			`PORT MAP (`
693			`vss => vss,`
694			`vdd => vdd,`
695			`nq => auxsc16,`
696			`i => count(1));`
697			`auxsc1 : inv_x1`
698			`PORT MAP (`
699			`vss => vss,`
700			`vdd => vdd,`
701			`nq => auxsc1,`
702			`i => auxreg4);`
703			`auxsc58 : inv_x1`
704			`PORT MAP (`
705			`vss => vss,`
706			`vdd => vdd,`
707			`nq => auxsc58,`
708			`i => start);`
709			`aux44_a : oa22_x2`
710			`PORT MAP (`
711			`vss => vss,`
712			`vdd => vdd,`
713			`q => aux44_a,`
714			`i2 => auxreg2,`
715			`i1 => auxsc58,`
716			`i0 => auxreg4);`
717			`aux38_a : o2_x2`
718			`PORT MAP (`
719			`vss => vss,`
720			`vdd => vdd,`
721			`q => aux38_a,`
722			`i1 => auxreg3,`
723			`i0 => auxreg2);`
724			`aux35_a : a4_x2`
725			`PORT MAP (`
726			`vss => vss,`
727			`vdd => vdd,`
728			`q => aux35_a,`
729			`i3 => start,`
730			`i2 => count(2),`
731			`i1 => count(1),`
732			`i0 => count(0));`
733			`aux33_a : a2_x2`
734			`PORT MAP (`
735			`vss => vss,`
736			`vdd => vdd,`
737			`q => aux33_a,`
738			`i1 => auxsc1,`
739			`i0 => auxreg2);`
740			`aux32_a : a2_x2`
741			`PORT MAP (`
742			`vss => vss,`
743			`vdd => vdd,`
744			`q => aux32_a,`
745			`i1 => auxsc38,`
746			`i0 => auxsc16);`
747			`auxinit1_a : a3_x2`
748			`PORT MAP (`
749			`vss => vss,`
750			`vdd => vdd,`
751			`q => en_count,`
752			`i2 => auxsc77,`
753			`i1 => auxsc69,`
754			`i0 => auxsc65);`
755			`aux40_a : a4_x2`
756			`PORT MAP (`
757			`vss => vss,`
758			`vdd => vdd,`
759			`q => aux40_a,`
760			`i3 => auxsc15,`
761			`i2 => auxsc16,`
762			`i1 => start,`
763			`i0 => count(0));`
764			`current_state_0 : sff1_x4`
765			`PORT MAP (`
766			`vss => vss,`
767			`vdd => vdd,`
768			`q => auxreg1,`
769			`i => auxsc13,`
770			`ck => auxsc9);`
771			`current_state_1 : sff1_x4`
772			`PORT MAP (`
773			`vss => vss,`
774			`vdd => vdd,`
775			`q => auxreg2,`
776			`i => auxsc34,`
777			`ck => auxsc9);`
778			`current_state_2 : sff1_x4`
779			`PORT MAP (`
780			`vss => vss,`
781			`vdd => vdd,`
782			`q => auxreg3,`
783			`i => auxsc52,`
784			`ck => auxsc9);`
785			`current_state_3 : sff1_x4`
786			`PORT MAP (`
787			`vss => vss,`
788			`vdd => vdd,`
789			`q => auxreg4,`
790			`i => auxsc64,`
791			`ck => auxsc9);`
792
793			`end VST;`