OpenCores
URL https://opencores.org/ocsvn/structural_vhdl/structural_vhdl/trunk

Subversion Repositories structural_vhdl

[/] [structural_vhdl/] [trunk/] [key_regulator/] [fulladder17.vst] - Blame information for rev 4

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 marta 
-- VHDL structural description generated from `fulladder17`
2 
--              date : Tue Jul 31 11:58:09 2001
3 
 
4 
 
5 
-- Entity Declaration
6 
 
7 
ENTITY fulladder17 IS
8 
  PORT (
9 
  a : in BIT_VECTOR (16 DOWNTO 0);      -- a
10 
  b : in BIT_VECTOR (16 DOWNTO 0);      -- b
11 
  sum : out BIT_VECTOR (17 DOWNTO 0);   -- sum
12 
  vdd : in BIT; -- vdd
13 
  vss : in BIT  -- vss
14 
  );
15 
END fulladder17;
16 
 
17 
-- Architecture Declaration
18 
 
19 
ARCHITECTURE VST OF fulladder17 IS
20 
  COMPONENT zero_x0
21 
    port (
22 
    nq : out BIT;       -- nq
23 
    vdd : in BIT;       -- vdd
24 
    vss : in BIT        -- vss
25 
    );
26 
  END COMPONENT;
27 
 
28 
  COMPONENT fulladder
29 
    port (
30 
    a : in BIT; -- a
31 
    b : in BIT; -- b
32 
    cin : in BIT;       -- cin
33 
    sum : out BIT;      -- sum
34 
    cout : out BIT;     -- cout
35 
    vdd : in BIT;       -- vdd
36 
    vss : in BIT        -- vss
37 
    );
38 
  END COMPONENT;
39 
 
40 
  SIGNAL cout0 : BIT;   -- cout0
41 
  SIGNAL cout1 : BIT;   -- cout1
42 
  SIGNAL cout10 : BIT;  -- cout10
43 
  SIGNAL cout11 : BIT;  -- cout11
44 
  SIGNAL cout12 : BIT;  -- cout12
45 
  SIGNAL cout13 : BIT;  -- cout13
46 
  SIGNAL cout14 : BIT;  -- cout14
47 
  SIGNAL cout15 : BIT;  -- cout15
48 
  SIGNAL cout2 : BIT;   -- cout2
49 
  SIGNAL cout3 : BIT;   -- cout3
50 
  SIGNAL cout4 : BIT;   -- cout4
51 
  SIGNAL cout5 : BIT;   -- cout5
52 
  SIGNAL cout6 : BIT;   -- cout6
53 
  SIGNAL cout7 : BIT;   -- cout7
54 
  SIGNAL cout8 : BIT;   -- cout8
55 
  SIGNAL cout9 : BIT;   -- cout9
56 
  SIGNAL nol : BIT;     -- nol
57 
 
58 
BEGIN
59 
 
60 
  zero1 : zero_x0
61 
    PORT MAP (
62 
    vss => vss,
63 
    vdd => vdd,
64 
    nq => nol);
65 
  fulladder1 : fulladder
66 
    PORT MAP (
67 
    vss => vss,
68 
    vdd => vdd,
69 
    cout => cout0,
70 
    sum => sum(0),
71 
    cin => nol,
72 
    b => b(0),
73 
    a => a(0));
74 
  fulladder2 : fulladder
75 
    PORT MAP (
76 
    vss => vss,
77 
    vdd => vdd,
78 
    cout => cout1,
79 
    sum => sum(1),
80 
    cin => cout0,
81 
    b => b(1),
82 
    a => a(1));
83 
  fulladder3 : fulladder
84 
    PORT MAP (
85 
    vss => vss,
86 
    vdd => vdd,
87 
    cout => cout2,
88 
    sum => sum(2),
89 
    cin => cout1,
90 
    b => b(2),
91 
    a => a(2));
92 
  fulladder4 : fulladder
93 
    PORT MAP (
94 
    vss => vss,
95 
    vdd => vdd,
96 
    cout => cout3,
97 
    sum => sum(3),
98 
    cin => cout2,
99 
    b => b(3),
100 
    a => a(3));
101 
  fulladder5 : fulladder
102 
    PORT MAP (
103 
    vss => vss,
104 
    vdd => vdd,
105 
    cout => cout4,
106 
    sum => sum(4),
107 
    cin => cout3,
108 
    b => b(4),
109 
    a => a(4));
110 
  fulladder6 : fulladder
111 
    PORT MAP (
112 
    vss => vss,
113 
    vdd => vdd,
114 
    cout => cout5,
115 
    sum => sum(5),
116 
    cin => cout4,
117 
    b => b(5),
118 
    a => a(5));
119 
  fulladder7 : fulladder
120 
    PORT MAP (
121 
    vss => vss,
122 
    vdd => vdd,
123 
    cout => cout6,
124 
    sum => sum(6),
125 
    cin => cout5,
126 
    b => b(6),
127 
    a => a(6));
128 
  fulladder8 : fulladder
129 
    PORT MAP (
130 
    vss => vss,
131 
    vdd => vdd,
132 
    cout => cout7,
133 
    sum => sum(7),
134 
    cin => cout6,
135 
    b => b(7),
136 
    a => a(7));
137 
  fulladder9 : fulladder
138 
    PORT MAP (
139 
    vss => vss,
140 
    vdd => vdd,
141 
    cout => cout8,
142 
    sum => sum(8),
143 
    cin => cout7,
144 
    b => b(8),
145 
    a => a(8));
146 
  fulladder10 : fulladder
147 
    PORT MAP (
148 
    vss => vss,
149 
    vdd => vdd,
150 
    cout => cout9,
151 
    sum => sum(9),
152 
    cin => cout8,
153 
    b => b(9),
154 
    a => a(9));
155 
  fulladder11 : fulladder
156 
    PORT MAP (
157 
    vss => vss,
158 
    vdd => vdd,
159 
    cout => cout10,
160 
    sum => sum(10),
161 
    cin => cout9,
162 
    b => b(10),
163 
    a => a(10));
164 
  fulladder12 : fulladder
165 
    PORT MAP (
166 
    vss => vss,
167 
    vdd => vdd,
168 
    cout => cout11,
169 
    sum => sum(11),
170 
    cin => cout10,
171 
    b => b(11),
172 
    a => a(11));
173 
  fulladder13 : fulladder
174 
    PORT MAP (
175 
    vss => vss,
176 
    vdd => vdd,
177 
    cout => cout12,
178 
    sum => sum(12),
179 
    cin => cout11,
180 
    b => b(12),
181 
    a => a(12));
182 
  fulladder14 : fulladder
183 
    PORT MAP (
184 
    vss => vss,
185 
    vdd => vdd,
186 
    cout => cout13,
187 
    sum => sum(13),
188 
    cin => cout12,
189 
    b => b(13),
190 
    a => a(13));
191 
  fulladder15 : fulladder
192 
    PORT MAP (
193 
    vss => vss,
194 
    vdd => vdd,
195 
    cout => cout14,
196 
    sum => sum(14),
197 
    cin => cout13,
198 
    b => b(14),
199 
    a => a(14));
200 
  fulladder16 : fulladder
201 
    PORT MAP (
202 
    vss => vss,
203 
    vdd => vdd,
204 
    cout => cout15,
205 
    sum => sum(15),
206 
    cin => cout14,
207 
    b => b(15),
208 
    a => a(15));
209 
  fulladder17 : fulladder
210 
    PORT MAP (
211 
    vss => vss,
212 
    vdd => vdd,
213 
    cout => sum(17),
214 
    sum => sum(16),
215 
    cin => cout15,
216 
    b => b(16),
217 
    a => a(16));
218 
 
219 
end VST;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.