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[/] [structural_vhdl/] [trunk/] [key_regulator/] [fullsubstractor16.vst] - Blame information for rev 4

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1 2 marta 
-- VHDL structural description generated from `fullsubstractor16`
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--              date : Tue Jul 31 12:52:37 2001
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-- Entity Declaration
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ENTITY fullsubstractor16 IS
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  PORT (
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  a : in BIT_VECTOR (15 DOWNTO 0);      -- a
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  b : in BIT_VECTOR (15 DOWNTO 0);      -- b
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  diff : out BIT_VECTOR (15 DOWNTO 0);  -- diff
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  vdd : in BIT; -- vdd
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  vss : in BIT  -- vss
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  );
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END fullsubstractor16;
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-- Architecture Declaration
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ARCHITECTURE VST OF fullsubstractor16 IS
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  COMPONENT zero_x0
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    port (
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    nq : out BIT;       -- nq
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  COMPONENT fullsubstractor
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    port (
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    a : in BIT; -- a
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    b : in BIT; -- b
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    bin : in BIT;       -- bin
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    diff : out BIT;     -- diff
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    bout : out BIT;     -- bout
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  COMPONENT fullsubstractorbout
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    port (
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    a : in BIT; -- a
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    b : in BIT; -- b
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    bin : in BIT;       -- bin
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    diff : out BIT;     -- diff
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  SIGNAL bout0 : BIT;   -- bout0
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  SIGNAL bout1 : BIT;   -- bout1
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  SIGNAL bout10 : BIT;  -- bout10
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  SIGNAL bout11 : BIT;  -- bout11
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  SIGNAL bout12 : BIT;  -- bout12
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  SIGNAL bout13 : BIT;  -- bout13
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  SIGNAL bout14 : BIT;  -- bout14
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  SIGNAL bout2 : BIT;   -- bout2
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  SIGNAL bout3 : BIT;   -- bout3
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  SIGNAL bout4 : BIT;   -- bout4
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  SIGNAL bout5 : BIT;   -- bout5
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  SIGNAL bout6 : BIT;   -- bout6
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  SIGNAL bout7 : BIT;   -- bout7
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  SIGNAL bout8 : BIT;   -- bout8
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  SIGNAL bout9 : BIT;   -- bout9
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  SIGNAL nol : BIT;     -- nol
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BEGIN
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  zero1 : zero_x0
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => nol);
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  fullsubstractor1 : fullsubstractor
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    bout => bout0,
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    diff => diff(0),
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    bin => nol,
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    b => b(0),
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    a => a(0));
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  fullsubstractor2 : fullsubstractor
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    bout => bout1,
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    diff => diff(1),
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    bin => bout0,
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    b => b(1),
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    a => a(1));
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  fullsubstractor3 : fullsubstractor
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    bout => bout2,
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    diff => diff(2),
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    bin => bout1,
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    b => b(2),
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    a => a(2));
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  fullsubstractor4 : fullsubstractor
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    bout => bout3,
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    diff => diff(3),
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    bin => bout2,
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    b => b(3),
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    a => a(3));
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  fullsubstractor5 : fullsubstractor
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    bout => bout4,
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    diff => diff(4),
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    bin => bout3,
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    b => b(4),
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    a => a(4));
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  fullsubstractor6 : fullsubstractor
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    bout => bout5,
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    diff => diff(5),
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    bin => bout4,
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    b => b(5),
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    a => a(5));
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  fullsubstractor7 : fullsubstractor
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    bout => bout6,
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    diff => diff(6),
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    bin => bout5,
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    b => b(6),
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    a => a(6));
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  fullsubstractor8 : fullsubstractor
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    bout => bout7,
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    diff => diff(7),
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    bin => bout6,
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    b => b(7),
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    a => a(7));
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  fullsubstractor9 : fullsubstractor
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    bout => bout8,
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    diff => diff(8),
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    bin => bout7,
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    b => b(8),
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    a => a(8));
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  fullsubstractor10 : fullsubstractor
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    bout => bout9,
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    diff => diff(9),
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    bin => bout8,
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    b => b(9),
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    a => a(9));
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  fullsubstractor11 : fullsubstractor
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    bout => bout10,
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    diff => diff(10),
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    bin => bout9,
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    b => b(10),
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    a => a(10));
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  fullsubstractor12 : fullsubstractor
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    bout => bout11,
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    diff => diff(11),
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    bin => bout10,
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    b => b(11),
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    a => a(11));
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  fullsubstractor13 : fullsubstractor
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    bout => bout12,
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    diff => diff(12),
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    bin => bout11,
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    b => b(12),
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    a => a(12));
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  fullsubstractor14 : fullsubstractor
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    bout => bout13,
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    diff => diff(13),
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    bin => bout12,
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    b => b(13),
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    a => a(13));
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  fullsubstractor15 : fullsubstractor
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    bout => bout14,
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    diff => diff(14),
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    bin => bout13,
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    b => b(14),
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    a => a(14));
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  fullsubstarctor16 : fullsubstractorbout
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    diff => diff(15),
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    bin => bout14,
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    b => b(15),
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    a => a(15));
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end VST;

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