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[/] [structural_vhdl/] [trunk/] [key_regulator/] [kontrol_invmul.vst] - Blame information for rev 4

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-- VHDL structural description generated from `kontrol_invmul`
--              date : Thu Aug  2 11:11:10 2001
 
 
-- Entity Declaration
 
ENTITY kontrol_invmul IS
  PORT (
  start : in BIT;       -- start
  clk : in BIT; -- clk
  rst : in BIT; -- rst
  finish : out BIT;     -- finish
  en_in : out BIT;      -- en_in
  sel_in : out BIT_VECTOR (4 DOWNTO 0); -- sel_in
  sel : out BIT;        -- sel
  en_pipe : out BIT;    -- en_pipe
  en_out : out BIT;     -- en_out
  sel_out : out BIT_VECTOR (4 DOWNTO 0);        -- sel_out
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END kontrol_invmul;
 
-- Architecture Declaration
 
ARCHITECTURE VST OF kontrol_invmul IS
  COMPONENT kontrol_utama_invmul
    port (
    start : in BIT;     -- start
    clk : in BIT;       -- clk
    rst : in BIT;       -- rst
    n_stage : in BIT_VECTOR(1 DOWNTO 0);        -- n_stage
    n_iterasi : in BIT_VECTOR(3 DOWNTO 0);      -- n_iterasi
    n_dtin : in BIT_VECTOR(4 DOWNTO 0); -- n_dtin
    n_dtout : in BIT_VECTOR(4 DOWNTO 0);        -- n_dtout
    en_cstage : out BIT;        -- en_cstage
    c_cstage : out BIT; -- c_cstage
    en_cite : out BIT;  -- en_cite
    c_cite : out BIT;   -- c_cite
    en_cdtin : out BIT; -- en_cdtin
    c_cdtin : out BIT;  -- c_cdtin
    en_cdtout : out BIT;        -- en_cdtout
    c_cdtout : out BIT; -- c_cdtout
    en_in : out BIT;    -- en_in
    en_out : out BIT;   -- en_out
    en_pipe : out BIT;  -- en_pipe
    sel : out BIT;      -- sel
    finish : out BIT;   -- finish
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT count2_latch
    port (
    clk : in BIT;       -- clk
    en : in BIT;        -- en
    rst : in BIT;       -- rst
    q : out BIT_VECTOR(1 DOWNTO 0);     -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT count4_latch
    port (
    clk : in BIT;       -- clk
    en : in BIT;        -- en
    rst : in BIT;       -- rst
    q : out BIT_VECTOR(3 DOWNTO 0);     -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT count5_latch
    port (
    clk : in BIT;       -- clk
    en : in BIT;        -- en
    rst : in BIT;       -- rst
    q : out BIT_VECTOR(4 DOWNTO 0);     -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  SIGNAL c_cdtin : BIT; -- c_cdtin
  SIGNAL c_cdtout : BIT;        -- c_cdtout
  SIGNAL c_cite : BIT;  -- c_cite
  SIGNAL c_cstage : BIT;        -- c_cstage
  SIGNAL en_cdtin : BIT;        -- en_cdtin
  SIGNAL en_cdtout : BIT;       -- en_cdtout
  SIGNAL en_cite : BIT; -- en_cite
  SIGNAL en_cstage : BIT;       -- en_cstage
  SIGNAL n_iterasi_0 : BIT;     -- n_iterasi 0
  SIGNAL n_iterasi_1 : BIT;     -- n_iterasi 1
  SIGNAL n_iterasi_2 : BIT;     -- n_iterasi 2
  SIGNAL n_iterasi_3 : BIT;     -- n_iterasi 3
  SIGNAL n_stage_0 : BIT;       -- n_stage 0
  SIGNAL n_stage_1 : BIT;       -- n_stage 1
 
BEGIN
 
  kontrol_utama_invmul1 : kontrol_utama_invmul
    PORT MAP (
    vss => vss,
    vdd => vdd,
    finish => finish,
    sel => sel,
    en_pipe => en_pipe,
    en_out => en_out,
    en_in => en_in,
    c_cdtout => c_cdtout,
    en_cdtout => en_cdtout,
    c_cdtin => c_cdtin,
    en_cdtin => en_cdtin,
    c_cite => c_cite,
    en_cite => en_cite,
    c_cstage => c_cstage,
    en_cstage => en_cstage,
    n_dtout => sel_out(4)& sel_out(3)& sel_out(2)& sel_out(1)& sel_out(0),
    n_dtin => sel_in(4)& sel_in(3)& sel_in(2)& sel_in(1)& sel_in(0),
    n_iterasi => n_iterasi_3& n_iterasi_2& n_iterasi_1& n_iterasi_0,
    n_stage => n_stage_1& n_stage_0,
    rst => rst,
    clk => clk,
    start => start);
  count1 : count2_latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => n_stage_1& n_stage_0,
    rst => rst,
    en => en_cstage,
    clk => c_cstage);
  count2 : count4_latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => n_iterasi_3& n_iterasi_2& n_iterasi_1& n_iterasi_0,
    rst => rst,
    en => en_cite,
    clk => c_cite);
  count3 : count5_latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => sel_in(4)& sel_in(3)& sel_in(2)& sel_in(1)& sel_in(0),
    rst => rst,
    en => en_cdtin,
    clk => c_cdtin);
  count4 : count5_latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => sel_out(4)& sel_out(3)& sel_out(2)& sel_out(1)& sel_out(0),
    rst => rst,
    en => en_cdtout,
    clk => c_cdtout);
 
end VST;

Line No.	Rev	Author	Line
1	2	marta	-- VHDL structural description generated from `kontrol_invmul`
2			`-- date : Thu Aug 2 11:11:10 2001`
3
4
5			`-- Entity Declaration`
6
7			`ENTITY kontrol_invmul IS`
8			`PORT (`
9			`start : in BIT; -- start`
10			`clk : in BIT; -- clk`
11			`rst : in BIT; -- rst`
12			`finish : out BIT; -- finish`
13			`en_in : out BIT; -- en_in`
14			`sel_in : out BIT_VECTOR (4 DOWNTO 0); -- sel_in`
15			`sel : out BIT; -- sel`
16			`en_pipe : out BIT; -- en_pipe`
17			`en_out : out BIT; -- en_out`
18			`sel_out : out BIT_VECTOR (4 DOWNTO 0); -- sel_out`
19			`vdd : in BIT; -- vdd`
20			`vss : in BIT -- vss`
21			`);`
22			`END kontrol_invmul;`
23
24			`-- Architecture Declaration`
25
26			`ARCHITECTURE VST OF kontrol_invmul IS`
27			`COMPONENT kontrol_utama_invmul`
28			`port (`
29			`start : in BIT; -- start`
30			`clk : in BIT; -- clk`
31			`rst : in BIT; -- rst`
32			`n_stage : in BIT_VECTOR(1 DOWNTO 0); -- n_stage`
33			`n_iterasi : in BIT_VECTOR(3 DOWNTO 0); -- n_iterasi`
34			`n_dtin : in BIT_VECTOR(4 DOWNTO 0); -- n_dtin`
35			`n_dtout : in BIT_VECTOR(4 DOWNTO 0); -- n_dtout`
36			`en_cstage : out BIT; -- en_cstage`
37			`c_cstage : out BIT; -- c_cstage`
38			`en_cite : out BIT; -- en_cite`
39			`c_cite : out BIT; -- c_cite`
40			`en_cdtin : out BIT; -- en_cdtin`
41			`c_cdtin : out BIT; -- c_cdtin`
42			`en_cdtout : out BIT; -- en_cdtout`
43			`c_cdtout : out BIT; -- c_cdtout`
44			`en_in : out BIT; -- en_in`
45			`en_out : out BIT; -- en_out`
46			`en_pipe : out BIT; -- en_pipe`
47			`sel : out BIT; -- sel`
48			`finish : out BIT; -- finish`
49			`vdd : in BIT; -- vdd`
50			`vss : in BIT -- vss`
51			`);`
52			`END COMPONENT;`
53
54			`COMPONENT count2_latch`
55			`port (`
56			`clk : in BIT; -- clk`
57			`en : in BIT; -- en`
58			`rst : in BIT; -- rst`
59			`q : out BIT_VECTOR(1 DOWNTO 0); -- q`
60			`vdd : in BIT; -- vdd`
61			`vss : in BIT -- vss`
62			`);`
63			`END COMPONENT;`
64
65			`COMPONENT count4_latch`
66			`port (`
67			`clk : in BIT; -- clk`
68			`en : in BIT; -- en`
69			`rst : in BIT; -- rst`
70			`q : out BIT_VECTOR(3 DOWNTO 0); -- q`
71			`vdd : in BIT; -- vdd`
72			`vss : in BIT -- vss`
73			`);`
74			`END COMPONENT;`
75
76			`COMPONENT count5_latch`
77			`port (`
78			`clk : in BIT; -- clk`
79			`en : in BIT; -- en`
80			`rst : in BIT; -- rst`
81			`q : out BIT_VECTOR(4 DOWNTO 0); -- q`
82			`vdd : in BIT; -- vdd`
83			`vss : in BIT -- vss`
84			`);`
85			`END COMPONENT;`
86
87			`SIGNAL c_cdtin : BIT; -- c_cdtin`
88			`SIGNAL c_cdtout : BIT; -- c_cdtout`
89			`SIGNAL c_cite : BIT; -- c_cite`
90			`SIGNAL c_cstage : BIT; -- c_cstage`
91			`SIGNAL en_cdtin : BIT; -- en_cdtin`
92			`SIGNAL en_cdtout : BIT; -- en_cdtout`
93			`SIGNAL en_cite : BIT; -- en_cite`
94			`SIGNAL en_cstage : BIT; -- en_cstage`
95			`SIGNAL n_iterasi_0 : BIT; -- n_iterasi 0`
96			`SIGNAL n_iterasi_1 : BIT; -- n_iterasi 1`
97			`SIGNAL n_iterasi_2 : BIT; -- n_iterasi 2`
98			`SIGNAL n_iterasi_3 : BIT; -- n_iterasi 3`
99			`SIGNAL n_stage_0 : BIT; -- n_stage 0`
100			`SIGNAL n_stage_1 : BIT; -- n_stage 1`
101
102			`BEGIN`
103
104			`kontrol_utama_invmul1 : kontrol_utama_invmul`
105			`PORT MAP (`
106			`vss => vss,`
107			`vdd => vdd,`
108			`finish => finish,`
109			`sel => sel,`
110			`en_pipe => en_pipe,`
111			`en_out => en_out,`
112			`en_in => en_in,`
113			`c_cdtout => c_cdtout,`
114			`en_cdtout => en_cdtout,`
115			`c_cdtin => c_cdtin,`
116			`en_cdtin => en_cdtin,`
117			`c_cite => c_cite,`
118			`en_cite => en_cite,`
119			`c_cstage => c_cstage,`
120			`en_cstage => en_cstage,`
121			`n_dtout => sel_out(4)& sel_out(3)& sel_out(2)& sel_out(1)& sel_out(0),`
122			`n_dtin => sel_in(4)& sel_in(3)& sel_in(2)& sel_in(1)& sel_in(0),`
123			`n_iterasi => n_iterasi_3& n_iterasi_2& n_iterasi_1& n_iterasi_0,`
124			`n_stage => n_stage_1& n_stage_0,`
125			`rst => rst,`
126			`clk => clk,`
127			`start => start);`
128			`count1 : count2_latch`
129			`PORT MAP (`
130			`vss => vss,`
131			`vdd => vdd,`
132			`q => n_stage_1& n_stage_0,`
133			`rst => rst,`
134			`en => en_cstage,`
135			`clk => c_cstage);`
136			`count2 : count4_latch`
137			`PORT MAP (`
138			`vss => vss,`
139			`vdd => vdd,`
140			`q => n_iterasi_3& n_iterasi_2& n_iterasi_1& n_iterasi_0,`
141			`rst => rst,`
142			`en => en_cite,`
143			`clk => c_cite);`
144			`count3 : count5_latch`
145			`PORT MAP (`
146			`vss => vss,`
147			`vdd => vdd,`
148			`q => sel_in(4)& sel_in(3)& sel_in(2)& sel_in(1)& sel_in(0),`
149			`rst => rst,`
150			`en => en_cdtin,`
151			`clk => c_cdtin);`
152			`count4 : count5_latch`
153			`PORT MAP (`
154			`vss => vss,`
155			`vdd => vdd,`
156			`q => sel_out(4)& sel_out(3)& sel_out(2)& sel_out(1)& sel_out(0),`
157			`rst => rst,`
158			`en => en_cdtout,`
159			`clk => c_cdtout);`
160
161			`end VST;`

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[/] [structural_vhdl/] [trunk/] [key_regulator/] [kontrol_invmul.vst] - Blame information for rev 4