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[/] [structural_vhdl/] [trunk/] [key_regulator/] [kontrol_utama_invadd.vst] - Blame information for rev 4

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-- VHDL structural description generated from `kontrol_utama_invadd`
--              date : Sun Jul 29 23:45:35 2001
 
 
-- Entity Declaration
 
ENTITY kontrol_utama_invadd IS
  PORT (
  clk : in BIT; -- clk
  rst : in BIT; -- rst
  start : in BIT;       -- start
  n_dtin : in BIT_VECTOR (4 DOWNTO 0);  -- n_dtin
  n_dtout : in BIT_VECTOR (4 DOWNTO 0); -- n_dtout
  c_cdtin : inout BIT;  -- c_cdtin
  en_cdtin : inout BIT; -- en_cdtin
  c_cdtout : out BIT;   -- c_cdtout
  en_cdtout : out BIT;  -- en_cdtout
  en_out : out BIT;     -- en_out
  en_in : out BIT;      -- en_in
  finish : out BIT;     -- finish
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END kontrol_utama_invadd;
 
-- Architecture Declaration
 
ARCHITECTURE VST OF kontrol_utama_invadd IS
  COMPONENT oa22_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT noa22_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT no2_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT o4_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    i3 : in BIT;        -- i3
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT na4_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    i3 : in BIT;        -- i3
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT an12_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT no3_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT xr2_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT nao22_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT a4_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    i3 : in BIT;        -- i3
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT na2_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT no4_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    i3 : in BIT;        -- i3
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT inv_x1
    port (
    i : in BIT; -- i
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT a3_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT o2_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT a2_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT sff1_x4
    port (
    ck : in BIT;        -- ck
    i : in BIT; -- i
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  SIGNAL aux27_a : BIT; -- aux27_a
  SIGNAL auxsc9 : BIT;  -- auxsc9
  SIGNAL auxsc13 : BIT; -- auxsc13
  SIGNAL auxsc14 : BIT; -- auxsc14
  SIGNAL auxsc10 : BIT; -- auxsc10
  SIGNAL auxsc17 : BIT; -- auxsc17
  SIGNAL auxsc4 : BIT;  -- auxsc4
  SIGNAL auxsc7 : BIT;  -- auxsc7
  SIGNAL auxsc8 : BIT;  -- auxsc8
  SIGNAL auxsc6 : BIT;  -- auxsc6
  SIGNAL auxsc18 : BIT; -- auxsc18
  SIGNAL auxsc19 : BIT; -- auxsc19
  SIGNAL auxsc12 : BIT; -- auxsc12
  SIGNAL auxsc65 : BIT; -- auxsc65
  SIGNAL auxsc69 : BIT; -- auxsc69
  SIGNAL auxsc61 : BIT; -- auxsc61
  SIGNAL auxsc62 : BIT; -- auxsc62
  SIGNAL auxsc80 : BIT; -- auxsc80
  SIGNAL auxsc20 : BIT; -- auxsc20
  SIGNAL auxsc41 : BIT; -- auxsc41
  SIGNAL auxsc81 : BIT; -- auxsc81
  SIGNAL auxsc82 : BIT; -- auxsc82
  SIGNAL auxsc86 : BIT; -- auxsc86
  SIGNAL auxsc87 : BIT; -- auxsc87
  SIGNAL auxsc83 : BIT; -- auxsc83
  SIGNAL auxsc84 : BIT; -- auxsc84
  SIGNAL auxsc85 : BIT; -- auxsc85
  SIGNAL auxsc31 : BIT; -- auxsc31
  SIGNAL auxsc32 : BIT; -- auxsc32
  SIGNAL auxsc26 : BIT; -- auxsc26
  SIGNAL auxsc29 : BIT; -- auxsc29
  SIGNAL auxsc33 : BIT; -- auxsc33
  SIGNAL auxsc34 : BIT; -- auxsc34
  SIGNAL auxsc44 : BIT; -- auxsc44
  SIGNAL auxsc39 : BIT; -- auxsc39
  SIGNAL auxsc43 : BIT; -- auxsc43
  SIGNAL auxsc48 : BIT; -- auxsc48
  SIGNAL auxsc50 : BIT; -- auxsc50
  SIGNAL auxsc45 : BIT; -- auxsc45
  SIGNAL auxsc55 : BIT; -- auxsc55
  SIGNAL auxreg3 : BIT; -- auxreg3
  SIGNAL auxreg2 : BIT; -- auxreg2
  SIGNAL auxreg1 : BIT; -- auxreg1
 
BEGIN
 
  finish : oa22_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => finish,
    i2 => auxsc82,
    i1 => auxsc20,
    i0 => auxsc80);
  en_out : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => en_out,
    i => auxsc86);
  en_cdtout : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => en_cdtout,
    i => auxsc87);
  c_cdtout : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => c_cdtout,
    i1 => auxsc85,
    i0 => auxsc83);
  auxsc55 : o4_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc55,
    i3 => auxsc45,
    i2 => auxsc50,
    i1 => auxsc48,
    i0 => rst);
  auxsc45 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc45,
    i1 => auxreg1,
    i0 => auxreg2);
  auxsc50 : xr2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc50,
    i1 => auxreg2,
    i0 => auxsc20);
  auxsc48 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc48,
    i1 => auxreg2,
    i0 => start);
  auxsc43 : oa22_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc43,
    i2 => auxsc39,
    i1 => auxsc41,
    i0 => auxsc44);
  auxsc39 : noa22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc39,
    i2 => rst,
    i1 => auxreg3,
    i0 => auxsc19);
  auxsc44 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc44,
    i1 => auxsc9,
    i0 => start);
  auxsc34 : oa22_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc34,
    i2 => auxsc33,
    i1 => auxsc12,
    i0 => auxsc32);
  auxsc33 : noa22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc33,
    i2 => auxsc29,
    i1 => auxreg2,
    i0 => auxsc26);
  auxsc29 : o2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc29,
    i1 => rst,
    i0 => auxreg3);
  auxsc26 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc26,
    i => auxreg1);
  auxsc32 : no2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc32,
    i1 => auxsc20,
    i0 => rst);
  auxsc31 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc31,
    i => clk);
  auxsc85 : an12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc85,
    i1 => auxreg3,
    i0 => auxsc84);
  auxsc84 : o4_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc84,
    i3 => auxreg2,
    i2 => auxsc18,
    i1 => auxsc61,
    i0 => rst);
  auxsc83 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc83,
    i1 => auxsc14,
    i0 => auxsc13);
  auxsc87 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc87,
    i => en_cdtin);
  auxsc86 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc86,
    i => c_cdtin);
  auxsc82 : an12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc82,
    i1 => auxreg3,
    i0 => auxsc81);
  auxsc81 : na4_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc81,
    i3 => auxsc19,
    i2 => auxsc41,
    i1 => auxsc9,
    i0 => start);
  auxsc41 : an12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc41,
    i1 => auxsc6,
    i0 => n_dtout(0));
  auxsc20 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc20,
    i => auxreg3);
  auxsc80 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc80,
    i1 => auxreg2,
    i0 => auxsc9);
  auxsc62 : no4_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc62,
    i3 => auxreg2,
    i2 => auxsc18,
    i1 => auxsc61,
    i0 => rst);
  auxsc61 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc61,
    i => start);
  auxsc69 : no3_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc69,
    i2 => auxreg3,
    i1 => auxreg2,
    i0 => rst);
  auxsc65 : xr2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc65,
    i1 => auxreg3,
    i0 => auxsc19);
  auxsc12 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc12,
    i2 => auxsc19,
    i1 => auxsc18,
    i0 => auxsc17);
  auxsc19 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc19,
    i => auxreg2);
  auxsc18 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc18,
    i1 => auxsc6,
    i0 => auxsc4);
  auxsc6 : a4_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc6,
    i3 => auxsc8,
    i2 => auxsc7,
    i1 => n_dtout(4),
    i0 => n_dtout(1));
  auxsc8 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc8,
    i => n_dtout(3));
  auxsc7 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc7,
    i => n_dtout(2));
  auxsc4 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc4,
    i => n_dtout(0));
  auxsc17 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc17,
    i1 => auxsc10,
    i0 => start);
  auxsc10 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc10,
    i1 => auxsc14,
    i0 => auxsc13);
  auxsc14 : no4_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc14,
    i3 => n_dtin(4),
    i2 => n_dtin(3),
    i1 => n_dtin(2),
    i0 => n_dtin(1));
  auxsc13 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc13,
    i => n_dtin(0));
  auxsc9 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc9,
    i => rst);
  aux27_a : a3_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => aux27_a,
    i2 => auxsc12,
    i1 => auxsc9,
    i0 => auxreg3);
  auxinit1_a : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => c_cdtin,
    i1 => auxsc65,
    i0 => auxsc9);
  auxinit2_a : o2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => en_cdtin,
    i1 => aux27_a,
    i0 => auxsc69);
  aux30_a : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => en_in,
    i1 => auxreg3,
    i0 => auxsc62);
  current_state_0 : sff1_x4
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxreg1,
    i => auxsc34,
    ck => auxsc31);
  current_state_1 : sff1_x4
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxreg2,
    i => auxsc43,
    ck => auxsc31);
  current_state_2 : sff1_x4
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxreg3,
    i => auxsc55,
    ck => auxsc31);
 
end VST;

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Subversion Repositories structural_vhdl

[/] [structural_vhdl/] [trunk/] [key_regulator/] [kontrol_utama_invadd.vst] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	marta	-- VHDL structural description generated from `kontrol_utama_invadd`
2			`-- date : Sun Jul 29 23:45:35 2001`
3
4
5			`-- Entity Declaration`
6
7			`ENTITY kontrol_utama_invadd IS`
8			`PORT (`
9			`clk : in BIT; -- clk`
10			`rst : in BIT; -- rst`
11			`start : in BIT; -- start`
12			`n_dtin : in BIT_VECTOR (4 DOWNTO 0); -- n_dtin`
13			`n_dtout : in BIT_VECTOR (4 DOWNTO 0); -- n_dtout`
14			`c_cdtin : inout BIT; -- c_cdtin`
15			`en_cdtin : inout BIT; -- en_cdtin`
16			`c_cdtout : out BIT; -- c_cdtout`
17			`en_cdtout : out BIT; -- en_cdtout`
18			`en_out : out BIT; -- en_out`
19			`en_in : out BIT; -- en_in`
20			`finish : out BIT; -- finish`
21			`vdd : in BIT; -- vdd`
22			`vss : in BIT -- vss`
23			`);`
24			`END kontrol_utama_invadd;`
25
26			`-- Architecture Declaration`
27
28			`ARCHITECTURE VST OF kontrol_utama_invadd IS`
29			`COMPONENT oa22_x2`
30			`port (`
31			`i0 : in BIT; -- i0`
32			`i1 : in BIT; -- i1`
33			`i2 : in BIT; -- i2`
34			`q : out BIT; -- q`
35			`vdd : in BIT; -- vdd`
36			`vss : in BIT -- vss`
37			`);`
38			`END COMPONENT;`
39
40			`COMPONENT noa22_x1`
41			`port (`
42			`i0 : in BIT; -- i0`
43			`i1 : in BIT; -- i1`
44			`i2 : in BIT; -- i2`
45			`nq : out BIT; -- nq`
46			`vdd : in BIT; -- vdd`
47			`vss : in BIT -- vss`
48			`);`
49			`END COMPONENT;`
50
51			`COMPONENT no2_x1`
52			`port (`
53			`i0 : in BIT; -- i0`
54			`i1 : in BIT; -- i1`
55			`nq : out BIT; -- nq`
56			`vdd : in BIT; -- vdd`
57			`vss : in BIT -- vss`
58			`);`
59			`END COMPONENT;`
60
61			`COMPONENT o4_x2`
62			`port (`
63			`i0 : in BIT; -- i0`
64			`i1 : in BIT; -- i1`
65			`i2 : in BIT; -- i2`
66			`i3 : in BIT; -- i3`
67			`q : out BIT; -- q`
68			`vdd : in BIT; -- vdd`
69			`vss : in BIT -- vss`
70			`);`
71			`END COMPONENT;`
72
73			`COMPONENT na4_x1`
74			`port (`
75			`i0 : in BIT; -- i0`
76			`i1 : in BIT; -- i1`
77			`i2 : in BIT; -- i2`
78			`i3 : in BIT; -- i3`
79			`nq : out BIT; -- nq`
80			`vdd : in BIT; -- vdd`
81			`vss : in BIT -- vss`
82			`);`
83			`END COMPONENT;`
84
85			`COMPONENT an12_x1`
86			`port (`
87			`i0 : in BIT; -- i0`
88			`i1 : in BIT; -- i1`
89			`q : out BIT; -- q`
90			`vdd : in BIT; -- vdd`
91			`vss : in BIT -- vss`
92			`);`
93			`END COMPONENT;`
94
95			`COMPONENT no3_x1`
96			`port (`
97			`i0 : in BIT; -- i0`
98			`i1 : in BIT; -- i1`
99			`i2 : in BIT; -- i2`
100			`nq : out BIT; -- nq`
101			`vdd : in BIT; -- vdd`
102			`vss : in BIT -- vss`
103			`);`
104			`END COMPONENT;`
105
106			`COMPONENT xr2_x1`
107			`port (`
108			`i0 : in BIT; -- i0`
109			`i1 : in BIT; -- i1`
110			`q : out BIT; -- q`
111			`vdd : in BIT; -- vdd`
112			`vss : in BIT -- vss`
113			`);`
114			`END COMPONENT;`
115
116			`COMPONENT nao22_x1`
117			`port (`
118			`i0 : in BIT; -- i0`
119			`i1 : in BIT; -- i1`
120			`i2 : in BIT; -- i2`
121			`nq : out BIT; -- nq`
122			`vdd : in BIT; -- vdd`
123			`vss : in BIT -- vss`
124			`);`
125			`END COMPONENT;`
126
127			`COMPONENT a4_x2`
128			`port (`
129			`i0 : in BIT; -- i0`
130			`i1 : in BIT; -- i1`
131			`i2 : in BIT; -- i2`
132			`i3 : in BIT; -- i3`
133			`q : out BIT; -- q`
134			`vdd : in BIT; -- vdd`
135			`vss : in BIT -- vss`
136			`);`
137			`END COMPONENT;`
138
139			`COMPONENT na2_x1`
140			`port (`
141			`i0 : in BIT; -- i0`
142			`i1 : in BIT; -- i1`
143			`nq : out BIT; -- nq`
144			`vdd : in BIT; -- vdd`
145			`vss : in BIT -- vss`
146			`);`
147			`END COMPONENT;`
148
149			`COMPONENT no4_x1`
150			`port (`
151			`i0 : in BIT; -- i0`
152			`i1 : in BIT; -- i1`
153			`i2 : in BIT; -- i2`
154			`i3 : in BIT; -- i3`
155			`nq : out BIT; -- nq`
156			`vdd : in BIT; -- vdd`
157			`vss : in BIT -- vss`
158			`);`
159			`END COMPONENT;`
160
161			`COMPONENT inv_x1`
162			`port (`
163			`i : in BIT; -- i`
164			`nq : out BIT; -- nq`
165			`vdd : in BIT; -- vdd`
166			`vss : in BIT -- vss`
167			`);`
168			`END COMPONENT;`
169
170			`COMPONENT a3_x2`
171			`port (`
172			`i0 : in BIT; -- i0`
173			`i1 : in BIT; -- i1`
174			`i2 : in BIT; -- i2`
175			`q : out BIT; -- q`
176			`vdd : in BIT; -- vdd`
177			`vss : in BIT -- vss`
178			`);`
179			`END COMPONENT;`
180
181			`COMPONENT o2_x2`
182			`port (`
183			`i0 : in BIT; -- i0`
184			`i1 : in BIT; -- i1`
185			`q : out BIT; -- q`
186			`vdd : in BIT; -- vdd`
187			`vss : in BIT -- vss`
188			`);`
189			`END COMPONENT;`
190
191			`COMPONENT a2_x2`
192			`port (`
193			`i0 : in BIT; -- i0`
194			`i1 : in BIT; -- i1`
195			`q : out BIT; -- q`
196			`vdd : in BIT; -- vdd`
197			`vss : in BIT -- vss`
198			`);`
199			`END COMPONENT;`
200
201			`COMPONENT sff1_x4`
202			`port (`
203			`ck : in BIT; -- ck`
204			`i : in BIT; -- i`
205			`q : out BIT; -- q`
206			`vdd : in BIT; -- vdd`
207			`vss : in BIT -- vss`
208			`);`
209			`END COMPONENT;`
210
211			`SIGNAL aux27_a : BIT; -- aux27_a`
212			`SIGNAL auxsc9 : BIT; -- auxsc9`
213			`SIGNAL auxsc13 : BIT; -- auxsc13`
214			`SIGNAL auxsc14 : BIT; -- auxsc14`
215			`SIGNAL auxsc10 : BIT; -- auxsc10`
216			`SIGNAL auxsc17 : BIT; -- auxsc17`
217			`SIGNAL auxsc4 : BIT; -- auxsc4`
218			`SIGNAL auxsc7 : BIT; -- auxsc7`
219			`SIGNAL auxsc8 : BIT; -- auxsc8`
220			`SIGNAL auxsc6 : BIT; -- auxsc6`
221			`SIGNAL auxsc18 : BIT; -- auxsc18`
222			`SIGNAL auxsc19 : BIT; -- auxsc19`
223			`SIGNAL auxsc12 : BIT; -- auxsc12`
224			`SIGNAL auxsc65 : BIT; -- auxsc65`
225			`SIGNAL auxsc69 : BIT; -- auxsc69`
226			`SIGNAL auxsc61 : BIT; -- auxsc61`
227			`SIGNAL auxsc62 : BIT; -- auxsc62`
228			`SIGNAL auxsc80 : BIT; -- auxsc80`
229			`SIGNAL auxsc20 : BIT; -- auxsc20`
230			`SIGNAL auxsc41 : BIT; -- auxsc41`
231			`SIGNAL auxsc81 : BIT; -- auxsc81`
232			`SIGNAL auxsc82 : BIT; -- auxsc82`
233			`SIGNAL auxsc86 : BIT; -- auxsc86`
234			`SIGNAL auxsc87 : BIT; -- auxsc87`
235			`SIGNAL auxsc83 : BIT; -- auxsc83`
236			`SIGNAL auxsc84 : BIT; -- auxsc84`
237			`SIGNAL auxsc85 : BIT; -- auxsc85`
238			`SIGNAL auxsc31 : BIT; -- auxsc31`
239			`SIGNAL auxsc32 : BIT; -- auxsc32`
240			`SIGNAL auxsc26 : BIT; -- auxsc26`
241			`SIGNAL auxsc29 : BIT; -- auxsc29`
242			`SIGNAL auxsc33 : BIT; -- auxsc33`
243			`SIGNAL auxsc34 : BIT; -- auxsc34`
244			`SIGNAL auxsc44 : BIT; -- auxsc44`
245			`SIGNAL auxsc39 : BIT; -- auxsc39`
246			`SIGNAL auxsc43 : BIT; -- auxsc43`
247			`SIGNAL auxsc48 : BIT; -- auxsc48`
248			`SIGNAL auxsc50 : BIT; -- auxsc50`
249			`SIGNAL auxsc45 : BIT; -- auxsc45`
250			`SIGNAL auxsc55 : BIT; -- auxsc55`
251			`SIGNAL auxreg3 : BIT; -- auxreg3`
252			`SIGNAL auxreg2 : BIT; -- auxreg2`
253			`SIGNAL auxreg1 : BIT; -- auxreg1`
254
255			`BEGIN`
256
257			`finish : oa22_x2`
258			`PORT MAP (`
259			`vss => vss,`
260			`vdd => vdd,`
261			`q => finish,`
262			`i2 => auxsc82,`
263			`i1 => auxsc20,`
264			`i0 => auxsc80);`
265			`en_out : inv_x1`
266			`PORT MAP (`
267			`vss => vss,`
268			`vdd => vdd,`
269			`nq => en_out,`
270			`i => auxsc86);`
271			`en_cdtout : inv_x1`
272			`PORT MAP (`
273			`vss => vss,`
274			`vdd => vdd,`
275			`nq => en_cdtout,`
276			`i => auxsc87);`
277			`c_cdtout : a2_x2`
278			`PORT MAP (`
279			`vss => vss,`
280			`vdd => vdd,`
281			`q => c_cdtout,`
282			`i1 => auxsc85,`
283			`i0 => auxsc83);`
284			`auxsc55 : o4_x2`
285			`PORT MAP (`
286			`vss => vss,`
287			`vdd => vdd,`
288			`q => auxsc55,`
289			`i3 => auxsc45,`
290			`i2 => auxsc50,`
291			`i1 => auxsc48,`
292			`i0 => rst);`
293			`auxsc45 : a2_x2`
294			`PORT MAP (`
295			`vss => vss,`
296			`vdd => vdd,`
297			`q => auxsc45,`
298			`i1 => auxreg1,`
299			`i0 => auxreg2);`
300			`auxsc50 : xr2_x1`
301			`PORT MAP (`
302			`vss => vss,`
303			`vdd => vdd,`
304			`q => auxsc50,`
305			`i1 => auxreg2,`
306			`i0 => auxsc20);`
307			`auxsc48 : no2_x1`
308			`PORT MAP (`
309			`vss => vss,`
310			`vdd => vdd,`
311			`nq => auxsc48,`
312			`i1 => auxreg2,`
313			`i0 => start);`
314			`auxsc43 : oa22_x2`
315			`PORT MAP (`
316			`vss => vss,`
317			`vdd => vdd,`
318			`q => auxsc43,`
319			`i2 => auxsc39,`
320			`i1 => auxsc41,`
321			`i0 => auxsc44);`
322			`auxsc39 : noa22_x1`
323			`PORT MAP (`
324			`vss => vss,`
325			`vdd => vdd,`
326			`nq => auxsc39,`
327			`i2 => rst,`
328			`i1 => auxreg3,`
329			`i0 => auxsc19);`
330			`auxsc44 : a2_x2`
331			`PORT MAP (`
332			`vss => vss,`
333			`vdd => vdd,`
334			`q => auxsc44,`
335			`i1 => auxsc9,`
336			`i0 => start);`
337			`auxsc34 : oa22_x2`
338			`PORT MAP (`
339			`vss => vss,`
340			`vdd => vdd,`
341			`q => auxsc34,`
342			`i2 => auxsc33,`
343			`i1 => auxsc12,`
344			`i0 => auxsc32);`
345			`auxsc33 : noa22_x1`
346			`PORT MAP (`
347			`vss => vss,`
348			`vdd => vdd,`
349			`nq => auxsc33,`
350			`i2 => auxsc29,`
351			`i1 => auxreg2,`
352			`i0 => auxsc26);`
353			`auxsc29 : o2_x2`
354			`PORT MAP (`
355			`vss => vss,`
356			`vdd => vdd,`
357			`q => auxsc29,`
358			`i1 => rst,`
359			`i0 => auxreg3);`
360			`auxsc26 : inv_x1`
361			`PORT MAP (`
362			`vss => vss,`
363			`vdd => vdd,`
364			`nq => auxsc26,`
365			`i => auxreg1);`
366			`auxsc32 : no2_x1`
367			`PORT MAP (`
368			`vss => vss,`
369			`vdd => vdd,`
370			`nq => auxsc32,`
371			`i1 => auxsc20,`
372			`i0 => rst);`
373			`auxsc31 : inv_x1`
374			`PORT MAP (`
375			`vss => vss,`
376			`vdd => vdd,`
377			`nq => auxsc31,`
378			`i => clk);`
379			`auxsc85 : an12_x1`
380			`PORT MAP (`
381			`vss => vss,`
382			`vdd => vdd,`
383			`q => auxsc85,`
384			`i1 => auxreg3,`
385			`i0 => auxsc84);`
386			`auxsc84 : o4_x2`
387			`PORT MAP (`
388			`vss => vss,`
389			`vdd => vdd,`
390			`q => auxsc84,`
391			`i3 => auxreg2,`
392			`i2 => auxsc18,`
393			`i1 => auxsc61,`
394			`i0 => rst);`
395			`auxsc83 : na2_x1`
396			`PORT MAP (`
397			`vss => vss,`
398			`vdd => vdd,`
399			`nq => auxsc83,`
400			`i1 => auxsc14,`
401			`i0 => auxsc13);`
402			`auxsc87 : inv_x1`
403			`PORT MAP (`
404			`vss => vss,`
405			`vdd => vdd,`
406			`nq => auxsc87,`
407			`i => en_cdtin);`
408			`auxsc86 : inv_x1`
409			`PORT MAP (`
410			`vss => vss,`
411			`vdd => vdd,`
412			`nq => auxsc86,`
413			`i => c_cdtin);`
414			`auxsc82 : an12_x1`
415			`PORT MAP (`
416			`vss => vss,`
417			`vdd => vdd,`
418			`q => auxsc82,`
419			`i1 => auxreg3,`
420			`i0 => auxsc81);`
421			`auxsc81 : na4_x1`
422			`PORT MAP (`
423			`vss => vss,`
424			`vdd => vdd,`
425			`nq => auxsc81,`
426			`i3 => auxsc19,`
427			`i2 => auxsc41,`
428			`i1 => auxsc9,`
429			`i0 => start);`
430			`auxsc41 : an12_x1`
431			`PORT MAP (`
432			`vss => vss,`
433			`vdd => vdd,`
434			`q => auxsc41,`
435			`i1 => auxsc6,`
436			`i0 => n_dtout(0));`
437			`auxsc20 : inv_x1`
438			`PORT MAP (`
439			`vss => vss,`
440			`vdd => vdd,`
441			`nq => auxsc20,`
442			`i => auxreg3);`
443			`auxsc80 : a2_x2`
444			`PORT MAP (`
445			`vss => vss,`
446			`vdd => vdd,`
447			`q => auxsc80,`
448			`i1 => auxreg2,`
449			`i0 => auxsc9);`
450			`auxsc62 : no4_x1`
451			`PORT MAP (`
452			`vss => vss,`
453			`vdd => vdd,`
454			`nq => auxsc62,`
455			`i3 => auxreg2,`
456			`i2 => auxsc18,`
457			`i1 => auxsc61,`
458			`i0 => rst);`
459			`auxsc61 : inv_x1`
460			`PORT MAP (`
461			`vss => vss,`
462			`vdd => vdd,`
463			`nq => auxsc61,`
464			`i => start);`
465			`auxsc69 : no3_x1`
466			`PORT MAP (`
467			`vss => vss,`
468			`vdd => vdd,`
469			`nq => auxsc69,`
470			`i2 => auxreg3,`
471			`i1 => auxreg2,`
472			`i0 => rst);`
473			`auxsc65 : xr2_x1`
474			`PORT MAP (`
475			`vss => vss,`
476			`vdd => vdd,`
477			`q => auxsc65,`
478			`i1 => auxreg3,`
479			`i0 => auxsc19);`
480			`auxsc12 : nao22_x1`
481			`PORT MAP (`
482			`vss => vss,`
483			`vdd => vdd,`
484			`nq => auxsc12,`
485			`i2 => auxsc19,`
486			`i1 => auxsc18,`
487			`i0 => auxsc17);`
488			`auxsc19 : inv_x1`
489			`PORT MAP (`
490			`vss => vss,`
491			`vdd => vdd,`
492			`nq => auxsc19,`
493			`i => auxreg2);`
494			`auxsc18 : a2_x2`
495			`PORT MAP (`
496			`vss => vss,`
497			`vdd => vdd,`
498			`q => auxsc18,`
499			`i1 => auxsc6,`
500			`i0 => auxsc4);`
501			`auxsc6 : a4_x2`
502			`PORT MAP (`
503			`vss => vss,`
504			`vdd => vdd,`
505			`q => auxsc6,`
506			`i3 => auxsc8,`
507			`i2 => auxsc7,`
508			`i1 => n_dtout(4),`
509			`i0 => n_dtout(1));`
510			`auxsc8 : inv_x1`
511			`PORT MAP (`
512			`vss => vss,`
513			`vdd => vdd,`
514			`nq => auxsc8,`
515			`i => n_dtout(3));`
516			`auxsc7 : inv_x1`
517			`PORT MAP (`
518			`vss => vss,`
519			`vdd => vdd,`
520			`nq => auxsc7,`
521			`i => n_dtout(2));`
522			`auxsc4 : inv_x1`
523			`PORT MAP (`
524			`vss => vss,`
525			`vdd => vdd,`
526			`nq => auxsc4,`
527			`i => n_dtout(0));`
528			`auxsc17 : na2_x1`
529			`PORT MAP (`
530			`vss => vss,`
531			`vdd => vdd,`
532			`nq => auxsc17,`
533			`i1 => auxsc10,`
534			`i0 => start);`
535			`auxsc10 : a2_x2`
536			`PORT MAP (`
537			`vss => vss,`
538			`vdd => vdd,`
539			`q => auxsc10,`
540			`i1 => auxsc14,`
541			`i0 => auxsc13);`
542			`auxsc14 : no4_x1`
543			`PORT MAP (`
544			`vss => vss,`
545			`vdd => vdd,`
546			`nq => auxsc14,`
547			`i3 => n_dtin(4),`
548			`i2 => n_dtin(3),`
549			`i1 => n_dtin(2),`
550			`i0 => n_dtin(1));`
551			`auxsc13 : inv_x1`
552			`PORT MAP (`
553			`vss => vss,`
554			`vdd => vdd,`
555			`nq => auxsc13,`
556			`i => n_dtin(0));`
557			`auxsc9 : inv_x1`
558			`PORT MAP (`
559			`vss => vss,`
560			`vdd => vdd,`
561			`nq => auxsc9,`
562			`i => rst);`
563			`aux27_a : a3_x2`
564			`PORT MAP (`
565			`vss => vss,`
566			`vdd => vdd,`
567			`q => aux27_a,`
568			`i2 => auxsc12,`
569			`i1 => auxsc9,`
570			`i0 => auxreg3);`
571			`auxinit1_a : a2_x2`
572			`PORT MAP (`
573			`vss => vss,`
574			`vdd => vdd,`
575			`q => c_cdtin,`
576			`i1 => auxsc65,`
577			`i0 => auxsc9);`
578			`auxinit2_a : o2_x2`
579			`PORT MAP (`
580			`vss => vss,`
581			`vdd => vdd,`
582			`q => en_cdtin,`
583			`i1 => aux27_a,`
584			`i0 => auxsc69);`
585			`aux30_a : a2_x2`
586			`PORT MAP (`
587			`vss => vss,`
588			`vdd => vdd,`
589			`q => en_in,`
590			`i1 => auxreg3,`
591			`i0 => auxsc62);`
592			`current_state_0 : sff1_x4`
593			`PORT MAP (`
594			`vss => vss,`
595			`vdd => vdd,`
596			`q => auxreg1,`
597			`i => auxsc34,`
598			`ck => auxsc31);`
599			`current_state_1 : sff1_x4`
600			`PORT MAP (`
601			`vss => vss,`
602			`vdd => vdd,`
603			`q => auxreg2,`
604			`i => auxsc43,`
605			`ck => auxsc31);`
606			`current_state_2 : sff1_x4`
607			`PORT MAP (`
608			`vss => vss,`
609			`vdd => vdd,`
610			`q => auxreg3,`
611			`i => auxsc55,`
612			`ck => auxsc31);`
613
614			`end VST;`