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[/] [structural_vhdl/] [trunk/] [key_regulator/] [leftshiftregister13.vst] - Blame information for rev 4

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-- VHDL structural description generated from `leftshiftregister13`
--              date : Tue Jul 31 10:17:46 2001
 
 
-- Entity Declaration
 
ENTITY leftshiftregister13 IS
  PORT (
  p : in BIT_VECTOR (16 DOWNTO 0);      -- p
  q : in BIT;   -- q
  r : out BIT_VECTOR (33 DOWNTO 0);     -- r
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END leftshiftregister13;
 
-- Architecture Declaration
 
ARCHITECTURE VST OF leftshiftregister13 IS
  COMPONENT a2_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT zero_x0
    port (
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
 
BEGIN
 
  r_0 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(0));
  r_1 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(1));
  r_2 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(2));
  r_3 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(3));
  r_4 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(4));
  r_5 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(5));
  r_6 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(6));
  r_7 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(7));
  r_8 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(8));
  r_9 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(9));
  r_10 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(10));
  r_11 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(11));
  r_12 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(12));
  r_13 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(13),
    i1 => p(0),
    i0 => q);
  r_14 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(14),
    i1 => p(1),
    i0 => q);
  r_15 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(15),
    i1 => p(2),
    i0 => q);
  r_16 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(16),
    i1 => p(3),
    i0 => q);
  r_17 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(17),
    i1 => p(4),
    i0 => q);
  r_18 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(18),
    i1 => p(5),
    i0 => q);
  r_19 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(19),
    i1 => p(6),
    i0 => q);
  r_20 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(20),
    i1 => p(7),
    i0 => q);
  r_21 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(21),
    i1 => p(8),
    i0 => q);
  r_22 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(22),
    i1 => p(9),
    i0 => q);
  r_23 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(23),
    i1 => p(10),
    i0 => q);
  r_24 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(24),
    i1 => p(11),
    i0 => q);
  r_25 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(25),
    i1 => p(12),
    i0 => q);
  r_26 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(26),
    i1 => p(13),
    i0 => q);
  r_27 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(27),
    i1 => p(14),
    i0 => q);
  r_28 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(28),
    i1 => p(15),
    i0 => q);
  r_29 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(29),
    i1 => p(16),
    i0 => q);
  r_30 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(30));
  r_31 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(31));
  r_32 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(32));
  r_33 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(33));
 
end VST;

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Subversion Repositories structural_vhdl

[/] [structural_vhdl/] [trunk/] [key_regulator/] [leftshiftregister13.vst] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	marta	-- VHDL structural description generated from `leftshiftregister13`
2			`-- date : Tue Jul 31 10:17:46 2001`
3
4
5			`-- Entity Declaration`
6
7			`ENTITY leftshiftregister13 IS`
8			`PORT (`
9			`p : in BIT_VECTOR (16 DOWNTO 0); -- p`
10			`q : in BIT; -- q`
11			`r : out BIT_VECTOR (33 DOWNTO 0); -- r`
12			`vdd : in BIT; -- vdd`
13			`vss : in BIT -- vss`
14			`);`
15			`END leftshiftregister13;`
16
17			`-- Architecture Declaration`
18
19			`ARCHITECTURE VST OF leftshiftregister13 IS`
20			`COMPONENT a2_x2`
21			`port (`
22			`i0 : in BIT; -- i0`
23			`i1 : in BIT; -- i1`
24			`q : out BIT; -- q`
25			`vdd : in BIT; -- vdd`
26			`vss : in BIT -- vss`
27			`);`
28			`END COMPONENT;`
29
30			`COMPONENT zero_x0`
31			`port (`
32			`nq : out BIT; -- nq`
33			`vdd : in BIT; -- vdd`
34			`vss : in BIT -- vss`
35			`);`
36			`END COMPONENT;`
37
38
39			`BEGIN`
40
41			`r_0 : zero_x0`
42			`PORT MAP (`
43			`vss => vss,`
44			`vdd => vdd,`
45			`nq => r(0));`
46			`r_1 : zero_x0`
47			`PORT MAP (`
48			`vss => vss,`
49			`vdd => vdd,`
50			`nq => r(1));`
51			`r_2 : zero_x0`
52			`PORT MAP (`
53			`vss => vss,`
54			`vdd => vdd,`
55			`nq => r(2));`
56			`r_3 : zero_x0`
57			`PORT MAP (`
58			`vss => vss,`
59			`vdd => vdd,`
60			`nq => r(3));`
61			`r_4 : zero_x0`
62			`PORT MAP (`
63			`vss => vss,`
64			`vdd => vdd,`
65			`nq => r(4));`
66			`r_5 : zero_x0`
67			`PORT MAP (`
68			`vss => vss,`
69			`vdd => vdd,`
70			`nq => r(5));`
71			`r_6 : zero_x0`
72			`PORT MAP (`
73			`vss => vss,`
74			`vdd => vdd,`
75			`nq => r(6));`
76			`r_7 : zero_x0`
77			`PORT MAP (`
78			`vss => vss,`
79			`vdd => vdd,`
80			`nq => r(7));`
81			`r_8 : zero_x0`
82			`PORT MAP (`
83			`vss => vss,`
84			`vdd => vdd,`
85			`nq => r(8));`
86			`r_9 : zero_x0`
87			`PORT MAP (`
88			`vss => vss,`
89			`vdd => vdd,`
90			`nq => r(9));`
91			`r_10 : zero_x0`
92			`PORT MAP (`
93			`vss => vss,`
94			`vdd => vdd,`
95			`nq => r(10));`
96			`r_11 : zero_x0`
97			`PORT MAP (`
98			`vss => vss,`
99			`vdd => vdd,`
100			`nq => r(11));`
101			`r_12 : zero_x0`
102			`PORT MAP (`
103			`vss => vss,`
104			`vdd => vdd,`
105			`nq => r(12));`
106			`r_13 : a2_x2`
107			`PORT MAP (`
108			`vss => vss,`
109			`vdd => vdd,`
110			`q => r(13),`
111			`i1 => p(0),`
112			`i0 => q);`
113			`r_14 : a2_x2`
114			`PORT MAP (`
115			`vss => vss,`
116			`vdd => vdd,`
117			`q => r(14),`
118			`i1 => p(1),`
119			`i0 => q);`
120			`r_15 : a2_x2`
121			`PORT MAP (`
122			`vss => vss,`
123			`vdd => vdd,`
124			`q => r(15),`
125			`i1 => p(2),`
126			`i0 => q);`
127			`r_16 : a2_x2`
128			`PORT MAP (`
129			`vss => vss,`
130			`vdd => vdd,`
131			`q => r(16),`
132			`i1 => p(3),`
133			`i0 => q);`
134			`r_17 : a2_x2`
135			`PORT MAP (`
136			`vss => vss,`
137			`vdd => vdd,`
138			`q => r(17),`
139			`i1 => p(4),`
140			`i0 => q);`
141			`r_18 : a2_x2`
142			`PORT MAP (`
143			`vss => vss,`
144			`vdd => vdd,`
145			`q => r(18),`
146			`i1 => p(5),`
147			`i0 => q);`
148			`r_19 : a2_x2`
149			`PORT MAP (`
150			`vss => vss,`
151			`vdd => vdd,`
152			`q => r(19),`
153			`i1 => p(6),`
154			`i0 => q);`
155			`r_20 : a2_x2`
156			`PORT MAP (`
157			`vss => vss,`
158			`vdd => vdd,`
159			`q => r(20),`
160			`i1 => p(7),`
161			`i0 => q);`
162			`r_21 : a2_x2`
163			`PORT MAP (`
164			`vss => vss,`
165			`vdd => vdd,`
166			`q => r(21),`
167			`i1 => p(8),`
168			`i0 => q);`
169			`r_22 : a2_x2`
170			`PORT MAP (`
171			`vss => vss,`
172			`vdd => vdd,`
173			`q => r(22),`
174			`i1 => p(9),`
175			`i0 => q);`
176			`r_23 : a2_x2`
177			`PORT MAP (`
178			`vss => vss,`
179			`vdd => vdd,`
180			`q => r(23),`
181			`i1 => p(10),`
182			`i0 => q);`
183			`r_24 : a2_x2`
184			`PORT MAP (`
185			`vss => vss,`
186			`vdd => vdd,`
187			`q => r(24),`
188			`i1 => p(11),`
189			`i0 => q);`
190			`r_25 : a2_x2`
191			`PORT MAP (`
192			`vss => vss,`
193			`vdd => vdd,`
194			`q => r(25),`
195			`i1 => p(12),`
196			`i0 => q);`
197			`r_26 : a2_x2`
198			`PORT MAP (`
199			`vss => vss,`
200			`vdd => vdd,`
201			`q => r(26),`
202			`i1 => p(13),`
203			`i0 => q);`
204			`r_27 : a2_x2`
205			`PORT MAP (`
206			`vss => vss,`
207			`vdd => vdd,`
208			`q => r(27),`
209			`i1 => p(14),`
210			`i0 => q);`
211			`r_28 : a2_x2`
212			`PORT MAP (`
213			`vss => vss,`
214			`vdd => vdd,`
215			`q => r(28),`
216			`i1 => p(15),`
217			`i0 => q);`
218			`r_29 : a2_x2`
219			`PORT MAP (`
220			`vss => vss,`
221			`vdd => vdd,`
222			`q => r(29),`
223			`i1 => p(16),`
224			`i0 => q);`
225			`r_30 : zero_x0`
226			`PORT MAP (`
227			`vss => vss,`
228			`vdd => vdd,`
229			`nq => r(30));`
230			`r_31 : zero_x0`
231			`PORT MAP (`
232			`vss => vss,`
233			`vdd => vdd,`
234			`nq => r(31));`
235			`r_32 : zero_x0`
236			`PORT MAP (`
237			`vss => vss,`
238			`vdd => vdd,`
239			`nq => r(32));`
240			`r_33 : zero_x0`
241			`PORT MAP (`
242			`vss => vss,`
243			`vdd => vdd,`
244			`nq => r(33));`
245
246			`end VST;`