URL https://opencores.org/ocsvn/structural_vhdl/structural_vhdl/trunk

Subversion Repositories structural_vhdl

[/] [structural_vhdl/] [trunk/] [key_regulator/] [leftshiftregister6.vst] - Blame information for rev 4

Details | Compare with Previous | View Log


-- VHDL structural description generated from `leftshiftregister6`
--              date : Tue Jul 31 10:16:54 2001
 
 
-- Entity Declaration
 
ENTITY leftshiftregister6 IS
  PORT (
  p : in BIT_VECTOR (16 DOWNTO 0);      -- p
  q : in BIT;   -- q
  r : out BIT_VECTOR (33 DOWNTO 0);     -- r
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END leftshiftregister6;
 
-- Architecture Declaration
 
ARCHITECTURE VST OF leftshiftregister6 IS
  COMPONENT a2_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT zero_x0
    port (
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
 
BEGIN
 
  r_0 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(0));
  r_1 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(1));
  r_2 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(2));
  r_3 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(3));
  r_4 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(4));
  r_5 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(5));
  r_6 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(6),
    i1 => p(0),
    i0 => q);
  r_7 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(7),
    i1 => p(1),
    i0 => q);
  r_8 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(8),
    i1 => p(2),
    i0 => q);
  r_9 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(9),
    i1 => p(3),
    i0 => q);
  r_10 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(10),
    i1 => p(4),
    i0 => q);
  r_11 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(11),
    i1 => p(5),
    i0 => q);
  r_12 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(12),
    i1 => p(6),
    i0 => q);
  r_13 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(13),
    i1 => p(7),
    i0 => q);
  r_14 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(14),
    i1 => p(8),
    i0 => q);
  r_15 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(15),
    i1 => p(9),
    i0 => q);
  r_16 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(16),
    i1 => p(10),
    i0 => q);
  r_17 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(17),
    i1 => p(11),
    i0 => q);
  r_18 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(18),
    i1 => p(12),
    i0 => q);
  r_19 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(19),
    i1 => p(13),
    i0 => q);
  r_20 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(20),
    i1 => p(14),
    i0 => q);
  r_21 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(21),
    i1 => p(15),
    i0 => q);
  r_22 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(22),
    i1 => p(16),
    i0 => q);
  r_23 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(23));
  r_24 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(24));
  r_25 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(25));
  r_26 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(26));
  r_27 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(27));
  r_28 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(28));
  r_29 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(29));
  r_30 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(30));
  r_31 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(31));
  r_32 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(32));
  r_33 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(33));
 
end VST;

Browse

Tools

Subversion Repositories structural_vhdl

[/] [structural_vhdl/] [trunk/] [key_regulator/] [leftshiftregister6.vst] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	marta	-- VHDL structural description generated from `leftshiftregister6`
2			`-- date : Tue Jul 31 10:16:54 2001`
3
4
5			`-- Entity Declaration`
6
7			`ENTITY leftshiftregister6 IS`
8			`PORT (`
9			`p : in BIT_VECTOR (16 DOWNTO 0); -- p`
10			`q : in BIT; -- q`
11			`r : out BIT_VECTOR (33 DOWNTO 0); -- r`
12			`vdd : in BIT; -- vdd`
13			`vss : in BIT -- vss`
14			`);`
15			`END leftshiftregister6;`
16
17			`-- Architecture Declaration`
18
19			`ARCHITECTURE VST OF leftshiftregister6 IS`
20			`COMPONENT a2_x2`
21			`port (`
22			`i0 : in BIT; -- i0`
23			`i1 : in BIT; -- i1`
24			`q : out BIT; -- q`
25			`vdd : in BIT; -- vdd`
26			`vss : in BIT -- vss`
27			`);`
28			`END COMPONENT;`
29
30			`COMPONENT zero_x0`
31			`port (`
32			`nq : out BIT; -- nq`
33			`vdd : in BIT; -- vdd`
34			`vss : in BIT -- vss`
35			`);`
36			`END COMPONENT;`
37
38
39			`BEGIN`
40
41			`r_0 : zero_x0`
42			`PORT MAP (`
43			`vss => vss,`
44			`vdd => vdd,`
45			`nq => r(0));`
46			`r_1 : zero_x0`
47			`PORT MAP (`
48			`vss => vss,`
49			`vdd => vdd,`
50			`nq => r(1));`
51			`r_2 : zero_x0`
52			`PORT MAP (`
53			`vss => vss,`
54			`vdd => vdd,`
55			`nq => r(2));`
56			`r_3 : zero_x0`
57			`PORT MAP (`
58			`vss => vss,`
59			`vdd => vdd,`
60			`nq => r(3));`
61			`r_4 : zero_x0`
62			`PORT MAP (`
63			`vss => vss,`
64			`vdd => vdd,`
65			`nq => r(4));`
66			`r_5 : zero_x0`
67			`PORT MAP (`
68			`vss => vss,`
69			`vdd => vdd,`
70			`nq => r(5));`
71			`r_6 : a2_x2`
72			`PORT MAP (`
73			`vss => vss,`
74			`vdd => vdd,`
75			`q => r(6),`
76			`i1 => p(0),`
77			`i0 => q);`
78			`r_7 : a2_x2`
79			`PORT MAP (`
80			`vss => vss,`
81			`vdd => vdd,`
82			`q => r(7),`
83			`i1 => p(1),`
84			`i0 => q);`
85			`r_8 : a2_x2`
86			`PORT MAP (`
87			`vss => vss,`
88			`vdd => vdd,`
89			`q => r(8),`
90			`i1 => p(2),`
91			`i0 => q);`
92			`r_9 : a2_x2`
93			`PORT MAP (`
94			`vss => vss,`
95			`vdd => vdd,`
96			`q => r(9),`
97			`i1 => p(3),`
98			`i0 => q);`
99			`r_10 : a2_x2`
100			`PORT MAP (`
101			`vss => vss,`
102			`vdd => vdd,`
103			`q => r(10),`
104			`i1 => p(4),`
105			`i0 => q);`
106			`r_11 : a2_x2`
107			`PORT MAP (`
108			`vss => vss,`
109			`vdd => vdd,`
110			`q => r(11),`
111			`i1 => p(5),`
112			`i0 => q);`
113			`r_12 : a2_x2`
114			`PORT MAP (`
115			`vss => vss,`
116			`vdd => vdd,`
117			`q => r(12),`
118			`i1 => p(6),`
119			`i0 => q);`
120			`r_13 : a2_x2`
121			`PORT MAP (`
122			`vss => vss,`
123			`vdd => vdd,`
124			`q => r(13),`
125			`i1 => p(7),`
126			`i0 => q);`
127			`r_14 : a2_x2`
128			`PORT MAP (`
129			`vss => vss,`
130			`vdd => vdd,`
131			`q => r(14),`
132			`i1 => p(8),`
133			`i0 => q);`
134			`r_15 : a2_x2`
135			`PORT MAP (`
136			`vss => vss,`
137			`vdd => vdd,`
138			`q => r(15),`
139			`i1 => p(9),`
140			`i0 => q);`
141			`r_16 : a2_x2`
142			`PORT MAP (`
143			`vss => vss,`
144			`vdd => vdd,`
145			`q => r(16),`
146			`i1 => p(10),`
147			`i0 => q);`
148			`r_17 : a2_x2`
149			`PORT MAP (`
150			`vss => vss,`
151			`vdd => vdd,`
152			`q => r(17),`
153			`i1 => p(11),`
154			`i0 => q);`
155			`r_18 : a2_x2`
156			`PORT MAP (`
157			`vss => vss,`
158			`vdd => vdd,`
159			`q => r(18),`
160			`i1 => p(12),`
161			`i0 => q);`
162			`r_19 : a2_x2`
163			`PORT MAP (`
164			`vss => vss,`
165			`vdd => vdd,`
166			`q => r(19),`
167			`i1 => p(13),`
168			`i0 => q);`
169			`r_20 : a2_x2`
170			`PORT MAP (`
171			`vss => vss,`
172			`vdd => vdd,`
173			`q => r(20),`
174			`i1 => p(14),`
175			`i0 => q);`
176			`r_21 : a2_x2`
177			`PORT MAP (`
178			`vss => vss,`
179			`vdd => vdd,`
180			`q => r(21),`
181			`i1 => p(15),`
182			`i0 => q);`
183			`r_22 : a2_x2`
184			`PORT MAP (`
185			`vss => vss,`
186			`vdd => vdd,`
187			`q => r(22),`
188			`i1 => p(16),`
189			`i0 => q);`
190			`r_23 : zero_x0`
191			`PORT MAP (`
192			`vss => vss,`
193			`vdd => vdd,`
194			`nq => r(23));`
195			`r_24 : zero_x0`
196			`PORT MAP (`
197			`vss => vss,`
198			`vdd => vdd,`
199			`nq => r(24));`
200			`r_25 : zero_x0`
201			`PORT MAP (`
202			`vss => vss,`
203			`vdd => vdd,`
204			`nq => r(25));`
205			`r_26 : zero_x0`
206			`PORT MAP (`
207			`vss => vss,`
208			`vdd => vdd,`
209			`nq => r(26));`
210			`r_27 : zero_x0`
211			`PORT MAP (`
212			`vss => vss,`
213			`vdd => vdd,`
214			`nq => r(27));`
215			`r_28 : zero_x0`
216			`PORT MAP (`
217			`vss => vss,`
218			`vdd => vdd,`
219			`nq => r(28));`
220			`r_29 : zero_x0`
221			`PORT MAP (`
222			`vss => vss,`
223			`vdd => vdd,`
224			`nq => r(29));`
225			`r_30 : zero_x0`
226			`PORT MAP (`
227			`vss => vss,`
228			`vdd => vdd,`
229			`nq => r(30));`
230			`r_31 : zero_x0`
231			`PORT MAP (`
232			`vss => vss,`
233			`vdd => vdd,`
234			`nq => r(31));`
235			`r_32 : zero_x0`
236			`PORT MAP (`
237			`vss => vss,`
238			`vdd => vdd,`
239			`nq => r(32));`
240			`r_33 : zero_x0`
241			`PORT MAP (`
242			`vss => vss,`
243			`vdd => vdd,`
244			`nq => r(33));`
245
246			`end VST;`