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[/] [structural_vhdl/] [trunk/] [key_regulator/] [mux12to6_latch.vst] - Blame information for rev 4

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1 2 marta 
-- VHDL structural description generated from `mux12to6_latch`
2 
--              date : Sat Jul 28 16:30:45 2001
3 
 
4 
 
5 
-- Entity Declaration
6 
 
7 
ENTITY mux12to6_latch IS
8 
  PORT (
9 
  i1 : in BIT_VECTOR (15 DOWNTO 0);     -- i1
10 
  i2 : in BIT_VECTOR (15 DOWNTO 0);     -- i2
11 
  i3 : in BIT_VECTOR (15 DOWNTO 0);     -- i3
12 
  i4 : in BIT_VECTOR (15 DOWNTO 0);     -- i4
13 
  i5 : in BIT_VECTOR (15 DOWNTO 0);     -- i5
14 
  i6 : in BIT_VECTOR (15 DOWNTO 0);     -- i6
15 
  i7 : in BIT_VECTOR (15 DOWNTO 0);     -- i7
16 
  i8 : in BIT_VECTOR (15 DOWNTO 0);     -- i8
17 
  i9 : in BIT_VECTOR (15 DOWNTO 0);     -- i9
18 
  i10 : in BIT_VECTOR (15 DOWNTO 0);    -- i10
19 
  i11 : in BIT_VECTOR (15 DOWNTO 0);    -- i11
20 
  i12 : in BIT_VECTOR (15 DOWNTO 0);    -- i12
21 
  en : in BIT;  -- en
22 
  clr : in BIT; -- clr
23 
  sel : in BIT; -- sel
24 
  cke : in BIT; -- cke
25 
  o1 : inout BIT_VECTOR (15 DOWNTO 0);  -- o1
26 
  o2 : inout BIT_VECTOR (15 DOWNTO 0);  -- o2
27 
  o3 : inout BIT_VECTOR (15 DOWNTO 0);  -- o3
28 
  o4 : inout BIT_VECTOR (15 DOWNTO 0);  -- o4
29 
  o5 : inout BIT_VECTOR (15 DOWNTO 0);  -- o5
30 
  o6 : inout BIT_VECTOR (15 DOWNTO 0);  -- o6
31 
  vdd : in BIT; -- vdd
32 
  vss : in BIT  -- vss
33 
  );
34 
END mux12to6_latch;
35 
 
36 
-- Architecture Declaration
37 
 
38 
ARCHITECTURE VST OF mux12to6_latch IS
39 
  COMPONENT mux12to6
40 
    port (
41 
    i1 : in BIT_VECTOR(15 DOWNTO 0);    -- i1
42 
    i2 : in BIT_VECTOR(15 DOWNTO 0);    -- i2
43 
    i3 : in BIT_VECTOR(15 DOWNTO 0);    -- i3
44 
    i4 : in BIT_VECTOR(15 DOWNTO 0);    -- i4
45 
    i5 : in BIT_VECTOR(15 DOWNTO 0);    -- i5
46 
    i6 : in BIT_VECTOR(15 DOWNTO 0);    -- i6
47 
    i7 : in BIT_VECTOR(15 DOWNTO 0);    -- i7
48 
    i8 : in BIT_VECTOR(15 DOWNTO 0);    -- i8
49 
    i9 : in BIT_VECTOR(15 DOWNTO 0);    -- i9
50 
    i10 : in BIT_VECTOR(15 DOWNTO 0);   -- i10
51 
    i11 : in BIT_VECTOR(15 DOWNTO 0);   -- i11
52 
    i12 : in BIT_VECTOR(15 DOWNTO 0);   -- i12
53 
    en : in BIT;        -- en
54 
    clr : in BIT;       -- clr
55 
    sel : in BIT;       -- sel
56 
    o1 : out BIT_VECTOR(15 DOWNTO 0);   -- o1
57 
    o2 : out BIT_VECTOR(15 DOWNTO 0);   -- o2
58 
    o3 : out BIT_VECTOR(15 DOWNTO 0);   -- o3
59 
    o4 : out BIT_VECTOR(15 DOWNTO 0);   -- o4
60 
    o5 : out BIT_VECTOR(15 DOWNTO 0);   -- o5
61 
    o6 : out BIT_VECTOR(15 DOWNTO 0);   -- o6
62 
    vdd : in BIT;       -- vdd
63 
    vss : in BIT        -- vss
64 
    );
65 
  END COMPONENT;
66 
 
67 
  COMPONENT latch
68 
    port (
69 
    a : in BIT; -- a
70 
    en : in BIT;        -- en
71 
    b : inout BIT;      -- b
72 
    vdd : in BIT;       -- vdd
73 
    vss : in BIT        -- vss
74 
    );
75 
  END COMPONENT;
76 
 
77 
  SIGNAL x1_0 : BIT;    -- x1 0
78 
  SIGNAL x1_1 : BIT;    -- x1 1
79 
  SIGNAL x1_2 : BIT;    -- x1 2
80 
  SIGNAL x1_3 : BIT;    -- x1 3
81 
  SIGNAL x1_4 : BIT;    -- x1 4
82 
  SIGNAL x1_5 : BIT;    -- x1 5
83 
  SIGNAL x1_6 : BIT;    -- x1 6
84 
  SIGNAL x1_7 : BIT;    -- x1 7
85 
  SIGNAL x1_8 : BIT;    -- x1 8
86 
  SIGNAL x1_9 : BIT;    -- x1 9
87 
  SIGNAL x1_10 : BIT;   -- x1 10
88 
  SIGNAL x1_11 : BIT;   -- x1 11
89 
  SIGNAL x1_12 : BIT;   -- x1 12
90 
  SIGNAL x1_13 : BIT;   -- x1 13
91 
  SIGNAL x1_14 : BIT;   -- x1 14
92 
  SIGNAL x1_15 : BIT;   -- x1 15
93 
  SIGNAL x2_0 : BIT;    -- x2 0
94 
  SIGNAL x2_1 : BIT;    -- x2 1
95 
  SIGNAL x2_2 : BIT;    -- x2 2
96 
  SIGNAL x2_3 : BIT;    -- x2 3
97 
  SIGNAL x2_4 : BIT;    -- x2 4
98 
  SIGNAL x2_5 : BIT;    -- x2 5
99 
  SIGNAL x2_6 : BIT;    -- x2 6
100 
  SIGNAL x2_7 : BIT;    -- x2 7
101 
  SIGNAL x2_8 : BIT;    -- x2 8
102 
  SIGNAL x2_9 : BIT;    -- x2 9
103 
  SIGNAL x2_10 : BIT;   -- x2 10
104 
  SIGNAL x2_11 : BIT;   -- x2 11
105 
  SIGNAL x2_12 : BIT;   -- x2 12
106 
  SIGNAL x2_13 : BIT;   -- x2 13
107 
  SIGNAL x2_14 : BIT;   -- x2 14
108 
  SIGNAL x2_15 : BIT;   -- x2 15
109 
  SIGNAL x3_0 : BIT;    -- x3 0
110 
  SIGNAL x3_1 : BIT;    -- x3 1
111 
  SIGNAL x3_2 : BIT;    -- x3 2
112 
  SIGNAL x3_3 : BIT;    -- x3 3
113 
  SIGNAL x3_4 : BIT;    -- x3 4
114 
  SIGNAL x3_5 : BIT;    -- x3 5
115 
  SIGNAL x3_6 : BIT;    -- x3 6
116 
  SIGNAL x3_7 : BIT;    -- x3 7
117 
  SIGNAL x3_8 : BIT;    -- x3 8
118 
  SIGNAL x3_9 : BIT;    -- x3 9
119 
  SIGNAL x3_10 : BIT;   -- x3 10
120 
  SIGNAL x3_11 : BIT;   -- x3 11
121 
  SIGNAL x3_12 : BIT;   -- x3 12
122 
  SIGNAL x3_13 : BIT;   -- x3 13
123 
  SIGNAL x3_14 : BIT;   -- x3 14
124 
  SIGNAL x3_15 : BIT;   -- x3 15
125 
  SIGNAL x4_0 : BIT;    -- x4 0
126 
  SIGNAL x4_1 : BIT;    -- x4 1
127 
  SIGNAL x4_2 : BIT;    -- x4 2
128 
  SIGNAL x4_3 : BIT;    -- x4 3
129 
  SIGNAL x4_4 : BIT;    -- x4 4
130 
  SIGNAL x4_5 : BIT;    -- x4 5
131 
  SIGNAL x4_6 : BIT;    -- x4 6
132 
  SIGNAL x4_7 : BIT;    -- x4 7
133 
  SIGNAL x4_8 : BIT;    -- x4 8
134 
  SIGNAL x4_9 : BIT;    -- x4 9
135 
  SIGNAL x4_10 : BIT;   -- x4 10
136 
  SIGNAL x4_11 : BIT;   -- x4 11
137 
  SIGNAL x4_12 : BIT;   -- x4 12
138 
  SIGNAL x4_13 : BIT;   -- x4 13
139 
  SIGNAL x4_14 : BIT;   -- x4 14
140 
  SIGNAL x4_15 : BIT;   -- x4 15
141 
  SIGNAL x5_0 : BIT;    -- x5 0
142 
  SIGNAL x5_1 : BIT;    -- x5 1
143 
  SIGNAL x5_2 : BIT;    -- x5 2
144 
  SIGNAL x5_3 : BIT;    -- x5 3
145 
  SIGNAL x5_4 : BIT;    -- x5 4
146 
  SIGNAL x5_5 : BIT;    -- x5 5
147 
  SIGNAL x5_6 : BIT;    -- x5 6
148 
  SIGNAL x5_7 : BIT;    -- x5 7
149 
  SIGNAL x5_8 : BIT;    -- x5 8
150 
  SIGNAL x5_9 : BIT;    -- x5 9
151 
  SIGNAL x5_10 : BIT;   -- x5 10
152 
  SIGNAL x5_11 : BIT;   -- x5 11
153 
  SIGNAL x5_12 : BIT;   -- x5 12
154 
  SIGNAL x5_13 : BIT;   -- x5 13
155 
  SIGNAL x5_14 : BIT;   -- x5 14
156 
  SIGNAL x5_15 : BIT;   -- x5 15
157 
  SIGNAL x6_0 : BIT;    -- x6 0
158 
  SIGNAL x6_1 : BIT;    -- x6 1
159 
  SIGNAL x6_2 : BIT;    -- x6 2
160 
  SIGNAL x6_3 : BIT;    -- x6 3
161 
  SIGNAL x6_4 : BIT;    -- x6 4
162 
  SIGNAL x6_5 : BIT;    -- x6 5
163 
  SIGNAL x6_6 : BIT;    -- x6 6
164 
  SIGNAL x6_7 : BIT;    -- x6 7
165 
  SIGNAL x6_8 : BIT;    -- x6 8
166 
  SIGNAL x6_9 : BIT;    -- x6 9
167 
  SIGNAL x6_10 : BIT;   -- x6 10
168 
  SIGNAL x6_11 : BIT;   -- x6 11
169 
  SIGNAL x6_12 : BIT;   -- x6 12
170 
  SIGNAL x6_13 : BIT;   -- x6 13
171 
  SIGNAL x6_14 : BIT;   -- x6 14
172 
  SIGNAL x6_15 : BIT;   -- x6 15
173 
 
174 
BEGIN
175 
 
176 
  mux1 : mux12to6
177 
    PORT MAP (
178 
    vss => vss,
179 
    vdd => vdd,
180 
    o6 => x6_15& x6_14& x6_13& x6_12& x6_11& x6_10& x6_9& x6_8& x6_7& x6_6& x6_5& x6_4& x6_3& x6_2& x6_1& x6_0,
181 
    o5 => x5_15& x5_14& x5_13& x5_12& x5_11& x5_10& x5_9& x5_8& x5_7& x5_6& x5_5& x5_4& x5_3& x5_2& x5_1& x5_0,
182 
    o4 => x4_15& x4_14& x4_13& x4_12& x4_11& x4_10& x4_9& x4_8& x4_7& x4_6& x4_5& x4_4& x4_3& x4_2& x4_1& x4_0,
183 
    o3 => x3_15& x3_14& x3_13& x3_12& x3_11& x3_10& x3_9& x3_8& x3_7& x3_6& x3_5& x3_4& x3_3& x3_2& x3_1& x3_0,
184 
    o2 => x2_15& x2_14& x2_13& x2_12& x2_11& x2_10& x2_9& x2_8& x2_7& x2_6& x2_5& x2_4& x2_3& x2_2& x2_1& x2_0,
185 
    o1 => x1_15& x1_14& x1_13& x1_12& x1_11& x1_10& x1_9& x1_8& x1_7& x1_6& x1_5& x1_4& x1_3& x1_2& x1_1& x1_0,
186 
    sel => sel,
187 
    clr => clr,
188 
    en => en,
189 
    i12 => i12(15)& i12(14)& i12(13)& i12(12)& i12(11)& i12(10)& i12(9)& i12(8)& i12(7)& i12(6)& i12(5)& i12(4)& i12(3)& i12(2)& i12(1)& i12(0),
190 
    i11 => i11(15)& i11(14)& i11(13)& i11(12)& i11(11)& i11(10)& i11(9)& i11(8)& i11(7)& i11(6)& i11(5)& i11(4)& i11(3)& i11(2)& i11(1)& i11(0),
191 
    i10 => i10(15)& i10(14)& i10(13)& i10(12)& i10(11)& i10(10)& i10(9)& i10(8)& i10(7)& i10(6)& i10(5)& i10(4)& i10(3)& i10(2)& i10(1)& i10(0),
192 
    i9 => i9(15)& i9(14)& i9(13)& i9(12)& i9(11)& i9(10)& i9(9)& i9(8)& i9(7)& i9(6)& i9(5)& i9(4)& i9(3)& i9(2)& i9(1)& i9(0),
193 
    i8 => i8(15)& i8(14)& i8(13)& i8(12)& i8(11)& i8(10)& i8(9)& i8(8)& i8(7)& i8(6)& i8(5)& i8(4)& i8(3)& i8(2)& i8(1)& i8(0),
194 
    i7 => i7(15)& i7(14)& i7(13)& i7(12)& i7(11)& i7(10)& i7(9)& i7(8)& i7(7)& i7(6)& i7(5)& i7(4)& i7(3)& i7(2)& i7(1)& i7(0),
195 
    i6 => i6(15)& i6(14)& i6(13)& i6(12)& i6(11)& i6(10)& i6(9)& i6(8)& i6(7)& i6(6)& i6(5)& i6(4)& i6(3)& i6(2)& i6(1)& i6(0),
196 
    i5 => i5(15)& i5(14)& i5(13)& i5(12)& i5(11)& i5(10)& i5(9)& i5(8)& i5(7)& i5(6)& i5(5)& i5(4)& i5(3)& i5(2)& i5(1)& i5(0),
197 
    i4 => i4(15)& i4(14)& i4(13)& i4(12)& i4(11)& i4(10)& i4(9)& i4(8)& i4(7)& i4(6)& i4(5)& i4(4)& i4(3)& i4(2)& i4(1)& i4(0),
198 
    i3 => i3(15)& i3(14)& i3(13)& i3(12)& i3(11)& i3(10)& i3(9)& i3(8)& i3(7)& i3(6)& i3(5)& i3(4)& i3(3)& i3(2)& i3(1)& i3(0),
199 
    i2 => i2(15)& i2(14)& i2(13)& i2(12)& i2(11)& i2(10)& i2(9)& i2(8)& i2(7)& i2(6)& i2(5)& i2(4)& i2(3)& i2(2)& i2(1)& i2(0),
200 
    i1 => i1(15)& i1(14)& i1(13)& i1(12)& i1(11)& i1(10)& i1(9)& i1(8)& i1(7)& i1(6)& i1(5)& i1(4)& i1(3)& i1(2)& i1(1)& i1(0));
201 
  latch0 : latch
202 
    PORT MAP (
203 
    vss => vss,
204 
    vdd => vdd,
205 
    b => o1(0),
206 
    en => cke,
207 
    a => x1_0);
208 
  latch16 : latch
209 
    PORT MAP (
210 
    vss => vss,
211 
    vdd => vdd,
212 
    b => o2(0),
213 
    en => cke,
214 
    a => x2_0);
215 
  latch32 : latch
216 
    PORT MAP (
217 
    vss => vss,
218 
    vdd => vdd,
219 
    b => o3(0),
220 
    en => cke,
221 
    a => x3_0);
222 
  latch48 : latch
223 
    PORT MAP (
224 
    vss => vss,
225 
    vdd => vdd,
226 
    b => o4(0),
227 
    en => cke,
228 
    a => x4_0);
229 
  latch64 : latch
230 
    PORT MAP (
231 
    vss => vss,
232 
    vdd => vdd,
233 
    b => o5(0),
234 
    en => cke,
235 
    a => x5_0);
236 
  latch80 : latch
237 
    PORT MAP (
238 
    vss => vss,
239 
    vdd => vdd,
240 
    b => o6(0),
241 
    en => cke,
242 
    a => x6_0);
243 
  latch1 : latch
244 
    PORT MAP (
245 
    vss => vss,
246 
    vdd => vdd,
247 
    b => o1(1),
248 
    en => cke,
249 
    a => x1_1);
250 
  latch17 : latch
251 
    PORT MAP (
252 
    vss => vss,
253 
    vdd => vdd,
254 
    b => o2(1),
255 
    en => cke,
256 
    a => x2_1);
257 
  latch33 : latch
258 
    PORT MAP (
259 
    vss => vss,
260 
    vdd => vdd,
261 
    b => o3(1),
262 
    en => cke,
263 
    a => x3_1);
264 
  latch49 : latch
265 
    PORT MAP (
266 
    vss => vss,
267 
    vdd => vdd,
268 
    b => o4(1),
269 
    en => cke,
270 
    a => x4_1);
271 
  latch65 : latch
272 
    PORT MAP (
273 
    vss => vss,
274 
    vdd => vdd,
275 
    b => o5(1),
276 
    en => cke,
277 
    a => x5_1);
278 
  latch81 : latch
279 
    PORT MAP (
280 
    vss => vss,
281 
    vdd => vdd,
282 
    b => o6(1),
283 
    en => cke,
284 
    a => x6_1);
285 
  latch2 : latch
286 
    PORT MAP (
287 
    vss => vss,
288 
    vdd => vdd,
289 
    b => o1(2),
290 
    en => cke,
291 
    a => x1_2);
292 
  latch18 : latch
293 
    PORT MAP (
294 
    vss => vss,
295 
    vdd => vdd,
296 
    b => o2(2),
297 
    en => cke,
298 
    a => x2_2);
299 
  latch34 : latch
300 
    PORT MAP (
301 
    vss => vss,
302 
    vdd => vdd,
303 
    b => o3(2),
304 
    en => cke,
305 
    a => x3_2);
306 
  latch50 : latch
307 
    PORT MAP (
308 
    vss => vss,
309 
    vdd => vdd,
310 
    b => o4(2),
311 
    en => cke,
312 
    a => x4_2);
313 
  latch66 : latch
314 
    PORT MAP (
315 
    vss => vss,
316 
    vdd => vdd,
317 
    b => o5(2),
318 
    en => cke,
319 
    a => x5_2);
320 
  latch82 : latch
321 
    PORT MAP (
322 
    vss => vss,
323 
    vdd => vdd,
324 
    b => o6(2),
325 
    en => cke,
326 
    a => x6_2);
327 
  latch3 : latch
328 
    PORT MAP (
329 
    vss => vss,
330 
    vdd => vdd,
331 
    b => o1(3),
332 
    en => cke,
333 
    a => x1_3);
334 
  latch19 : latch
335 
    PORT MAP (
336 
    vss => vss,
337 
    vdd => vdd,
338 
    b => o2(3),
339 
    en => cke,
340 
    a => x2_3);
341 
  latch35 : latch
342 
    PORT MAP (
343 
    vss => vss,
344 
    vdd => vdd,
345 
    b => o3(3),
346 
    en => cke,
347 
    a => x3_3);
348 
  latch51 : latch
349 
    PORT MAP (
350 
    vss => vss,
351 
    vdd => vdd,
352 
    b => o4(3),
353 
    en => cke,
354 
    a => x4_3);
355 
  latch67 : latch
356 
    PORT MAP (
357 
    vss => vss,
358 
    vdd => vdd,
359 
    b => o5(3),
360 
    en => cke,
361 
    a => x5_3);
362 
  latch83 : latch
363 
    PORT MAP (
364 
    vss => vss,
365 
    vdd => vdd,
366 
    b => o6(3),
367 
    en => cke,
368 
    a => x6_3);
369 
  latch4 : latch
370 
    PORT MAP (
371 
    vss => vss,
372 
    vdd => vdd,
373 
    b => o1(4),
374 
    en => cke,
375 
    a => x1_4);
376 
  latch20 : latch
377 
    PORT MAP (
378 
    vss => vss,
379 
    vdd => vdd,
380 
    b => o2(4),
381 
    en => cke,
382 
    a => x2_4);
383 
  latch36 : latch
384 
    PORT MAP (
385 
    vss => vss,
386 
    vdd => vdd,
387 
    b => o3(4),
388 
    en => cke,
389 
    a => x3_4);
390 
  latch52 : latch
391 
    PORT MAP (
392 
    vss => vss,
393 
    vdd => vdd,
394 
    b => o4(4),
395 
    en => cke,
396 
    a => x4_4);
397 
  latch68 : latch
398 
    PORT MAP (
399 
    vss => vss,
400 
    vdd => vdd,
401 
    b => o5(4),
402 
    en => cke,
403 
    a => x5_4);
404 
  latch84 : latch
405 
    PORT MAP (
406 
    vss => vss,
407 
    vdd => vdd,
408 
    b => o6(4),
409 
    en => cke,
410 
    a => x6_4);
411 
  latch5 : latch
412 
    PORT MAP (
413 
    vss => vss,
414 
    vdd => vdd,
415 
    b => o1(5),
416 
    en => cke,
417 
    a => x1_5);
418 
  latch21 : latch
419 
    PORT MAP (
420 
    vss => vss,
421 
    vdd => vdd,
422 
    b => o2(5),
423 
    en => cke,
424 
    a => x2_5);
425 
  latch37 : latch
426 
    PORT MAP (
427 
    vss => vss,
428 
    vdd => vdd,
429 
    b => o3(5),
430 
    en => cke,
431 
    a => x3_5);
432 
  latch53 : latch
433 
    PORT MAP (
434 
    vss => vss,
435 
    vdd => vdd,
436 
    b => o4(5),
437 
    en => cke,
438 
    a => x4_5);
439 
  latch69 : latch
440 
    PORT MAP (
441 
    vss => vss,
442 
    vdd => vdd,
443 
    b => o5(5),
444 
    en => cke,
445 
    a => x5_5);
446 
  latch85 : latch
447 
    PORT MAP (
448 
    vss => vss,
449 
    vdd => vdd,
450 
    b => o6(5),
451 
    en => cke,
452 
    a => x6_5);
453 
  latch6 : latch
454 
    PORT MAP (
455 
    vss => vss,
456 
    vdd => vdd,
457 
    b => o1(6),
458 
    en => cke,
459 
    a => x1_6);
460 
  latch22 : latch
461 
    PORT MAP (
462 
    vss => vss,
463 
    vdd => vdd,
464 
    b => o2(6),
465 
    en => cke,
466 
    a => x2_6);
467 
  latch38 : latch
468 
    PORT MAP (
469 
    vss => vss,
470 
    vdd => vdd,
471 
    b => o3(6),
472 
    en => cke,
473 
    a => x3_6);
474 
  latch54 : latch
475 
    PORT MAP (
476 
    vss => vss,
477 
    vdd => vdd,
478 
    b => o4(6),
479 
    en => cke,
480 
    a => x4_6);
481 
  latch70 : latch
482 
    PORT MAP (
483 
    vss => vss,
484 
    vdd => vdd,
485 
    b => o5(6),
486 
    en => cke,
487 
    a => x5_6);
488 
  latch86 : latch
489 
    PORT MAP (
490 
    vss => vss,
491 
    vdd => vdd,
492 
    b => o6(6),
493 
    en => cke,
494 
    a => x6_6);
495 
  latch7 : latch
496 
    PORT MAP (
497 
    vss => vss,
498 
    vdd => vdd,
499 
    b => o1(7),
500 
    en => cke,
501 
    a => x1_7);
502 
  latch23 : latch
503 
    PORT MAP (
504 
    vss => vss,
505 
    vdd => vdd,
506 
    b => o2(7),
507 
    en => cke,
508 
    a => x2_7);
509 
  latch39 : latch
510 
    PORT MAP (
511 
    vss => vss,
512 
    vdd => vdd,
513 
    b => o3(7),
514 
    en => cke,
515 
    a => x3_7);
516 
  latch55 : latch
517 
    PORT MAP (
518 
    vss => vss,
519 
    vdd => vdd,
520 
    b => o4(7),
521 
    en => cke,
522 
    a => x4_7);
523 
  latch71 : latch
524 
    PORT MAP (
525 
    vss => vss,
526 
    vdd => vdd,
527 
    b => o5(7),
528 
    en => cke,
529 
    a => x5_7);
530 
  latch87 : latch
531 
    PORT MAP (
532 
    vss => vss,
533 
    vdd => vdd,
534 
    b => o6(7),
535 
    en => cke,
536 
    a => x6_7);
537 
  latch8 : latch
538 
    PORT MAP (
539 
    vss => vss,
540 
    vdd => vdd,
541 
    b => o1(8),
542 
    en => cke,
543 
    a => x1_8);
544 
  latch24 : latch
545 
    PORT MAP (
546 
    vss => vss,
547 
    vdd => vdd,
548 
    b => o2(8),
549 
    en => cke,
550 
    a => x2_8);
551 
  latch40 : latch
552 
    PORT MAP (
553 
    vss => vss,
554 
    vdd => vdd,
555 
    b => o3(8),
556 
    en => cke,
557 
    a => x3_8);
558 
  latch56 : latch
559 
    PORT MAP (
560 
    vss => vss,
561 
    vdd => vdd,
562 
    b => o4(8),
563 
    en => cke,
564 
    a => x4_8);
565 
  latch72 : latch
566 
    PORT MAP (
567 
    vss => vss,
568 
    vdd => vdd,
569 
    b => o5(8),
570 
    en => cke,
571 
    a => x5_8);
572 
  latch88 : latch
573 
    PORT MAP (
574 
    vss => vss,
575 
    vdd => vdd,
576 
    b => o6(8),
577 
    en => cke,
578 
    a => x6_8);
579 
  latch9 : latch
580 
    PORT MAP (
581 
    vss => vss,
582 
    vdd => vdd,
583 
    b => o1(9),
584 
    en => cke,
585 
    a => x1_9);
586 
  latch25 : latch
587 
    PORT MAP (
588 
    vss => vss,
589 
    vdd => vdd,
590 
    b => o2(9),
591 
    en => cke,
592 
    a => x2_9);
593 
  latch41 : latch
594 
    PORT MAP (
595 
    vss => vss,
596 
    vdd => vdd,
597 
    b => o3(9),
598 
    en => cke,
599 
    a => x3_9);
600 
  latch57 : latch
601 
    PORT MAP (
602 
    vss => vss,
603 
    vdd => vdd,
604 
    b => o4(9),
605 
    en => cke,
606 
    a => x4_9);
607 
  latch73 : latch
608 
    PORT MAP (
609 
    vss => vss,
610 
    vdd => vdd,
611 
    b => o5(9),
612 
    en => cke,
613 
    a => x5_9);
614 
  latch89 : latch
615 
    PORT MAP (
616 
    vss => vss,
617 
    vdd => vdd,
618 
    b => o6(9),
619 
    en => cke,
620 
    a => x6_9);
621 
  latch10 : latch
622 
    PORT MAP (
623 
    vss => vss,
624 
    vdd => vdd,
625 
    b => o1(10),
626 
    en => cke,
627 
    a => x1_10);
628 
  latch26 : latch
629 
    PORT MAP (
630 
    vss => vss,
631 
    vdd => vdd,
632 
    b => o2(10),
633 
    en => cke,
634 
    a => x2_10);
635 
  latch42 : latch
636 
    PORT MAP (
637 
    vss => vss,
638 
    vdd => vdd,
639 
    b => o3(10),
640 
    en => cke,
641 
    a => x3_10);
642 
  latch58 : latch
643 
    PORT MAP (
644 
    vss => vss,
645 
    vdd => vdd,
646 
    b => o4(10),
647 
    en => cke,
648 
    a => x4_10);
649 
  latch74 : latch
650 
    PORT MAP (
651 
    vss => vss,
652 
    vdd => vdd,
653 
    b => o5(10),
654 
    en => cke,
655 
    a => x5_10);
656 
  latch90 : latch
657 
    PORT MAP (
658 
    vss => vss,
659 
    vdd => vdd,
660 
    b => o6(10),
661 
    en => cke,
662 
    a => x6_10);
663 
  latch11 : latch
664 
    PORT MAP (
665 
    vss => vss,
666 
    vdd => vdd,
667 
    b => o1(11),
668 
    en => cke,
669 
    a => x1_11);
670 
  latch27 : latch
671 
    PORT MAP (
672 
    vss => vss,
673 
    vdd => vdd,
674 
    b => o2(11),
675 
    en => cke,
676 
    a => x2_11);
677 
  latch43 : latch
678 
    PORT MAP (
679 
    vss => vss,
680 
    vdd => vdd,
681 
    b => o3(11),
682 
    en => cke,
683 
    a => x3_11);
684 
  latch59 : latch
685 
    PORT MAP (
686 
    vss => vss,
687 
    vdd => vdd,
688 
    b => o4(11),
689 
    en => cke,
690 
    a => x4_11);
691 
  latch75 : latch
692 
    PORT MAP (
693 
    vss => vss,
694 
    vdd => vdd,
695 
    b => o5(11),
696 
    en => cke,
697 
    a => x5_11);
698 
  latch91 : latch
699 
    PORT MAP (
700 
    vss => vss,
701 
    vdd => vdd,
702 
    b => o6(11),
703 
    en => cke,
704 
    a => x6_11);
705 
  latch12 : latch
706 
    PORT MAP (
707 
    vss => vss,
708 
    vdd => vdd,
709 
    b => o1(12),
710 
    en => cke,
711 
    a => x1_12);
712 
  latch28 : latch
713 
    PORT MAP (
714 
    vss => vss,
715 
    vdd => vdd,
716 
    b => o2(12),
717 
    en => cke,
718 
    a => x2_12);
719 
  latch44 : latch
720 
    PORT MAP (
721 
    vss => vss,
722 
    vdd => vdd,
723 
    b => o3(12),
724 
    en => cke,
725 
    a => x3_12);
726 
  latch60 : latch
727 
    PORT MAP (
728 
    vss => vss,
729 
    vdd => vdd,
730 
    b => o4(12),
731 
    en => cke,
732 
    a => x4_12);
733 
  latch76 : latch
734 
    PORT MAP (
735 
    vss => vss,
736 
    vdd => vdd,
737 
    b => o5(12),
738 
    en => cke,
739 
    a => x5_12);
740 
  latch92 : latch
741 
    PORT MAP (
742 
    vss => vss,
743 
    vdd => vdd,
744 
    b => o6(12),
745 
    en => cke,
746 
    a => x6_12);
747 
  latch13 : latch
748 
    PORT MAP (
749 
    vss => vss,
750 
    vdd => vdd,
751 
    b => o1(13),
752 
    en => cke,
753 
    a => x1_13);
754 
  latch29 : latch
755 
    PORT MAP (
756 
    vss => vss,
757 
    vdd => vdd,
758 
    b => o2(13),
759 
    en => cke,
760 
    a => x2_13);
761 
  latch45 : latch
762 
    PORT MAP (
763 
    vss => vss,
764 
    vdd => vdd,
765 
    b => o3(13),
766 
    en => cke,
767 
    a => x3_13);
768 
  latch61 : latch
769 
    PORT MAP (
770 
    vss => vss,
771 
    vdd => vdd,
772 
    b => o4(13),
773 
    en => cke,
774 
    a => x4_13);
775 
  latch77 : latch
776 
    PORT MAP (
777 
    vss => vss,
778 
    vdd => vdd,
779 
    b => o5(13),
780 
    en => cke,
781 
    a => x5_13);
782 
  latch93 : latch
783 
    PORT MAP (
784 
    vss => vss,
785 
    vdd => vdd,
786 
    b => o6(13),
787 
    en => cke,
788 
    a => x6_13);
789 
  latch14 : latch
790 
    PORT MAP (
791 
    vss => vss,
792 
    vdd => vdd,
793 
    b => o1(14),
794 
    en => cke,
795 
    a => x1_14);
796 
  latch30 : latch
797 
    PORT MAP (
798 
    vss => vss,
799 
    vdd => vdd,
800 
    b => o2(14),
801 
    en => cke,
802 
    a => x2_14);
803 
  latch46 : latch
804 
    PORT MAP (
805 
    vss => vss,
806 
    vdd => vdd,
807 
    b => o3(14),
808 
    en => cke,
809 
    a => x3_14);
810 
  latch62 : latch
811 
    PORT MAP (
812 
    vss => vss,
813 
    vdd => vdd,
814 
    b => o4(14),
815 
    en => cke,
816 
    a => x4_14);
817 
  latch78 : latch
818 
    PORT MAP (
819 
    vss => vss,
820 
    vdd => vdd,
821 
    b => o5(14),
822 
    en => cke,
823 
    a => x5_14);
824 
  latch94 : latch
825 
    PORT MAP (
826 
    vss => vss,
827 
    vdd => vdd,
828 
    b => o6(14),
829 
    en => cke,
830 
    a => x6_14);
831 
  latch15 : latch
832 
    PORT MAP (
833 
    vss => vss,
834 
    vdd => vdd,
835 
    b => o1(15),
836 
    en => cke,
837 
    a => x1_15);
838 
  latch31 : latch
839 
    PORT MAP (
840 
    vss => vss,
841 
    vdd => vdd,
842 
    b => o2(15),
843 
    en => cke,
844 
    a => x2_15);
845 
  latch47 : latch
846 
    PORT MAP (
847 
    vss => vss,
848 
    vdd => vdd,
849 
    b => o3(15),
850 
    en => cke,
851 
    a => x3_15);
852 
  latch63 : latch
853 
    PORT MAP (
854 
    vss => vss,
855 
    vdd => vdd,
856 
    b => o4(15),
857 
    en => cke,
858 
    a => x4_15);
859 
  latch79 : latch
860 
    PORT MAP (
861 
    vss => vss,
862 
    vdd => vdd,
863 
    b => o5(15),
864 
    en => cke,
865 
    a => x5_15);
866 
  latch95 : latch
867 
    PORT MAP (
868 
    vss => vss,
869 
    vdd => vdd,
870 
    b => o6(15),
871 
    en => cke,
872 
    a => x6_15);
873 
 
874 
end VST;

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