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[/] [structural_vhdl/] [trunk/] [key_regulator/] [mux288to16_latch.vst] - Blame information for rev 4

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1 2 marta 
-- VHDL structural description generated from `mux288to16_latch`
2 
--              date : Sat Jul 28 10:14:55 2001
3 
 
4 
 
5 
-- Entity Declaration
6 
 
7 
ENTITY mux288to16_latch IS
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  PORT (
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  i1 : in BIT_VECTOR (15 DOWNTO 0);     -- i1
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  i2 : in BIT_VECTOR (15 DOWNTO 0);     -- i2
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  i3 : in BIT_VECTOR (15 DOWNTO 0);     -- i3
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  i4 : in BIT_VECTOR (15 DOWNTO 0);     -- i4
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  i5 : in BIT_VECTOR (15 DOWNTO 0);     -- i5
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  i6 : in BIT_VECTOR (15 DOWNTO 0);     -- i6
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  i7 : in BIT_VECTOR (15 DOWNTO 0);     -- i7
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  i8 : in BIT_VECTOR (15 DOWNTO 0);     -- i8
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  i9 : in BIT_VECTOR (15 DOWNTO 0);     -- i9
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  i10 : in BIT_VECTOR (15 DOWNTO 0);    -- i10
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  i11 : in BIT_VECTOR (15 DOWNTO 0);    -- i11
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  i12 : in BIT_VECTOR (15 DOWNTO 0);    -- i12
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  i13 : in BIT_VECTOR (15 DOWNTO 0);    -- i13
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  i14 : in BIT_VECTOR (15 DOWNTO 0);    -- i14
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  i15 : in BIT_VECTOR (15 DOWNTO 0);    -- i15
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  i16 : in BIT_VECTOR (15 DOWNTO 0);    -- i16
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  i17 : in BIT_VECTOR (15 DOWNTO 0);    -- i17
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  i18 : in BIT_VECTOR (15 DOWNTO 0);    -- i18
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  en : in BIT;  -- en
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  clr : in BIT; -- clr
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  sel : in BIT_VECTOR (4 DOWNTO 0);     -- sel
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  cke : in BIT; -- cke
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  c : inout BIT_VECTOR (15 DOWNTO 0);   -- c
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  vdd : in BIT; -- vdd
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  vss : in BIT  -- vss
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  );
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END mux288to16_latch;
36 
 
37 
-- Architecture Declaration
38 
 
39 
ARCHITECTURE VST OF mux288to16_latch IS
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  COMPONENT mux288to16
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    port (
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    i1 : in BIT_VECTOR(15 DOWNTO 0);    -- i1
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    i2 : in BIT_VECTOR(15 DOWNTO 0);    -- i2
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    i3 : in BIT_VECTOR(15 DOWNTO 0);    -- i3
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    i4 : in BIT_VECTOR(15 DOWNTO 0);    -- i4
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    i5 : in BIT_VECTOR(15 DOWNTO 0);    -- i5
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    i6 : in BIT_VECTOR(15 DOWNTO 0);    -- i6
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    i7 : in BIT_VECTOR(15 DOWNTO 0);    -- i7
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    i8 : in BIT_VECTOR(15 DOWNTO 0);    -- i8
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    i9 : in BIT_VECTOR(15 DOWNTO 0);    -- i9
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    i10 : in BIT_VECTOR(15 DOWNTO 0);   -- i10
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    i11 : in BIT_VECTOR(15 DOWNTO 0);   -- i11
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    i12 : in BIT_VECTOR(15 DOWNTO 0);   -- i12
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    i13 : in BIT_VECTOR(15 DOWNTO 0);   -- i13
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    i14 : in BIT_VECTOR(15 DOWNTO 0);   -- i14
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    i15 : in BIT_VECTOR(15 DOWNTO 0);   -- i15
57 
    i16 : in BIT_VECTOR(15 DOWNTO 0);   -- i16
58 
    i17 : in BIT_VECTOR(15 DOWNTO 0);   -- i17
59 
    i18 : in BIT_VECTOR(15 DOWNTO 0);   -- i18
60 
    en : in BIT;        -- en
61 
    clr : in BIT;       -- clr
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    sel : in BIT_VECTOR(4 DOWNTO 0);    -- sel
63 
    c : out BIT_VECTOR(15 DOWNTO 0);    -- c
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
66 
    );
67 
  END COMPONENT;
68 
 
69 
  COMPONENT latch
70 
    port (
71 
    a : in BIT; -- a
72 
    en : in BIT;        -- en
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    b : inout BIT;      -- b
74 
    vdd : in BIT;       -- vdd
75 
    vss : in BIT        -- vss
76 
    );
77 
  END COMPONENT;
78 
 
79 
  SIGNAL b_0 : BIT;     -- b 0
80 
  SIGNAL b_1 : BIT;     -- b 1
81 
  SIGNAL b_2 : BIT;     -- b 2
82 
  SIGNAL b_3 : BIT;     -- b 3
83 
  SIGNAL b_4 : BIT;     -- b 4
84 
  SIGNAL b_5 : BIT;     -- b 5
85 
  SIGNAL b_6 : BIT;     -- b 6
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  SIGNAL b_7 : BIT;     -- b 7
87 
  SIGNAL b_8 : BIT;     -- b 8
88 
  SIGNAL b_9 : BIT;     -- b 9
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  SIGNAL b_10 : BIT;    -- b 10
90 
  SIGNAL b_11 : BIT;    -- b 11
91 
  SIGNAL b_12 : BIT;    -- b 12
92 
  SIGNAL b_13 : BIT;    -- b 13
93 
  SIGNAL b_14 : BIT;    -- b 14
94 
  SIGNAL b_15 : BIT;    -- b 15
95 
 
96 
BEGIN
97 
 
98 
  mux1 : mux288to16
99 
    PORT MAP (
100 
    vss => vss,
101 
    vdd => vdd,
102 
    c => b_15& b_14& b_13& b_12& b_11& b_10& b_9& b_8& b_7& b_6& b_5& b_4& b_3& b_2& b_1& b_0,
103 
    sel => sel(4)& sel(3)& sel(2)& sel(1)& sel(0),
104 
    clr => clr,
105 
    en => en,
106 
    i18 => i18(15)& i18(14)& i18(13)& i18(12)& i18(11)& i18(10)& i18(9)& i18(8)& i18(7)& i18(6)& i18(5)& i18(4)& i18(3)& i18(2)& i18(1)& i18(0),
107 
    i17 => i17(15)& i17(14)& i17(13)& i17(12)& i17(11)& i17(10)& i17(9)& i17(8)& i17(7)& i17(6)& i17(5)& i17(4)& i17(3)& i17(2)& i17(1)& i17(0),
108 
    i16 => i16(15)& i16(14)& i16(13)& i16(12)& i16(11)& i16(10)& i16(9)& i16(8)& i16(7)& i16(6)& i16(5)& i16(4)& i16(3)& i16(2)& i16(1)& i16(0),
109 
    i15 => i15(15)& i15(14)& i15(13)& i15(12)& i15(11)& i15(10)& i15(9)& i15(8)& i15(7)& i15(6)& i15(5)& i15(4)& i15(3)& i15(2)& i15(1)& i15(0),
110 
    i14 => i14(15)& i14(14)& i14(13)& i14(12)& i14(11)& i14(10)& i14(9)& i14(8)& i14(7)& i14(6)& i14(5)& i14(4)& i14(3)& i14(2)& i14(1)& i14(0),
111 
    i13 => i13(15)& i13(14)& i13(13)& i13(12)& i13(11)& i13(10)& i13(9)& i13(8)& i13(7)& i13(6)& i13(5)& i13(4)& i13(3)& i13(2)& i13(1)& i13(0),
112 
    i12 => i12(15)& i12(14)& i12(13)& i12(12)& i12(11)& i12(10)& i12(9)& i12(8)& i12(7)& i12(6)& i12(5)& i12(4)& i12(3)& i12(2)& i12(1)& i12(0),
113 
    i11 => i11(15)& i11(14)& i11(13)& i11(12)& i11(11)& i11(10)& i11(9)& i11(8)& i11(7)& i11(6)& i11(5)& i11(4)& i11(3)& i11(2)& i11(1)& i11(0),
114 
    i10 => i10(15)& i10(14)& i10(13)& i10(12)& i10(11)& i10(10)& i10(9)& i10(8)& i10(7)& i10(6)& i10(5)& i10(4)& i10(3)& i10(2)& i10(1)& i10(0),
115 
    i9 => i9(15)& i9(14)& i9(13)& i9(12)& i9(11)& i9(10)& i9(9)& i9(8)& i9(7)& i9(6)& i9(5)& i9(4)& i9(3)& i9(2)& i9(1)& i9(0),
116 
    i8 => i8(15)& i8(14)& i8(13)& i8(12)& i8(11)& i8(10)& i8(9)& i8(8)& i8(7)& i8(6)& i8(5)& i8(4)& i8(3)& i8(2)& i8(1)& i8(0),
117 
    i7 => i7(15)& i7(14)& i7(13)& i7(12)& i7(11)& i7(10)& i7(9)& i7(8)& i7(7)& i7(6)& i7(5)& i7(4)& i7(3)& i7(2)& i7(1)& i7(0),
118 
    i6 => i6(15)& i6(14)& i6(13)& i6(12)& i6(11)& i6(10)& i6(9)& i6(8)& i6(7)& i6(6)& i6(5)& i6(4)& i6(3)& i6(2)& i6(1)& i6(0),
119 
    i5 => i5(15)& i5(14)& i5(13)& i5(12)& i5(11)& i5(10)& i5(9)& i5(8)& i5(7)& i5(6)& i5(5)& i5(4)& i5(3)& i5(2)& i5(1)& i5(0),
120 
    i4 => i4(15)& i4(14)& i4(13)& i4(12)& i4(11)& i4(10)& i4(9)& i4(8)& i4(7)& i4(6)& i4(5)& i4(4)& i4(3)& i4(2)& i4(1)& i4(0),
121 
    i3 => i3(15)& i3(14)& i3(13)& i3(12)& i3(11)& i3(10)& i3(9)& i3(8)& i3(7)& i3(6)& i3(5)& i3(4)& i3(3)& i3(2)& i3(1)& i3(0),
122 
    i2 => i2(15)& i2(14)& i2(13)& i2(12)& i2(11)& i2(10)& i2(9)& i2(8)& i2(7)& i2(6)& i2(5)& i2(4)& i2(3)& i2(2)& i2(1)& i2(0),
123 
    i1 => i1(15)& i1(14)& i1(13)& i1(12)& i1(11)& i1(10)& i1(9)& i1(8)& i1(7)& i1(6)& i1(5)& i1(4)& i1(3)& i1(2)& i1(1)& i1(0));
124 
  latch0 : latch
125 
    PORT MAP (
126 
    vss => vss,
127 
    vdd => vdd,
128 
    b => c(0),
129 
    en => cke,
130 
    a => b_0);
131 
  latch1 : latch
132 
    PORT MAP (
133 
    vss => vss,
134 
    vdd => vdd,
135 
    b => c(1),
136 
    en => cke,
137 
    a => b_1);
138 
  latch2 : latch
139 
    PORT MAP (
140 
    vss => vss,
141 
    vdd => vdd,
142 
    b => c(2),
143 
    en => cke,
144 
    a => b_2);
145 
  latch3 : latch
146 
    PORT MAP (
147 
    vss => vss,
148 
    vdd => vdd,
149 
    b => c(3),
150 
    en => cke,
151 
    a => b_3);
152 
  latch4 : latch
153 
    PORT MAP (
154 
    vss => vss,
155 
    vdd => vdd,
156 
    b => c(4),
157 
    en => cke,
158 
    a => b_4);
159 
  latch5 : latch
160 
    PORT MAP (
161 
    vss => vss,
162 
    vdd => vdd,
163 
    b => c(5),
164 
    en => cke,
165 
    a => b_5);
166 
  latch6 : latch
167 
    PORT MAP (
168 
    vss => vss,
169 
    vdd => vdd,
170 
    b => c(6),
171 
    en => cke,
172 
    a => b_6);
173 
  latch7 : latch
174 
    PORT MAP (
175 
    vss => vss,
176 
    vdd => vdd,
177 
    b => c(7),
178 
    en => cke,
179 
    a => b_7);
180 
  latch8 : latch
181 
    PORT MAP (
182 
    vss => vss,
183 
    vdd => vdd,
184 
    b => c(8),
185 
    en => cke,
186 
    a => b_8);
187 
  latch9 : latch
188 
    PORT MAP (
189 
    vss => vss,
190 
    vdd => vdd,
191 
    b => c(9),
192 
    en => cke,
193 
    a => b_9);
194 
  latch10 : latch
195 
    PORT MAP (
196 
    vss => vss,
197 
    vdd => vdd,
198 
    b => c(10),
199 
    en => cke,
200 
    a => b_10);
201 
  latch11 : latch
202 
    PORT MAP (
203 
    vss => vss,
204 
    vdd => vdd,
205 
    b => c(11),
206 
    en => cke,
207 
    a => b_11);
208 
  latch12 : latch
209 
    PORT MAP (
210 
    vss => vss,
211 
    vdd => vdd,
212 
    b => c(12),
213 
    en => cke,
214 
    a => b_12);
215 
  latch13 : latch
216 
    PORT MAP (
217 
    vss => vss,
218 
    vdd => vdd,
219 
    b => c(13),
220 
    en => cke,
221 
    a => b_13);
222 
  latch14 : latch
223 
    PORT MAP (
224 
    vss => vss,
225 
    vdd => vdd,
226 
    b => c(14),
227 
    en => cke,
228 
    a => b_14);
229 
  latch15 : latch
230 
    PORT MAP (
231 
    vss => vss,
232 
    vdd => vdd,
233 
    b => c(15),
234 
    en => cke,
235 
    a => b_15);
236 
 
237 
end VST;

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