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[/] [structural_vhdl/] [trunk/] [key_regulator/] [mux8to4_latch.vst] - Blame information for rev 2

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1 2 marta 
-- VHDL structural description generated from `mux8to4_latch`
2 
--              date : Sat Jul 28 16:33:13 2001
3 
 
4 
 
5 
-- Entity Declaration
6 
 
7 
ENTITY mux8to4_latch IS
8 
  PORT (
9 
  i1 : in BIT_VECTOR (15 DOWNTO 0);     -- i1
10 
  i2 : in BIT_VECTOR (15 DOWNTO 0);     -- i2
11 
  i3 : in BIT_VECTOR (15 DOWNTO 0);     -- i3
12 
  i4 : in BIT_VECTOR (15 DOWNTO 0);     -- i4
13 
  i5 : in BIT_VECTOR (15 DOWNTO 0);     -- i5
14 
  i6 : in BIT_VECTOR (15 DOWNTO 0);     -- i6
15 
  i7 : in BIT_VECTOR (15 DOWNTO 0);     -- i7
16 
  i8 : in BIT_VECTOR (15 DOWNTO 0);     -- i8
17 
  en : in BIT;  -- en
18 
  clr : in BIT; -- clr
19 
  sel : in BIT; -- sel
20 
  cke : in BIT; -- cke
21 
  o1 : inout BIT_VECTOR (15 DOWNTO 0);  -- o1
22 
  o2 : inout BIT_VECTOR (15 DOWNTO 0);  -- o2
23 
  o3 : inout BIT_VECTOR (15 DOWNTO 0);  -- o3
24 
  o4 : inout BIT_VECTOR (15 DOWNTO 0);  -- o4
25 
  vdd : in BIT; -- vdd
26 
  vss : in BIT  -- vss
27 
  );
28 
END mux8to4_latch;
29 
 
30 
-- Architecture Declaration
31 
 
32 
ARCHITECTURE VST OF mux8to4_latch IS
33 
  COMPONENT mux8to4
34 
    port (
35 
    i1 : in BIT_VECTOR(15 DOWNTO 0);    -- i1
36 
    i2 : in BIT_VECTOR(15 DOWNTO 0);    -- i2
37 
    i3 : in BIT_VECTOR(15 DOWNTO 0);    -- i3
38 
    i4 : in BIT_VECTOR(15 DOWNTO 0);    -- i4
39 
    i5 : in BIT_VECTOR(15 DOWNTO 0);    -- i5
40 
    i6 : in BIT_VECTOR(15 DOWNTO 0);    -- i6
41 
    i7 : in BIT_VECTOR(15 DOWNTO 0);    -- i7
42 
    i8 : in BIT_VECTOR(15 DOWNTO 0);    -- i8
43 
    en : in BIT;        -- en
44 
    clr : in BIT;       -- clr
45 
    sel : in BIT;       -- sel
46 
    o1 : out BIT_VECTOR(15 DOWNTO 0);   -- o1
47 
    o2 : out BIT_VECTOR(15 DOWNTO 0);   -- o2
48 
    o3 : out BIT_VECTOR(15 DOWNTO 0);   -- o3
49 
    o4 : out BIT_VECTOR(15 DOWNTO 0);   -- o4
50 
    vdd : in BIT;       -- vdd
51 
    vss : in BIT        -- vss
52 
    );
53 
  END COMPONENT;
54 
 
55 
  COMPONENT latch
56 
    port (
57 
    a : in BIT; -- a
58 
    en : in BIT;        -- en
59 
    b : inout BIT;      -- b
60 
    vdd : in BIT;       -- vdd
61 
    vss : in BIT        -- vss
62 
    );
63 
  END COMPONENT;
64 
 
65 
  SIGNAL x1_0 : BIT;    -- x1 0
66 
  SIGNAL x1_1 : BIT;    -- x1 1
67 
  SIGNAL x1_2 : BIT;    -- x1 2
68 
  SIGNAL x1_3 : BIT;    -- x1 3
69 
  SIGNAL x1_4 : BIT;    -- x1 4
70 
  SIGNAL x1_5 : BIT;    -- x1 5
71 
  SIGNAL x1_6 : BIT;    -- x1 6
72 
  SIGNAL x1_7 : BIT;    -- x1 7
73 
  SIGNAL x1_8 : BIT;    -- x1 8
74 
  SIGNAL x1_9 : BIT;    -- x1 9
75 
  SIGNAL x1_10 : BIT;   -- x1 10
76 
  SIGNAL x1_11 : BIT;   -- x1 11
77 
  SIGNAL x1_12 : BIT;   -- x1 12
78 
  SIGNAL x1_13 : BIT;   -- x1 13
79 
  SIGNAL x1_14 : BIT;   -- x1 14
80 
  SIGNAL x1_15 : BIT;   -- x1 15
81 
  SIGNAL x2_0 : BIT;    -- x2 0
82 
  SIGNAL x2_1 : BIT;    -- x2 1
83 
  SIGNAL x2_2 : BIT;    -- x2 2
84 
  SIGNAL x2_3 : BIT;    -- x2 3
85 
  SIGNAL x2_4 : BIT;    -- x2 4
86 
  SIGNAL x2_5 : BIT;    -- x2 5
87 
  SIGNAL x2_6 : BIT;    -- x2 6
88 
  SIGNAL x2_7 : BIT;    -- x2 7
89 
  SIGNAL x2_8 : BIT;    -- x2 8
90 
  SIGNAL x2_9 : BIT;    -- x2 9
91 
  SIGNAL x2_10 : BIT;   -- x2 10
92 
  SIGNAL x2_11 : BIT;   -- x2 11
93 
  SIGNAL x2_12 : BIT;   -- x2 12
94 
  SIGNAL x2_13 : BIT;   -- x2 13
95 
  SIGNAL x2_14 : BIT;   -- x2 14
96 
  SIGNAL x2_15 : BIT;   -- x2 15
97 
  SIGNAL x3_0 : BIT;    -- x3 0
98 
  SIGNAL x3_1 : BIT;    -- x3 1
99 
  SIGNAL x3_2 : BIT;    -- x3 2
100 
  SIGNAL x3_3 : BIT;    -- x3 3
101 
  SIGNAL x3_4 : BIT;    -- x3 4
102 
  SIGNAL x3_5 : BIT;    -- x3 5
103 
  SIGNAL x3_6 : BIT;    -- x3 6
104 
  SIGNAL x3_7 : BIT;    -- x3 7
105 
  SIGNAL x3_8 : BIT;    -- x3 8
106 
  SIGNAL x3_9 : BIT;    -- x3 9
107 
  SIGNAL x3_10 : BIT;   -- x3 10
108 
  SIGNAL x3_11 : BIT;   -- x3 11
109 
  SIGNAL x3_12 : BIT;   -- x3 12
110 
  SIGNAL x3_13 : BIT;   -- x3 13
111 
  SIGNAL x3_14 : BIT;   -- x3 14
112 
  SIGNAL x3_15 : BIT;   -- x3 15
113 
  SIGNAL x4_0 : BIT;    -- x4 0
114 
  SIGNAL x4_1 : BIT;    -- x4 1
115 
  SIGNAL x4_2 : BIT;    -- x4 2
116 
  SIGNAL x4_3 : BIT;    -- x4 3
117 
  SIGNAL x4_4 : BIT;    -- x4 4
118 
  SIGNAL x4_5 : BIT;    -- x4 5
119 
  SIGNAL x4_6 : BIT;    -- x4 6
120 
  SIGNAL x4_7 : BIT;    -- x4 7
121 
  SIGNAL x4_8 : BIT;    -- x4 8
122 
  SIGNAL x4_9 : BIT;    -- x4 9
123 
  SIGNAL x4_10 : BIT;   -- x4 10
124 
  SIGNAL x4_11 : BIT;   -- x4 11
125 
  SIGNAL x4_12 : BIT;   -- x4 12
126 
  SIGNAL x4_13 : BIT;   -- x4 13
127 
  SIGNAL x4_14 : BIT;   -- x4 14
128 
  SIGNAL x4_15 : BIT;   -- x4 15
129 
 
130 
BEGIN
131 
 
132 
  mux1 : mux8to4
133 
    PORT MAP (
134 
    vss => vss,
135 
    vdd => vdd,
136 
    o4 => x4_15& x4_14& x4_13& x4_12& x4_11& x4_10& x4_9& x4_8& x4_7& x4_6& x4_5& x4_4& x4_3& x4_2& x4_1& x4_0,
137 
    o3 => x3_15& x3_14& x3_13& x3_12& x3_11& x3_10& x3_9& x3_8& x3_7& x3_6& x3_5& x3_4& x3_3& x3_2& x3_1& x3_0,
138 
    o2 => x2_15& x2_14& x2_13& x2_12& x2_11& x2_10& x2_9& x2_8& x2_7& x2_6& x2_5& x2_4& x2_3& x2_2& x2_1& x2_0,
139 
    o1 => x1_15& x1_14& x1_13& x1_12& x1_11& x1_10& x1_9& x1_8& x1_7& x1_6& x1_5& x1_4& x1_3& x1_2& x1_1& x1_0,
140 
    sel => sel,
141 
    clr => clr,
142 
    en => en,
143 
    i8 => i8(15)& i8(14)& i8(13)& i8(12)& i8(11)& i8(10)& i8(9)& i8(8)& i8(7)& i8(6)& i8(5)& i8(4)& i8(3)& i8(2)& i8(1)& i8(0),
144 
    i7 => i7(15)& i7(14)& i7(13)& i7(12)& i7(11)& i7(10)& i7(9)& i7(8)& i7(7)& i7(6)& i7(5)& i7(4)& i7(3)& i7(2)& i7(1)& i7(0),
145 
    i6 => i6(15)& i6(14)& i6(13)& i6(12)& i6(11)& i6(10)& i6(9)& i6(8)& i6(7)& i6(6)& i6(5)& i6(4)& i6(3)& i6(2)& i6(1)& i6(0),
146 
    i5 => i5(15)& i5(14)& i5(13)& i5(12)& i5(11)& i5(10)& i5(9)& i5(8)& i5(7)& i5(6)& i5(5)& i5(4)& i5(3)& i5(2)& i5(1)& i5(0),
147 
    i4 => i4(15)& i4(14)& i4(13)& i4(12)& i4(11)& i4(10)& i4(9)& i4(8)& i4(7)& i4(6)& i4(5)& i4(4)& i4(3)& i4(2)& i4(1)& i4(0),
148 
    i3 => i3(15)& i3(14)& i3(13)& i3(12)& i3(11)& i3(10)& i3(9)& i3(8)& i3(7)& i3(6)& i3(5)& i3(4)& i3(3)& i3(2)& i3(1)& i3(0),
149 
    i2 => i2(15)& i2(14)& i2(13)& i2(12)& i2(11)& i2(10)& i2(9)& i2(8)& i2(7)& i2(6)& i2(5)& i2(4)& i2(3)& i2(2)& i2(1)& i2(0),
150 
    i1 => i1(15)& i1(14)& i1(13)& i1(12)& i1(11)& i1(10)& i1(9)& i1(8)& i1(7)& i1(6)& i1(5)& i1(4)& i1(3)& i1(2)& i1(1)& i1(0));
151 
  latch0 : latch
152 
    PORT MAP (
153 
    vss => vss,
154 
    vdd => vdd,
155 
    b => o1(0),
156 
    en => cke,
157 
    a => x1_0);
158 
  latch16 : latch
159 
    PORT MAP (
160 
    vss => vss,
161 
    vdd => vdd,
162 
    b => o2(0),
163 
    en => cke,
164 
    a => x2_0);
165 
  latch32 : latch
166 
    PORT MAP (
167 
    vss => vss,
168 
    vdd => vdd,
169 
    b => o3(0),
170 
    en => cke,
171 
    a => x3_0);
172 
  latch48 : latch
173 
    PORT MAP (
174 
    vss => vss,
175 
    vdd => vdd,
176 
    b => o4(0),
177 
    en => cke,
178 
    a => x4_0);
179 
  latch1 : latch
180 
    PORT MAP (
181 
    vss => vss,
182 
    vdd => vdd,
183 
    b => o1(1),
184 
    en => cke,
185 
    a => x1_1);
186 
  latch17 : latch
187 
    PORT MAP (
188 
    vss => vss,
189 
    vdd => vdd,
190 
    b => o2(1),
191 
    en => cke,
192 
    a => x2_1);
193 
  latch33 : latch
194 
    PORT MAP (
195 
    vss => vss,
196 
    vdd => vdd,
197 
    b => o3(1),
198 
    en => cke,
199 
    a => x3_1);
200 
  latch49 : latch
201 
    PORT MAP (
202 
    vss => vss,
203 
    vdd => vdd,
204 
    b => o4(1),
205 
    en => cke,
206 
    a => x4_1);
207 
  latch2 : latch
208 
    PORT MAP (
209 
    vss => vss,
210 
    vdd => vdd,
211 
    b => o1(2),
212 
    en => cke,
213 
    a => x1_2);
214 
  latch18 : latch
215 
    PORT MAP (
216 
    vss => vss,
217 
    vdd => vdd,
218 
    b => o2(2),
219 
    en => cke,
220 
    a => x2_2);
221 
  latch34 : latch
222 
    PORT MAP (
223 
    vss => vss,
224 
    vdd => vdd,
225 
    b => o3(2),
226 
    en => cke,
227 
    a => x3_2);
228 
  latch50 : latch
229 
    PORT MAP (
230 
    vss => vss,
231 
    vdd => vdd,
232 
    b => o4(2),
233 
    en => cke,
234 
    a => x4_2);
235 
  latch3 : latch
236 
    PORT MAP (
237 
    vss => vss,
238 
    vdd => vdd,
239 
    b => o1(3),
240 
    en => cke,
241 
    a => x1_3);
242 
  latch19 : latch
243 
    PORT MAP (
244 
    vss => vss,
245 
    vdd => vdd,
246 
    b => o2(3),
247 
    en => cke,
248 
    a => x2_3);
249 
  latch35 : latch
250 
    PORT MAP (
251 
    vss => vss,
252 
    vdd => vdd,
253 
    b => o3(3),
254 
    en => cke,
255 
    a => x3_3);
256 
  latch51 : latch
257 
    PORT MAP (
258 
    vss => vss,
259 
    vdd => vdd,
260 
    b => o4(3),
261 
    en => cke,
262 
    a => x4_3);
263 
  latch4 : latch
264 
    PORT MAP (
265 
    vss => vss,
266 
    vdd => vdd,
267 
    b => o1(4),
268 
    en => cke,
269 
    a => x1_4);
270 
  latch20 : latch
271 
    PORT MAP (
272 
    vss => vss,
273 
    vdd => vdd,
274 
    b => o2(4),
275 
    en => cke,
276 
    a => x2_4);
277 
  latch36 : latch
278 
    PORT MAP (
279 
    vss => vss,
280 
    vdd => vdd,
281 
    b => o3(4),
282 
    en => cke,
283 
    a => x3_4);
284 
  latch52 : latch
285 
    PORT MAP (
286 
    vss => vss,
287 
    vdd => vdd,
288 
    b => o4(4),
289 
    en => cke,
290 
    a => x4_4);
291 
  latch5 : latch
292 
    PORT MAP (
293 
    vss => vss,
294 
    vdd => vdd,
295 
    b => o1(5),
296 
    en => cke,
297 
    a => x1_5);
298 
  latch21 : latch
299 
    PORT MAP (
300 
    vss => vss,
301 
    vdd => vdd,
302 
    b => o2(5),
303 
    en => cke,
304 
    a => x2_5);
305 
  latch37 : latch
306 
    PORT MAP (
307 
    vss => vss,
308 
    vdd => vdd,
309 
    b => o3(5),
310 
    en => cke,
311 
    a => x3_5);
312 
  latch53 : latch
313 
    PORT MAP (
314 
    vss => vss,
315 
    vdd => vdd,
316 
    b => o4(5),
317 
    en => cke,
318 
    a => x4_5);
319 
  latch6 : latch
320 
    PORT MAP (
321 
    vss => vss,
322 
    vdd => vdd,
323 
    b => o1(6),
324 
    en => cke,
325 
    a => x1_6);
326 
  latch22 : latch
327 
    PORT MAP (
328 
    vss => vss,
329 
    vdd => vdd,
330 
    b => o2(6),
331 
    en => cke,
332 
    a => x2_6);
333 
  latch38 : latch
334 
    PORT MAP (
335 
    vss => vss,
336 
    vdd => vdd,
337 
    b => o3(6),
338 
    en => cke,
339 
    a => x3_6);
340 
  latch54 : latch
341 
    PORT MAP (
342 
    vss => vss,
343 
    vdd => vdd,
344 
    b => o4(6),
345 
    en => cke,
346 
    a => x4_6);
347 
  latch7 : latch
348 
    PORT MAP (
349 
    vss => vss,
350 
    vdd => vdd,
351 
    b => o1(7),
352 
    en => cke,
353 
    a => x1_7);
354 
  latch23 : latch
355 
    PORT MAP (
356 
    vss => vss,
357 
    vdd => vdd,
358 
    b => o2(7),
359 
    en => cke,
360 
    a => x2_7);
361 
  latch39 : latch
362 
    PORT MAP (
363 
    vss => vss,
364 
    vdd => vdd,
365 
    b => o3(7),
366 
    en => cke,
367 
    a => x3_7);
368 
  latch55 : latch
369 
    PORT MAP (
370 
    vss => vss,
371 
    vdd => vdd,
372 
    b => o4(7),
373 
    en => cke,
374 
    a => x4_7);
375 
  latch8 : latch
376 
    PORT MAP (
377 
    vss => vss,
378 
    vdd => vdd,
379 
    b => o1(8),
380 
    en => cke,
381 
    a => x1_8);
382 
  latch24 : latch
383 
    PORT MAP (
384 
    vss => vss,
385 
    vdd => vdd,
386 
    b => o2(8),
387 
    en => cke,
388 
    a => x2_8);
389 
  latch40 : latch
390 
    PORT MAP (
391 
    vss => vss,
392 
    vdd => vdd,
393 
    b => o3(8),
394 
    en => cke,
395 
    a => x3_8);
396 
  latch56 : latch
397 
    PORT MAP (
398 
    vss => vss,
399 
    vdd => vdd,
400 
    b => o4(8),
401 
    en => cke,
402 
    a => x4_8);
403 
  latch9 : latch
404 
    PORT MAP (
405 
    vss => vss,
406 
    vdd => vdd,
407 
    b => o1(9),
408 
    en => cke,
409 
    a => x1_9);
410 
  latch25 : latch
411 
    PORT MAP (
412 
    vss => vss,
413 
    vdd => vdd,
414 
    b => o2(9),
415 
    en => cke,
416 
    a => x2_9);
417 
  latch41 : latch
418 
    PORT MAP (
419 
    vss => vss,
420 
    vdd => vdd,
421 
    b => o3(9),
422 
    en => cke,
423 
    a => x3_9);
424 
  latch57 : latch
425 
    PORT MAP (
426 
    vss => vss,
427 
    vdd => vdd,
428 
    b => o4(9),
429 
    en => cke,
430 
    a => x4_9);
431 
  latch10 : latch
432 
    PORT MAP (
433 
    vss => vss,
434 
    vdd => vdd,
435 
    b => o1(10),
436 
    en => cke,
437 
    a => x1_10);
438 
  latch26 : latch
439 
    PORT MAP (
440 
    vss => vss,
441 
    vdd => vdd,
442 
    b => o2(10),
443 
    en => cke,
444 
    a => x2_10);
445 
  latch42 : latch
446 
    PORT MAP (
447 
    vss => vss,
448 
    vdd => vdd,
449 
    b => o3(10),
450 
    en => cke,
451 
    a => x3_10);
452 
  latch58 : latch
453 
    PORT MAP (
454 
    vss => vss,
455 
    vdd => vdd,
456 
    b => o4(10),
457 
    en => cke,
458 
    a => x4_10);
459 
  latch11 : latch
460 
    PORT MAP (
461 
    vss => vss,
462 
    vdd => vdd,
463 
    b => o1(11),
464 
    en => cke,
465 
    a => x1_11);
466 
  latch27 : latch
467 
    PORT MAP (
468 
    vss => vss,
469 
    vdd => vdd,
470 
    b => o2(11),
471 
    en => cke,
472 
    a => x2_11);
473 
  latch43 : latch
474 
    PORT MAP (
475 
    vss => vss,
476 
    vdd => vdd,
477 
    b => o3(11),
478 
    en => cke,
479 
    a => x3_11);
480 
  latch59 : latch
481 
    PORT MAP (
482 
    vss => vss,
483 
    vdd => vdd,
484 
    b => o4(11),
485 
    en => cke,
486 
    a => x4_11);
487 
  latch12 : latch
488 
    PORT MAP (
489 
    vss => vss,
490 
    vdd => vdd,
491 
    b => o1(12),
492 
    en => cke,
493 
    a => x1_12);
494 
  latch28 : latch
495 
    PORT MAP (
496 
    vss => vss,
497 
    vdd => vdd,
498 
    b => o2(12),
499 
    en => cke,
500 
    a => x2_12);
501 
  latch44 : latch
502 
    PORT MAP (
503 
    vss => vss,
504 
    vdd => vdd,
505 
    b => o3(12),
506 
    en => cke,
507 
    a => x3_12);
508 
  latch60 : latch
509 
    PORT MAP (
510 
    vss => vss,
511 
    vdd => vdd,
512 
    b => o4(12),
513 
    en => cke,
514 
    a => x4_12);
515 
  latch13 : latch
516 
    PORT MAP (
517 
    vss => vss,
518 
    vdd => vdd,
519 
    b => o1(13),
520 
    en => cke,
521 
    a => x1_13);
522 
  latch29 : latch
523 
    PORT MAP (
524 
    vss => vss,
525 
    vdd => vdd,
526 
    b => o2(13),
527 
    en => cke,
528 
    a => x2_13);
529 
  latch45 : latch
530 
    PORT MAP (
531 
    vss => vss,
532 
    vdd => vdd,
533 
    b => o3(13),
534 
    en => cke,
535 
    a => x3_13);
536 
  latch61 : latch
537 
    PORT MAP (
538 
    vss => vss,
539 
    vdd => vdd,
540 
    b => o4(13),
541 
    en => cke,
542 
    a => x4_13);
543 
  latch14 : latch
544 
    PORT MAP (
545 
    vss => vss,
546 
    vdd => vdd,
547 
    b => o1(14),
548 
    en => cke,
549 
    a => x1_14);
550 
  latch30 : latch
551 
    PORT MAP (
552 
    vss => vss,
553 
    vdd => vdd,
554 
    b => o2(14),
555 
    en => cke,
556 
    a => x2_14);
557 
  latch46 : latch
558 
    PORT MAP (
559 
    vss => vss,
560 
    vdd => vdd,
561 
    b => o3(14),
562 
    en => cke,
563 
    a => x3_14);
564 
  latch62 : latch
565 
    PORT MAP (
566 
    vss => vss,
567 
    vdd => vdd,
568 
    b => o4(14),
569 
    en => cke,
570 
    a => x4_14);
571 
  latch15 : latch
572 
    PORT MAP (
573 
    vss => vss,
574 
    vdd => vdd,
575 
    b => o1(15),
576 
    en => cke,
577 
    a => x1_15);
578 
  latch31 : latch
579 
    PORT MAP (
580 
    vss => vss,
581 
    vdd => vdd,
582 
    b => o2(15),
583 
    en => cke,
584 
    a => x2_15);
585 
  latch47 : latch
586 
    PORT MAP (
587 
    vss => vss,
588 
    vdd => vdd,
589 
    b => o3(15),
590 
    en => cke,
591 
    a => x3_15);
592 
  latch63 : latch
593 
    PORT MAP (
594 
    vss => vss,
595 
    vdd => vdd,
596 
    b => o4(15),
597 
    en => cke,
598 
    a => x4_15);
599 
 
600 
end VST;

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