URL https://opencores.org/ocsvn/structural_vhdl/structural_vhdl/trunk

Subversion Repositories structural_vhdl

[/] [structural_vhdl/] [trunk/] [key_regulator/] [reg16_latch.vst] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log


-- VHDL structural description generated from `reg16_latch`
--              date : Tue Jul 31 11:00:53 2001
 
 
-- Entity Declaration
 
ENTITY reg16_latch IS
  PORT (
  a : in BIT_VECTOR (15 DOWNTO 0);      -- a
  en : in BIT;  -- en
  clr : in BIT; -- clr
  cke : in BIT; -- cke
  b : inout BIT_VECTOR (15 DOWNTO 0);   -- b
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END reg16_latch;
 
-- Architecture Declaration
 
ARCHITECTURE VST OF reg16_latch IS
  COMPONENT reg16
    port (
    a : in BIT_VECTOR(15 DOWNTO 0);     -- a
    en : in BIT;        -- en
    clr : in BIT;       -- clr
    b : out BIT_VECTOR(15 DOWNTO 0);    -- b
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT latch
    port (
    a : in BIT; -- a
    en : in BIT;        -- en
    b : inout BIT;      -- b
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  SIGNAL x_0 : BIT;     -- x 0
  SIGNAL x_1 : BIT;     -- x 1
  SIGNAL x_2 : BIT;     -- x 2
  SIGNAL x_3 : BIT;     -- x 3
  SIGNAL x_4 : BIT;     -- x 4
  SIGNAL x_5 : BIT;     -- x 5
  SIGNAL x_6 : BIT;     -- x 6
  SIGNAL x_7 : BIT;     -- x 7
  SIGNAL x_8 : BIT;     -- x 8
  SIGNAL x_9 : BIT;     -- x 9
  SIGNAL x_10 : BIT;    -- x 10
  SIGNAL x_11 : BIT;    -- x 11
  SIGNAL x_12 : BIT;    -- x 12
  SIGNAL x_13 : BIT;    -- x 13
  SIGNAL x_14 : BIT;    -- x 14
  SIGNAL x_15 : BIT;    -- x 15
 
BEGIN
 
  reg1 : reg16
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => x_15& x_14& x_13& x_12& x_11& x_10& x_9& x_8& x_7& x_6& x_5& x_4& x_3& x_2& x_1& x_0,
    clr => clr,
    en => en,
    a => a(15)& a(14)& a(13)& a(12)& a(11)& a(10)& a(9)& a(8)& a(7)& a(6)& a(5)& a(4)& a(3)& a(2)& a(1)& a(0));
  latch0 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(0),
    en => cke,
    a => x_0);
  latch1 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(1),
    en => cke,
    a => x_1);
  latch2 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(2),
    en => cke,
    a => x_2);
  latch3 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(3),
    en => cke,
    a => x_3);
  latch4 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(4),
    en => cke,
    a => x_4);
  latch5 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(5),
    en => cke,
    a => x_5);
  latch6 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(6),
    en => cke,
    a => x_6);
  latch7 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(7),
    en => cke,
    a => x_7);
  latch8 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(8),
    en => cke,
    a => x_8);
  latch9 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(9),
    en => cke,
    a => x_9);
  latch10 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(10),
    en => cke,
    a => x_10);
  latch11 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(11),
    en => cke,
    a => x_11);
  latch12 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(12),
    en => cke,
    a => x_12);
  latch13 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(13),
    en => cke,
    a => x_13);
  latch14 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(14),
    en => cke,
    a => x_14);
  latch15 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(15),
    en => cke,
    a => x_15);
 
end VST;

Line No.	Rev	Author	Line
1	2	marta	-- VHDL structural description generated from `reg16_latch`
2			`-- date : Tue Jul 31 11:00:53 2001`
3
4
5			`-- Entity Declaration`
6
7			`ENTITY reg16_latch IS`
8			`PORT (`
9			`a : in BIT_VECTOR (15 DOWNTO 0); -- a`
10			`en : in BIT; -- en`
11			`clr : in BIT; -- clr`
12			`cke : in BIT; -- cke`
13			`b : inout BIT_VECTOR (15 DOWNTO 0); -- b`
14			`vdd : in BIT; -- vdd`
15			`vss : in BIT -- vss`
16			`);`
17			`END reg16_latch;`
18
19			`-- Architecture Declaration`
20
21			`ARCHITECTURE VST OF reg16_latch IS`
22			`COMPONENT reg16`
23			`port (`
24			`a : in BIT_VECTOR(15 DOWNTO 0); -- a`
25			`en : in BIT; -- en`
26			`clr : in BIT; -- clr`
27			`b : out BIT_VECTOR(15 DOWNTO 0); -- b`
28			`vdd : in BIT; -- vdd`
29			`vss : in BIT -- vss`
30			`);`
31			`END COMPONENT;`
32
33			`COMPONENT latch`
34			`port (`
35			`a : in BIT; -- a`
36			`en : in BIT; -- en`
37			`b : inout BIT; -- b`
38			`vdd : in BIT; -- vdd`
39			`vss : in BIT -- vss`
40			`);`
41			`END COMPONENT;`
42
43			`SIGNAL x_0 : BIT; -- x 0`
44			`SIGNAL x_1 : BIT; -- x 1`
45			`SIGNAL x_2 : BIT; -- x 2`
46			`SIGNAL x_3 : BIT; -- x 3`
47			`SIGNAL x_4 : BIT; -- x 4`
48			`SIGNAL x_5 : BIT; -- x 5`
49			`SIGNAL x_6 : BIT; -- x 6`
50			`SIGNAL x_7 : BIT; -- x 7`
51			`SIGNAL x_8 : BIT; -- x 8`
52			`SIGNAL x_9 : BIT; -- x 9`
53			`SIGNAL x_10 : BIT; -- x 10`
54			`SIGNAL x_11 : BIT; -- x 11`
55			`SIGNAL x_12 : BIT; -- x 12`
56			`SIGNAL x_13 : BIT; -- x 13`
57			`SIGNAL x_14 : BIT; -- x 14`
58			`SIGNAL x_15 : BIT; -- x 15`
59
60			`BEGIN`
61
62			`reg1 : reg16`
63			`PORT MAP (`
64			`vss => vss,`
65			`vdd => vdd,`
66			`b => x_15& x_14& x_13& x_12& x_11& x_10& x_9& x_8& x_7& x_6& x_5& x_4& x_3& x_2& x_1& x_0,`
67			`clr => clr,`
68			`en => en,`
69			`a => a(15)& a(14)& a(13)& a(12)& a(11)& a(10)& a(9)& a(8)& a(7)& a(6)& a(5)& a(4)& a(3)& a(2)& a(1)& a(0));`
70			`latch0 : latch`
71			`PORT MAP (`
72			`vss => vss,`
73			`vdd => vdd,`
74			`b => b(0),`
75			`en => cke,`
76			`a => x_0);`
77			`latch1 : latch`
78			`PORT MAP (`
79			`vss => vss,`
80			`vdd => vdd,`
81			`b => b(1),`
82			`en => cke,`
83			`a => x_1);`
84			`latch2 : latch`
85			`PORT MAP (`
86			`vss => vss,`
87			`vdd => vdd,`
88			`b => b(2),`
89			`en => cke,`
90			`a => x_2);`
91			`latch3 : latch`
92			`PORT MAP (`
93			`vss => vss,`
94			`vdd => vdd,`
95			`b => b(3),`
96			`en => cke,`
97			`a => x_3);`
98			`latch4 : latch`
99			`PORT MAP (`
100			`vss => vss,`
101			`vdd => vdd,`
102			`b => b(4),`
103			`en => cke,`
104			`a => x_4);`
105			`latch5 : latch`
106			`PORT MAP (`
107			`vss => vss,`
108			`vdd => vdd,`
109			`b => b(5),`
110			`en => cke,`
111			`a => x_5);`
112			`latch6 : latch`
113			`PORT MAP (`
114			`vss => vss,`
115			`vdd => vdd,`
116			`b => b(6),`
117			`en => cke,`
118			`a => x_6);`
119			`latch7 : latch`
120			`PORT MAP (`
121			`vss => vss,`
122			`vdd => vdd,`
123			`b => b(7),`
124			`en => cke,`
125			`a => x_7);`
126			`latch8 : latch`
127			`PORT MAP (`
128			`vss => vss,`
129			`vdd => vdd,`
130			`b => b(8),`
131			`en => cke,`
132			`a => x_8);`
133			`latch9 : latch`
134			`PORT MAP (`
135			`vss => vss,`
136			`vdd => vdd,`
137			`b => b(9),`
138			`en => cke,`
139			`a => x_9);`
140			`latch10 : latch`
141			`PORT MAP (`
142			`vss => vss,`
143			`vdd => vdd,`
144			`b => b(10),`
145			`en => cke,`
146			`a => x_10);`
147			`latch11 : latch`
148			`PORT MAP (`
149			`vss => vss,`
150			`vdd => vdd,`
151			`b => b(11),`
152			`en => cke,`
153			`a => x_11);`
154			`latch12 : latch`
155			`PORT MAP (`
156			`vss => vss,`
157			`vdd => vdd,`
158			`b => b(12),`
159			`en => cke,`
160			`a => x_12);`
161			`latch13 : latch`
162			`PORT MAP (`
163			`vss => vss,`
164			`vdd => vdd,`
165			`b => b(13),`
166			`en => cke,`
167			`a => x_13);`
168			`latch14 : latch`
169			`PORT MAP (`
170			`vss => vss,`
171			`vdd => vdd,`
172			`b => b(14),`
173			`en => cke,`
174			`a => x_14);`
175			`latch15 : latch`
176			`PORT MAP (`
177			`vss => vss,`
178			`vdd => vdd,`
179			`b => b(15),`
180			`en => cke,`
181			`a => x_15);`
182
183			`end VST;`

Browse

Tools

Subversion Repositories structural_vhdl

[/] [structural_vhdl/] [trunk/] [key_regulator/] [reg16_latch.vst] - Blame information for rev 2