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[/] [structural_vhdl/] [trunk/] [key_regulator/] [substract.vst] - Blame information for rev 4

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1 2 marta 
-- VHDL structural description generated from `substract`
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--              date : Mon Jul 30 16:47:44 2001
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-- Entity Declaration
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ENTITY substract IS
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  PORT (
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  a : in BIT;   -- a
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  b : in BIT;   -- b
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  bin : in BIT; -- bin
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  diff : out BIT;       -- diff
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  bout : out BIT;       -- bout
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  vdd : in BIT; -- vdd
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  vss : in BIT  -- vss
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  );
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END substract;
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-- Architecture Declaration
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ARCHITECTURE VST OF substract IS
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  COMPONENT nao2o22_x1
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    port (
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    i0 : in BIT;        -- i0
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    i1 : in BIT;        -- i1
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    i2 : in BIT;        -- i2
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    i3 : in BIT;        -- i3
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    nq : out BIT;       -- nq
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  COMPONENT xr2_x1
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    port (
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    i0 : in BIT;        -- i0
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    i1 : in BIT;        -- i1
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    q : out BIT;        -- q
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  COMPONENT an12_x1
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    port (
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    i0 : in BIT;        -- i0
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    i1 : in BIT;        -- i1
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    q : out BIT;        -- q
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  COMPONENT inv_x1
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    port (
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    i : in BIT; -- i
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    nq : out BIT;       -- nq
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  SIGNAL auxsc7 : BIT;  -- auxsc7
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  SIGNAL auxsc8 : BIT;  -- auxsc8
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  SIGNAL auxsc9 : BIT;  -- auxsc9
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  SIGNAL auxsc1 : BIT;  -- auxsc1
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BEGIN
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  bout : nao2o22_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => bout,
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    i3 => auxsc9,
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    i2 => a,
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    i1 => auxsc8,
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    i0 => auxsc7);
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  diff : xr2_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => diff,
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    i1 => auxsc1,
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    i0 => bin);
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  auxsc1 : xr2_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => auxsc1,
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    i1 => a,
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    i0 => b);
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  auxsc9 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc9,
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    i => b);
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  auxsc8 : an12_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => auxsc8,
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    i1 => a,
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    i0 => b);
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  auxsc7 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc7,
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    i => bin);
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end VST;

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