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[/] [structural_vhdl/] [trunk/] [key_regulator/] [zero34.vst] - Blame information for rev 4

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-- VHDL structural description generated from `zero34`
--              date : Tue Jul 31 10:40:28 2001
 
 
-- Entity Declaration
 
ENTITY zero34 IS
  PORT (
  nq : out BIT_VECTOR (33 DOWNTO 0);    -- nq
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END zero34;
 
-- Architecture Declaration
 
ARCHITECTURE VST OF zero34 IS
  COMPONENT zero_x0
    port (
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
 
BEGIN
 
  nq_0 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => nq(0));
  nq_1 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => nq(1));
  nq_2 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => nq(2));
  nq_3 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => nq(3));
  nq_4 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => nq(4));
  nq_5 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => nq(5));
  nq_6 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => nq(6));
  nq_7 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => nq(7));
  nq_8 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => nq(8));
  nq_9 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => nq(9));
  nq_10 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => nq(10));
  nq_11 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => nq(11));
  nq_12 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => nq(12));
  nq_13 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => nq(13));
  nq_14 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => nq(14));
  nq_15 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => nq(15));
  nq_16 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => nq(16));
  nq_17 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => nq(17));
  nq_18 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => nq(18));
  nq_19 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => nq(19));
  nq_20 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => nq(20));
  nq_21 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => nq(21));
  nq_22 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => nq(22));
  nq_23 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => nq(23));
  nq_24 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => nq(24));
  nq_25 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => nq(25));
  nq_26 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => nq(26));
  nq_27 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => nq(27));
  nq_28 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => nq(28));
  nq_29 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => nq(29));
  nq_30 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => nq(30));
  nq_31 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => nq(31));
  nq_32 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => nq(32));
  nq_33 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => nq(33));
 
end VST;

Line No.	Rev	Author	Line
1	2	marta	-- VHDL structural description generated from `zero34`
2			`-- date : Tue Jul 31 10:40:28 2001`
3
4
5			`-- Entity Declaration`
6
7			`ENTITY zero34 IS`
8			`PORT (`
9			`nq : out BIT_VECTOR (33 DOWNTO 0); -- nq`
10			`vdd : in BIT; -- vdd`
11			`vss : in BIT -- vss`
12			`);`
13			`END zero34;`
14
15			`-- Architecture Declaration`
16
17			`ARCHITECTURE VST OF zero34 IS`
18			`COMPONENT zero_x0`
19			`port (`
20			`nq : out BIT; -- nq`
21			`vdd : in BIT; -- vdd`
22			`vss : in BIT -- vss`
23			`);`
24			`END COMPONENT;`
25
26
27			`BEGIN`
28
29			`nq_0 : zero_x0`
30			`PORT MAP (`
31			`vss => vss,`
32			`vdd => vdd,`
33			`nq => nq(0));`
34			`nq_1 : zero_x0`
35			`PORT MAP (`
36			`vss => vss,`
37			`vdd => vdd,`
38			`nq => nq(1));`
39			`nq_2 : zero_x0`
40			`PORT MAP (`
41			`vss => vss,`
42			`vdd => vdd,`
43			`nq => nq(2));`
44			`nq_3 : zero_x0`
45			`PORT MAP (`
46			`vss => vss,`
47			`vdd => vdd,`
48			`nq => nq(3));`
49			`nq_4 : zero_x0`
50			`PORT MAP (`
51			`vss => vss,`
52			`vdd => vdd,`
53			`nq => nq(4));`
54			`nq_5 : zero_x0`
55			`PORT MAP (`
56			`vss => vss,`
57			`vdd => vdd,`
58			`nq => nq(5));`
59			`nq_6 : zero_x0`
60			`PORT MAP (`
61			`vss => vss,`
62			`vdd => vdd,`
63			`nq => nq(6));`
64			`nq_7 : zero_x0`
65			`PORT MAP (`
66			`vss => vss,`
67			`vdd => vdd,`
68			`nq => nq(7));`
69			`nq_8 : zero_x0`
70			`PORT MAP (`
71			`vss => vss,`
72			`vdd => vdd,`
73			`nq => nq(8));`
74			`nq_9 : zero_x0`
75			`PORT MAP (`
76			`vss => vss,`
77			`vdd => vdd,`
78			`nq => nq(9));`
79			`nq_10 : zero_x0`
80			`PORT MAP (`
81			`vss => vss,`
82			`vdd => vdd,`
83			`nq => nq(10));`
84			`nq_11 : zero_x0`
85			`PORT MAP (`
86			`vss => vss,`
87			`vdd => vdd,`
88			`nq => nq(11));`
89			`nq_12 : zero_x0`
90			`PORT MAP (`
91			`vss => vss,`
92			`vdd => vdd,`
93			`nq => nq(12));`
94			`nq_13 : zero_x0`
95			`PORT MAP (`
96			`vss => vss,`
97			`vdd => vdd,`
98			`nq => nq(13));`
99			`nq_14 : zero_x0`
100			`PORT MAP (`
101			`vss => vss,`
102			`vdd => vdd,`
103			`nq => nq(14));`
104			`nq_15 : zero_x0`
105			`PORT MAP (`
106			`vss => vss,`
107			`vdd => vdd,`
108			`nq => nq(15));`
109			`nq_16 : zero_x0`
110			`PORT MAP (`
111			`vss => vss,`
112			`vdd => vdd,`
113			`nq => nq(16));`
114			`nq_17 : zero_x0`
115			`PORT MAP (`
116			`vss => vss,`
117			`vdd => vdd,`
118			`nq => nq(17));`
119			`nq_18 : zero_x0`
120			`PORT MAP (`
121			`vss => vss,`
122			`vdd => vdd,`
123			`nq => nq(18));`
124			`nq_19 : zero_x0`
125			`PORT MAP (`
126			`vss => vss,`
127			`vdd => vdd,`
128			`nq => nq(19));`
129			`nq_20 : zero_x0`
130			`PORT MAP (`
131			`vss => vss,`
132			`vdd => vdd,`
133			`nq => nq(20));`
134			`nq_21 : zero_x0`
135			`PORT MAP (`
136			`vss => vss,`
137			`vdd => vdd,`
138			`nq => nq(21));`
139			`nq_22 : zero_x0`
140			`PORT MAP (`
141			`vss => vss,`
142			`vdd => vdd,`
143			`nq => nq(22));`
144			`nq_23 : zero_x0`
145			`PORT MAP (`
146			`vss => vss,`
147			`vdd => vdd,`
148			`nq => nq(23));`
149			`nq_24 : zero_x0`
150			`PORT MAP (`
151			`vss => vss,`
152			`vdd => vdd,`
153			`nq => nq(24));`
154			`nq_25 : zero_x0`
155			`PORT MAP (`
156			`vss => vss,`
157			`vdd => vdd,`
158			`nq => nq(25));`
159			`nq_26 : zero_x0`
160			`PORT MAP (`
161			`vss => vss,`
162			`vdd => vdd,`
163			`nq => nq(26));`
164			`nq_27 : zero_x0`
165			`PORT MAP (`
166			`vss => vss,`
167			`vdd => vdd,`
168			`nq => nq(27));`
169			`nq_28 : zero_x0`
170			`PORT MAP (`
171			`vss => vss,`
172			`vdd => vdd,`
173			`nq => nq(28));`
174			`nq_29 : zero_x0`
175			`PORT MAP (`
176			`vss => vss,`
177			`vdd => vdd,`
178			`nq => nq(29));`
179			`nq_30 : zero_x0`
180			`PORT MAP (`
181			`vss => vss,`
182			`vdd => vdd,`
183			`nq => nq(30));`
184			`nq_31 : zero_x0`
185			`PORT MAP (`
186			`vss => vss,`
187			`vdd => vdd,`
188			`nq => nq(31));`
189			`nq_32 : zero_x0`
190			`PORT MAP (`
191			`vss => vss,`
192			`vdd => vdd,`
193			`nq => nq(32));`
194			`nq_33 : zero_x0`
195			`PORT MAP (`
196			`vss => vss,`
197			`vdd => vdd,`
198			`nq => nq(33));`
199
200			`end VST;`

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[/] [structural_vhdl/] [trunk/] [key_regulator/] [zero34.vst] - Blame information for rev 4