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[/] [structural_vhdl/] [trunk/] [main control/] [mux02.vst] - Blame information for rev 4

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1 2 marta 
-- VHDL structural description generated from `mux02`
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--              date : Sat Sep  1 20:26:25 2001
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-- Entity Declaration
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ENTITY mux02 IS
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  PORT (
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  a : in BIT_VECTOR (1 DOWNTO 0);       -- a
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  b : in BIT_VECTOR (1 DOWNTO 0);       -- b
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  c : in BIT_VECTOR (1 DOWNTO 0);       -- c
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  d : in BIT_VECTOR (1 DOWNTO 0);       -- d
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  sel : in BIT_VECTOR (1 DOWNTO 0);     -- sel
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  o : out BIT_VECTOR (1 DOWNTO 0);      -- o
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  vdd : in BIT; -- vdd
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  vss : in BIT  -- vss
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  );
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END mux02;
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-- Architecture Declaration
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ARCHITECTURE VST OF mux02 IS
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  COMPONENT o4_x2
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    port (
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    i0 : in BIT;        -- i0
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    i1 : in BIT;        -- i1
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    i2 : in BIT;        -- i2
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    i3 : in BIT;        -- i3
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    q : out BIT;        -- q
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  COMPONENT no2_x1
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    port (
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    i0 : in BIT;        -- i0
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    i1 : in BIT;        -- i1
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    nq : out BIT;       -- nq
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  COMPONENT o2_x2
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    port (
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    i0 : in BIT;        -- i0
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    i1 : in BIT;        -- i1
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    q : out BIT;        -- q
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  COMPONENT no3_x1
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    port (
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    i0 : in BIT;        -- i0
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    i1 : in BIT;        -- i1
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    i2 : in BIT;        -- i2
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    nq : out BIT;       -- nq
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  COMPONENT inv_x1
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    port (
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    i : in BIT; -- i
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    nq : out BIT;       -- nq
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  SIGNAL auxsc6 : BIT;  -- auxsc6
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  SIGNAL auxsc9 : BIT;  -- auxsc9
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  SIGNAL auxsc10 : BIT; -- auxsc10
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  SIGNAL auxsc4 : BIT;  -- auxsc4
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  SIGNAL auxsc11 : BIT; -- auxsc11
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  SIGNAL auxsc12 : BIT; -- auxsc12
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  SIGNAL auxsc13 : BIT; -- auxsc13
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  SIGNAL auxsc14 : BIT; -- auxsc14
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  SIGNAL auxsc15 : BIT; -- auxsc15
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  SIGNAL auxsc16 : BIT; -- auxsc16
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  SIGNAL auxsc17 : BIT; -- auxsc17
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  SIGNAL auxsc26 : BIT; -- auxsc26
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  SIGNAL auxsc27 : BIT; -- auxsc27
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  SIGNAL auxsc28 : BIT; -- auxsc28
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  SIGNAL auxsc29 : BIT; -- auxsc29
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  SIGNAL auxsc30 : BIT; -- auxsc30
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  SIGNAL auxsc31 : BIT; -- auxsc31
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  SIGNAL auxsc32 : BIT; -- auxsc32
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  SIGNAL auxsc33 : BIT; -- auxsc33
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BEGIN
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  o_0 : o4_x2
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => o(0),
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    i3 => auxsc17,
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    i2 => auxsc14,
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    i1 => auxsc12,
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    i0 => auxsc10);
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  o_1 : o4_x2
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => o(1),
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    i3 => auxsc33,
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    i2 => auxsc31,
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    i1 => auxsc29,
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    i0 => auxsc27);
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  auxsc33 : no2_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc33,
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    i1 => auxsc16,
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    i0 => auxsc32);
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  auxsc32 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc32,
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    i => a(1));
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  auxsc31 : no3_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc31,
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    i2 => auxsc30,
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    i1 => auxsc4,
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    i0 => auxsc6);
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  auxsc30 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc30,
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    i => d(1));
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  auxsc29 : no3_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc29,
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    i2 => auxsc28,
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    i1 => auxsc4,
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    i0 => sel(0));
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  auxsc28 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc28,
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    i => c(1));
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  auxsc27 : no3_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc27,
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    i2 => auxsc26,
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    i1 => auxsc6,
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    i0 => sel(1));
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  auxsc26 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc26,
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    i => b(1));
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  auxsc17 : no2_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc17,
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    i1 => auxsc16,
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    i0 => auxsc15);
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  auxsc16 : o2_x2
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => auxsc16,
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    i1 => sel(1),
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    i0 => sel(0));
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  auxsc15 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc15,
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    i => a(0));
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  auxsc14 : no3_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc14,
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    i2 => auxsc13,
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    i1 => auxsc4,
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    i0 => auxsc6);
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  auxsc13 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc13,
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    i => d(0));
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  auxsc12 : no3_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc12,
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    i2 => auxsc11,
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    i1 => auxsc4,
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    i0 => sel(0));
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  auxsc11 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc11,
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    i => c(0));
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  auxsc4 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc4,
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    i => sel(1));
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  auxsc10 : no3_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc10,
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    i2 => auxsc9,
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    i1 => auxsc6,
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    i0 => sel(1));
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  auxsc9 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc9,
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    i => b(0));
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  auxsc6 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc6,
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    i => sel(0));
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end VST;

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