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[/] [structural_vhdl/] [trunk/] [operation_mode/] [register64.vst] - Blame information for rev 4

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-- VHDL structural description generated from `register64`
--              date : Sat Sep  1 20:30:06 2001
 
 
-- Entity Declaration
 
ENTITY register64 IS
  PORT (
  a : in BIT_VECTOR (0 TO 63);  -- a
  rst : in BIT; -- rst
  en : in BIT;  -- en
  b : inout BIT_VECTOR (0 TO 63);       -- b
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END register64;
 
-- Architecture Declaration
 
ARCHITECTURE VST OF register64 IS
  COMPONENT reg01
    port (
    a : in BIT; -- a
    rst : in BIT;       -- rst
    en : in BIT;        -- en
    b : inout BIT;      -- b
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
 
BEGIN
 
  reg1 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(0),
    en => en,
    rst => rst,
    a => a(0));
  reg2 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(1),
    en => en,
    rst => rst,
    a => a(1));
  reg3 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(2),
    en => en,
    rst => rst,
    a => a(2));
  reg4 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(3),
    en => en,
    rst => rst,
    a => a(3));
  reg5 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(4),
    en => en,
    rst => rst,
    a => a(4));
  reg6 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(5),
    en => en,
    rst => rst,
    a => a(5));
  reg7 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(6),
    en => en,
    rst => rst,
    a => a(6));
  reg8 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(7),
    en => en,
    rst => rst,
    a => a(7));
  reg9 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(8),
    en => en,
    rst => rst,
    a => a(8));
  reg10 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(9),
    en => en,
    rst => rst,
    a => a(9));
  reg11 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(10),
    en => en,
    rst => rst,
    a => a(10));
  reg12 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(11),
    en => en,
    rst => rst,
    a => a(11));
  reg13 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(12),
    en => en,
    rst => rst,
    a => a(12));
  reg14 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(13),
    en => en,
    rst => rst,
    a => a(13));
  reg15 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(14),
    en => en,
    rst => rst,
    a => a(14));
  reg16 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(15),
    en => en,
    rst => rst,
    a => a(15));
  reg17 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(16),
    en => en,
    rst => rst,
    a => a(16));
  reg18 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(17),
    en => en,
    rst => rst,
    a => a(17));
  reg19 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(18),
    en => en,
    rst => rst,
    a => a(18));
  reg20 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(19),
    en => en,
    rst => rst,
    a => a(19));
  reg21 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(20),
    en => en,
    rst => rst,
    a => a(20));
  reg22 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(21),
    en => en,
    rst => rst,
    a => a(21));
  reg23 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(22),
    en => en,
    rst => rst,
    a => a(22));
  reg24 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(23),
    en => en,
    rst => rst,
    a => a(23));
  reg25 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(24),
    en => en,
    rst => rst,
    a => a(24));
  reg26 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(25),
    en => en,
    rst => rst,
    a => a(25));
  reg27 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(26),
    en => en,
    rst => rst,
    a => a(26));
  reg28 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(27),
    en => en,
    rst => rst,
    a => a(27));
  reg29 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(28),
    en => en,
    rst => rst,
    a => a(28));
  reg30 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(29),
    en => en,
    rst => rst,
    a => a(29));
  reg31 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(30),
    en => en,
    rst => rst,
    a => a(30));
  reg32 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(31),
    en => en,
    rst => rst,
    a => a(31));
  reg33 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(32),
    en => en,
    rst => rst,
    a => a(32));
  reg34 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(33),
    en => en,
    rst => rst,
    a => a(33));
  reg35 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(34),
    en => en,
    rst => rst,
    a => a(34));
  reg36 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(35),
    en => en,
    rst => rst,
    a => a(35));
  reg37 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(36),
    en => en,
    rst => rst,
    a => a(36));
  reg38 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(37),
    en => en,
    rst => rst,
    a => a(37));
  reg39 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(38),
    en => en,
    rst => rst,
    a => a(38));
  reg40 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(39),
    en => en,
    rst => rst,
    a => a(39));
  reg41 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(40),
    en => en,
    rst => rst,
    a => a(40));
  reg42 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(41),
    en => en,
    rst => rst,
    a => a(41));
  reg43 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(42),
    en => en,
    rst => rst,
    a => a(42));
  reg44 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(43),
    en => en,
    rst => rst,
    a => a(43));
  reg45 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(44),
    en => en,
    rst => rst,
    a => a(44));
  reg46 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(45),
    en => en,
    rst => rst,
    a => a(45));
  reg47 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(46),
    en => en,
    rst => rst,
    a => a(46));
  reg48 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(47),
    en => en,
    rst => rst,
    a => a(47));
  reg49 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(48),
    en => en,
    rst => rst,
    a => a(48));
  reg50 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(49),
    en => en,
    rst => rst,
    a => a(49));
  reg51 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(50),
    en => en,
    rst => rst,
    a => a(50));
  reg52 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(51),
    en => en,
    rst => rst,
    a => a(51));
  reg53 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(52),
    en => en,
    rst => rst,
    a => a(52));
  reg54 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(53),
    en => en,
    rst => rst,
    a => a(53));
  reg55 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(54),
    en => en,
    rst => rst,
    a => a(54));
  reg56 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(55),
    en => en,
    rst => rst,
    a => a(55));
  reg57 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(56),
    en => en,
    rst => rst,
    a => a(56));
  reg58 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(57),
    en => en,
    rst => rst,
    a => a(57));
  reg59 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(58),
    en => en,
    rst => rst,
    a => a(58));
  reg60 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(59),
    en => en,
    rst => rst,
    a => a(59));
  reg61 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(60),
    en => en,
    rst => rst,
    a => a(60));
  reg62 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(61),
    en => en,
    rst => rst,
    a => a(61));
  reg63 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(62),
    en => en,
    rst => rst,
    a => a(62));
  reg64 : reg01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => b(63),
    en => en,
    rst => rst,
    a => a(63));
 
end VST;

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Subversion Repositories structural_vhdl

[/] [structural_vhdl/] [trunk/] [operation_mode/] [register64.vst] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	marta	-- VHDL structural description generated from `register64`
2			`-- date : Sat Sep 1 20:30:06 2001`
3
4
5			`-- Entity Declaration`
6
7			`ENTITY register64 IS`
8			`PORT (`
9			`a : in BIT_VECTOR (0 TO 63); -- a`
10			`rst : in BIT; -- rst`
11			`en : in BIT; -- en`
12			`b : inout BIT_VECTOR (0 TO 63); -- b`
13			`vdd : in BIT; -- vdd`
14			`vss : in BIT -- vss`
15			`);`
16			`END register64;`
17
18			`-- Architecture Declaration`
19
20			`ARCHITECTURE VST OF register64 IS`
21			`COMPONENT reg01`
22			`port (`
23			`a : in BIT; -- a`
24			`rst : in BIT; -- rst`
25			`en : in BIT; -- en`
26			`b : inout BIT; -- b`
27			`vdd : in BIT; -- vdd`
28			`vss : in BIT -- vss`
29			`);`
30			`END COMPONENT;`
31
32
33			`BEGIN`
34
35			`reg1 : reg01`
36			`PORT MAP (`
37			`vss => vss,`
38			`vdd => vdd,`
39			`b => b(0),`
40			`en => en,`
41			`rst => rst,`
42			`a => a(0));`
43			`reg2 : reg01`
44			`PORT MAP (`
45			`vss => vss,`
46			`vdd => vdd,`
47			`b => b(1),`
48			`en => en,`
49			`rst => rst,`
50			`a => a(1));`
51			`reg3 : reg01`
52			`PORT MAP (`
53			`vss => vss,`
54			`vdd => vdd,`
55			`b => b(2),`
56			`en => en,`
57			`rst => rst,`
58			`a => a(2));`
59			`reg4 : reg01`
60			`PORT MAP (`
61			`vss => vss,`
62			`vdd => vdd,`
63			`b => b(3),`
64			`en => en,`
65			`rst => rst,`
66			`a => a(3));`
67			`reg5 : reg01`
68			`PORT MAP (`
69			`vss => vss,`
70			`vdd => vdd,`
71			`b => b(4),`
72			`en => en,`
73			`rst => rst,`
74			`a => a(4));`
75			`reg6 : reg01`
76			`PORT MAP (`
77			`vss => vss,`
78			`vdd => vdd,`
79			`b => b(5),`
80			`en => en,`
81			`rst => rst,`
82			`a => a(5));`
83			`reg7 : reg01`
84			`PORT MAP (`
85			`vss => vss,`
86			`vdd => vdd,`
87			`b => b(6),`
88			`en => en,`
89			`rst => rst,`
90			`a => a(6));`
91			`reg8 : reg01`
92			`PORT MAP (`
93			`vss => vss,`
94			`vdd => vdd,`
95			`b => b(7),`
96			`en => en,`
97			`rst => rst,`
98			`a => a(7));`
99			`reg9 : reg01`
100			`PORT MAP (`
101			`vss => vss,`
102			`vdd => vdd,`
103			`b => b(8),`
104			`en => en,`
105			`rst => rst,`
106			`a => a(8));`
107			`reg10 : reg01`
108			`PORT MAP (`
109			`vss => vss,`
110			`vdd => vdd,`
111			`b => b(9),`
112			`en => en,`
113			`rst => rst,`
114			`a => a(9));`
115			`reg11 : reg01`
116			`PORT MAP (`
117			`vss => vss,`
118			`vdd => vdd,`
119			`b => b(10),`
120			`en => en,`
121			`rst => rst,`
122			`a => a(10));`
123			`reg12 : reg01`
124			`PORT MAP (`
125			`vss => vss,`
126			`vdd => vdd,`
127			`b => b(11),`
128			`en => en,`
129			`rst => rst,`
130			`a => a(11));`
131			`reg13 : reg01`
132			`PORT MAP (`
133			`vss => vss,`
134			`vdd => vdd,`
135			`b => b(12),`
136			`en => en,`
137			`rst => rst,`
138			`a => a(12));`
139			`reg14 : reg01`
140			`PORT MAP (`
141			`vss => vss,`
142			`vdd => vdd,`
143			`b => b(13),`
144			`en => en,`
145			`rst => rst,`
146			`a => a(13));`
147			`reg15 : reg01`
148			`PORT MAP (`
149			`vss => vss,`
150			`vdd => vdd,`
151			`b => b(14),`
152			`en => en,`
153			`rst => rst,`
154			`a => a(14));`
155			`reg16 : reg01`
156			`PORT MAP (`
157			`vss => vss,`
158			`vdd => vdd,`
159			`b => b(15),`
160			`en => en,`
161			`rst => rst,`
162			`a => a(15));`
163			`reg17 : reg01`
164			`PORT MAP (`
165			`vss => vss,`
166			`vdd => vdd,`
167			`b => b(16),`
168			`en => en,`
169			`rst => rst,`
170			`a => a(16));`
171			`reg18 : reg01`
172			`PORT MAP (`
173			`vss => vss,`
174			`vdd => vdd,`
175			`b => b(17),`
176			`en => en,`
177			`rst => rst,`
178			`a => a(17));`
179			`reg19 : reg01`
180			`PORT MAP (`
181			`vss => vss,`
182			`vdd => vdd,`
183			`b => b(18),`
184			`en => en,`
185			`rst => rst,`
186			`a => a(18));`
187			`reg20 : reg01`
188			`PORT MAP (`
189			`vss => vss,`
190			`vdd => vdd,`
191			`b => b(19),`
192			`en => en,`
193			`rst => rst,`
194			`a => a(19));`
195			`reg21 : reg01`
196			`PORT MAP (`
197			`vss => vss,`
198			`vdd => vdd,`
199			`b => b(20),`
200			`en => en,`
201			`rst => rst,`
202			`a => a(20));`
203			`reg22 : reg01`
204			`PORT MAP (`
205			`vss => vss,`
206			`vdd => vdd,`
207			`b => b(21),`
208			`en => en,`
209			`rst => rst,`
210			`a => a(21));`
211			`reg23 : reg01`
212			`PORT MAP (`
213			`vss => vss,`
214			`vdd => vdd,`
215			`b => b(22),`
216			`en => en,`
217			`rst => rst,`
218			`a => a(22));`
219			`reg24 : reg01`
220			`PORT MAP (`
221			`vss => vss,`
222			`vdd => vdd,`
223			`b => b(23),`
224			`en => en,`
225			`rst => rst,`
226			`a => a(23));`
227			`reg25 : reg01`
228			`PORT MAP (`
229			`vss => vss,`
230			`vdd => vdd,`
231			`b => b(24),`
232			`en => en,`
233			`rst => rst,`
234			`a => a(24));`
235			`reg26 : reg01`
236			`PORT MAP (`
237			`vss => vss,`
238			`vdd => vdd,`
239			`b => b(25),`
240			`en => en,`
241			`rst => rst,`
242			`a => a(25));`
243			`reg27 : reg01`
244			`PORT MAP (`
245			`vss => vss,`
246			`vdd => vdd,`
247			`b => b(26),`
248			`en => en,`
249			`rst => rst,`
250			`a => a(26));`
251			`reg28 : reg01`
252			`PORT MAP (`
253			`vss => vss,`
254			`vdd => vdd,`
255			`b => b(27),`
256			`en => en,`
257			`rst => rst,`
258			`a => a(27));`
259			`reg29 : reg01`
260			`PORT MAP (`
261			`vss => vss,`
262			`vdd => vdd,`
263			`b => b(28),`
264			`en => en,`
265			`rst => rst,`
266			`a => a(28));`
267			`reg30 : reg01`
268			`PORT MAP (`
269			`vss => vss,`
270			`vdd => vdd,`
271			`b => b(29),`
272			`en => en,`
273			`rst => rst,`
274			`a => a(29));`
275			`reg31 : reg01`
276			`PORT MAP (`
277			`vss => vss,`
278			`vdd => vdd,`
279			`b => b(30),`
280			`en => en,`
281			`rst => rst,`
282			`a => a(30));`
283			`reg32 : reg01`
284			`PORT MAP (`
285			`vss => vss,`
286			`vdd => vdd,`
287			`b => b(31),`
288			`en => en,`
289			`rst => rst,`
290			`a => a(31));`
291			`reg33 : reg01`
292			`PORT MAP (`
293			`vss => vss,`
294			`vdd => vdd,`
295			`b => b(32),`
296			`en => en,`
297			`rst => rst,`
298			`a => a(32));`
299			`reg34 : reg01`
300			`PORT MAP (`
301			`vss => vss,`
302			`vdd => vdd,`
303			`b => b(33),`
304			`en => en,`
305			`rst => rst,`
306			`a => a(33));`
307			`reg35 : reg01`
308			`PORT MAP (`
309			`vss => vss,`
310			`vdd => vdd,`
311			`b => b(34),`
312			`en => en,`
313			`rst => rst,`
314			`a => a(34));`
315			`reg36 : reg01`
316			`PORT MAP (`
317			`vss => vss,`
318			`vdd => vdd,`
319			`b => b(35),`
320			`en => en,`
321			`rst => rst,`
322			`a => a(35));`
323			`reg37 : reg01`
324			`PORT MAP (`
325			`vss => vss,`
326			`vdd => vdd,`
327			`b => b(36),`
328			`en => en,`
329			`rst => rst,`
330			`a => a(36));`
331			`reg38 : reg01`
332			`PORT MAP (`
333			`vss => vss,`
334			`vdd => vdd,`
335			`b => b(37),`
336			`en => en,`
337			`rst => rst,`
338			`a => a(37));`
339			`reg39 : reg01`
340			`PORT MAP (`
341			`vss => vss,`
342			`vdd => vdd,`
343			`b => b(38),`
344			`en => en,`
345			`rst => rst,`
346			`a => a(38));`
347			`reg40 : reg01`
348			`PORT MAP (`
349			`vss => vss,`
350			`vdd => vdd,`
351			`b => b(39),`
352			`en => en,`
353			`rst => rst,`
354			`a => a(39));`
355			`reg41 : reg01`
356			`PORT MAP (`
357			`vss => vss,`
358			`vdd => vdd,`
359			`b => b(40),`
360			`en => en,`
361			`rst => rst,`
362			`a => a(40));`
363			`reg42 : reg01`
364			`PORT MAP (`
365			`vss => vss,`
366			`vdd => vdd,`
367			`b => b(41),`
368			`en => en,`
369			`rst => rst,`
370			`a => a(41));`
371			`reg43 : reg01`
372			`PORT MAP (`
373			`vss => vss,`
374			`vdd => vdd,`
375			`b => b(42),`
376			`en => en,`
377			`rst => rst,`
378			`a => a(42));`
379			`reg44 : reg01`
380			`PORT MAP (`
381			`vss => vss,`
382			`vdd => vdd,`
383			`b => b(43),`
384			`en => en,`
385			`rst => rst,`
386			`a => a(43));`
387			`reg45 : reg01`
388			`PORT MAP (`
389			`vss => vss,`
390			`vdd => vdd,`
391			`b => b(44),`
392			`en => en,`
393			`rst => rst,`
394			`a => a(44));`
395			`reg46 : reg01`
396			`PORT MAP (`
397			`vss => vss,`
398			`vdd => vdd,`
399			`b => b(45),`
400			`en => en,`
401			`rst => rst,`
402			`a => a(45));`
403			`reg47 : reg01`
404			`PORT MAP (`
405			`vss => vss,`
406			`vdd => vdd,`
407			`b => b(46),`
408			`en => en,`
409			`rst => rst,`
410			`a => a(46));`
411			`reg48 : reg01`
412			`PORT MAP (`
413			`vss => vss,`
414			`vdd => vdd,`
415			`b => b(47),`
416			`en => en,`
417			`rst => rst,`
418			`a => a(47));`
419			`reg49 : reg01`
420			`PORT MAP (`
421			`vss => vss,`
422			`vdd => vdd,`
423			`b => b(48),`
424			`en => en,`
425			`rst => rst,`
426			`a => a(48));`
427			`reg50 : reg01`
428			`PORT MAP (`
429			`vss => vss,`
430			`vdd => vdd,`
431			`b => b(49),`
432			`en => en,`
433			`rst => rst,`
434			`a => a(49));`
435			`reg51 : reg01`
436			`PORT MAP (`
437			`vss => vss,`
438			`vdd => vdd,`
439			`b => b(50),`
440			`en => en,`
441			`rst => rst,`
442			`a => a(50));`
443			`reg52 : reg01`
444			`PORT MAP (`
445			`vss => vss,`
446			`vdd => vdd,`
447			`b => b(51),`
448			`en => en,`
449			`rst => rst,`
450			`a => a(51));`
451			`reg53 : reg01`
452			`PORT MAP (`
453			`vss => vss,`
454			`vdd => vdd,`
455			`b => b(52),`
456			`en => en,`
457			`rst => rst,`
458			`a => a(52));`
459			`reg54 : reg01`
460			`PORT MAP (`
461			`vss => vss,`
462			`vdd => vdd,`
463			`b => b(53),`
464			`en => en,`
465			`rst => rst,`
466			`a => a(53));`
467			`reg55 : reg01`
468			`PORT MAP (`
469			`vss => vss,`
470			`vdd => vdd,`
471			`b => b(54),`
472			`en => en,`
473			`rst => rst,`
474			`a => a(54));`
475			`reg56 : reg01`
476			`PORT MAP (`
477			`vss => vss,`
478			`vdd => vdd,`
479			`b => b(55),`
480			`en => en,`
481			`rst => rst,`
482			`a => a(55));`
483			`reg57 : reg01`
484			`PORT MAP (`
485			`vss => vss,`
486			`vdd => vdd,`
487			`b => b(56),`
488			`en => en,`
489			`rst => rst,`
490			`a => a(56));`
491			`reg58 : reg01`
492			`PORT MAP (`
493			`vss => vss,`
494			`vdd => vdd,`
495			`b => b(57),`
496			`en => en,`
497			`rst => rst,`
498			`a => a(57));`
499			`reg59 : reg01`
500			`PORT MAP (`
501			`vss => vss,`
502			`vdd => vdd,`
503			`b => b(58),`
504			`en => en,`
505			`rst => rst,`
506			`a => a(58));`
507			`reg60 : reg01`
508			`PORT MAP (`
509			`vss => vss,`
510			`vdd => vdd,`
511			`b => b(59),`
512			`en => en,`
513			`rst => rst,`
514			`a => a(59));`
515			`reg61 : reg01`
516			`PORT MAP (`
517			`vss => vss,`
518			`vdd => vdd,`
519			`b => b(60),`
520			`en => en,`
521			`rst => rst,`
522			`a => a(60));`
523			`reg62 : reg01`
524			`PORT MAP (`
525			`vss => vss,`
526			`vdd => vdd,`
527			`b => b(61),`
528			`en => en,`
529			`rst => rst,`
530			`a => a(61));`
531			`reg63 : reg01`
532			`PORT MAP (`
533			`vss => vss,`
534			`vdd => vdd,`
535			`b => b(62),`
536			`en => en,`
537			`rst => rst,`
538			`a => a(62));`
539			`reg64 : reg01`
540			`PORT MAP (`
541			`vss => vss,`
542			`vdd => vdd,`
543			`b => b(63),`
544			`en => en,`
545			`rst => rst,`
546			`a => a(63));`
547
548			`end VST;`