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module sub86( CLK, RSTN, IA, ID, A, D, Q, WEN,BEN );
input         CLK,RSTN;
output [31:0] IA;
input  [15:0] ID;
output [31:0] A;
input  [31:0] D;
output [31:0] Q;
output        WEN;
output  [1:0] BEN;
wire          nncry,neqF,ngF,nlF,naF,nbF;
reg    [31:0] EAX,EBX,ECX,EDX,EBP,ESP,PC,regsrc,regdest,alu_out;
reg     [5:0] state,nstate;
reg     [2:0] src,dest;
reg           cry,ncry,prefx,nprefx,cmpr,eqF,gF,lF,aF,bF;
wire   [31:0] pc_ja,pc_jae,pc_jb,pc_jbe,pc_jg,pc_jge,pc_jl,pc_jle,pc_eq,pc_jp,pc_neq;
wire   [31:0] Sregsrc,Zregsrc,incPC,sft_out,smlEAX,smlECX;
wire   [32:0] adder_out,sub_out;
wire    [4:0] EBX_shtr;
wire signed [31:0] ssregsrc, ssregdest;
`define fetch 6'b111111
`define jmp   6'b000001
`define jmp2  6'b000010
`define jge   6'b000011
`define jge2  6'b000100
`define imm   6'b000101
`define imm2  6'b000110
`define lea   6'b000111
`define lea2  6'b001000
`define call  6'b001001
`define call2 6'b001010
`define ret   6'b001011
`define ret2  6'b001100
`define shift 6'b001110
`define jg    6'b001111
`define jg2   6'b010000
`define jl    6'b010001
`define jl2   6'b010010
`define jle   6'b010011
`define jle2  6'b010100
`define je    6'b010101
`define je2   6'b010110
`define jne   6'b010111
`define jne2  6'b011000
`define mul   6'b011001
`define mul2  6'b011010
`define shft2 6'b011011
`define jb    6'b011100
`define jb2   6'b011101
`define jbe   6'b011110
`define jbe2  6'b011111
`define ja    6'b100000
`define ja2   6'b100001
`define jae   6'b100010
`define jae2  6'b100011
`define sml1  6'b100100
`define sml2  6'b100101
`define sml3  6'b100110
`define sml4  6'b100111
`define init  6'b000000
 always @(posedge CLK)
     begin
      case (state) // cry control
         `sml1     : cry <= EAX[31] ^ ECX[31];
         default   : cry <= ncry & RSTN;
      endcase
      prefx <= nprefx & RSTN;
      state <= nstate & {6{RSTN}};
      if (cmpr) begin eqF <= neqF & RSTN; lF <= nlF & RSTN; gF <= ngF & RSTN;
                      bF  <=   bF & RSTN; aF <= naF & RSTN; end
           else begin eqF <=  eqF & RSTN; lF <=  lF & RSTN; gF <=  gF & RSTN;
                      bF  <=   bF & RSTN; aF <=  aF & RSTN; end
      case(state)  // EAX control
        `mul,`sml2  : EAX <= {EAX[30:0],1'b0};
        `mul2       : EAX <= EBX;
        `sml1       : EAX <= smlEAX;
        `sml3       : if (cry==1'b0) EAX <= EBX; else EAX <= ((~EBX) + 1'b1);
        default: if (dest==3'b000) EAX <= alu_out; else EAX<=EAX;
      endcase
      case(state)  // EBX control
        `jmp , `jg, `jge , `jl, `jle, `je, `jne, `imm, `call, `jb,`jbe,`ja,`jae,
        `lea        : EBX<={EBX[31:16],ID[7:0],ID[15:8]};
        `imm2       : EBX<={ID[7:0],ID[15:8], EBX[15:0]};
        `lea2       : EBX<={ID[7:0],ID[15:8], EBX[15:0]}+EBP;
        `mul,`sml2  : if (ECX[0] == 1'b1) EBX <= EAX+EBX; else EBX <= EBX;
        `shift      : EBX<={EBX[31:5],EBX_shtr};
        default     : if (dest==3'b011) EBX <= alu_out; else EBX <= EBX;
      endcase
      case(state)  // ECX control
        `mul,`sml2  : ECX <= {1'b0,ECX[31:1]};
        `sml1       : ECX <= smlECX;
        default     : if (dest==3'b001) ECX <= alu_out; else ECX<=ECX;
      endcase
      if (dest==3'b010) EDX <= alu_out; else EDX<=EDX;  // EDX control       
      case(state)  // ESP control
        `init       : ESP<=32'h00ff;
        `call       : ESP<=ESP - 4'b0100;
        `ret2       : ESP<=ESP + 4'b0100;
       default: if (dest==3'b100) ESP <= alu_out; else ESP<=ESP;
      endcase
      if (dest==3'b101) EBP <= alu_out; else EBP<=EBP;  // EBP control 
      case(state)  // PC control
       `init        : PC<=32'h00;
       `jae2        : PC<=pc_jae;
       `jbe2        : PC<=pc_jbe;
       `ja2         : PC<=pc_ja ;
       `jb2         : PC<=pc_jb ;
       `jge2        : PC<=pc_jge;
       `jle2        : PC<=pc_jle;
       `jg2         : PC<=pc_jg ;
       `jl2         : PC<=pc_jl ;
       `je2         : PC<=pc_eq ;
       `jne2        : PC<=pc_neq;
       `jmp2,`call2 : PC<=pc_jp ;
       `ret2        : PC<=D     ;
       `mul,`mul2,`sml1,`sml2,`sml3,`sml4,
       `shift       : PC<=PC    ;
       default      : if (nstate == `shift) PC<=PC; else PC<=incPC ;
      endcase
     end
// muxing for source selection, used in alu & moves
always@(src,EAX,ECX,EDX,EBX,ESP,EBP,D)
   case(src)
    3'b000 : regsrc = EAX;
    3'b001 : regsrc = ECX;
    3'b010 : regsrc = EDX;
    3'b100 : regsrc = ESP;
    3'b101 : regsrc = EBP;
    3'b111 : regsrc = D;
    default: regsrc = EBX;
   endcase
// muxing for 2nd operand selection, used in alu only
always@(dest,EAX,ECX,EDX,EBX,ESP,EBP,D)
   case(dest)
    3'b000 : regdest = EAX;
    3'b001 : regdest = ECX;
    3'b010 : regdest = EDX;
    3'b100 : regdest = ESP;
    3'b101 : regdest = EBP;
    3'b111 : regdest = D  ;
    default: regdest = EBX;
   endcase
// alu
always@(state,regdest,regsrc,ID,cry,Zregsrc,Sregsrc,sft_out,adder_out,sub_out)
  if (state == `fetch )
  case (ID[15:10])
   6'b000000 : {ncry,alu_out} =             adder_out ;  // ADD , carry generation
   6'b000010 : {ncry,alu_out} = {cry,regdest | regsrc};  // OR
   6'b000100 : {ncry,alu_out} =             adder_out ;  // ADD , carry use
   6'b000110 : {ncry,alu_out} =               sub_out ;  // SUB , carry use
   6'b001000 : {ncry,alu_out} = {cry,regdest & regsrc};  // AND
   6'b001010 : {ncry,alu_out} =               sub_out ;  // SUB , carry generation
   6'b001100 : {ncry,alu_out} = {cry,regdest ^ regsrc};  // XOR
   6'b100010 : {ncry,alu_out} = {cry,          regsrc};  // MOVE
   6'b101101 : {ncry,alu_out} = {cry,         Zregsrc};  // MOVE
   6'b101111 : {ncry,alu_out} = {cry,         Sregsrc};  // MOVE
   //6'b110000 : {ncry,alu_out} = {cry, sft_out[31:0]};  // SHIFT
   //6'b110100 : {ncry,alu_out} = {cry, sft_out[31:0]};  // SHIFT
   default   : {ncry,alu_out} = {cry,regdest         };  // DO NOTHING
  endcase
  else if (state == `shift ) {ncry,alu_out} = {cry,sft_out           };
  else {ncry,alu_out} = {cry,regdest         };
// Main instruction decode
always @(ID,state,ECX,EBX_shtr)
 begin
   // One cycle instructions, operand selection
   if ((state == `fetch) || (state ==`shift))
     case ({ID[15:14],ID[9],ID[7]})
      4'b1000  : begin src=ID[5:3]; dest= 3'b111; end  // store into ram (x89 x00)
      4'b1010  : begin src= 3'b111; dest=ID[5:3]; end  // load from ram  (x8b x00)
      //4'b1001  : begin src=ID[5:3]; dest=ID[2:0]; end  // reg2reg xfer   (x89 xC0)
      4'b1011  : begin src=ID[2:0]; dest=ID[5:3]; end  // reg2reg xfer   (x8b xC0)
      //4'b0001  : begin src=ID[5:3]; dest=ID[2:0]; end  // alu op
      4'b0011  : begin src=ID[2:0]; dest=ID[5:3]; end  // alu op
      default  : begin src=ID[5:3]; dest=ID[2:0]; end  // shift
     endcase
   else if (state==`ret)
        begin src = 3'b011; dest = 3'b100; end
   else begin src = 3'b000; dest = 3'b000; end
   // instructions that require more than one cycle to execute
   if (state == `fetch)
   begin
    casex(ID)
     16'h90e9: nstate = `jmp;
     16'h0f87: nstate = `ja;
     16'h0f86: nstate = `jbe;
     16'h0f83: nstate = `jae;
     16'h0f82: nstate = `jb;
     16'h0f8f: nstate = `jg;
     16'h0f8e: nstate = `jle;
     16'h0f8d: nstate = `jge;
     16'h0f8c: nstate = `jl;
     16'h0f85: nstate = `jne;
     16'h0f84: nstate = `je;
     16'h90bb: nstate = `imm;
     16'h8d9d: nstate = `lea;
     16'h90e8: nstate = `call;
     16'h90c3: nstate = `ret;
     16'hc1xx: nstate = `shift;
     16'hd3xx: nstate = `shift;
     16'hf7e1: nstate = `mul;
     16'hafc1: nstate = `sml1;
     default : nstate = `fetch;
    endcase
    if (ID       == 16'h9066) nprefx = 1'b1; else nprefx = 1'b0;
    if (ID[15:8] ==  8'h39  ) cmpr   = 1'b1; else cmpr   = 1'b0;
   end
   else
   begin
        nprefx = 1'b0; cmpr   = 1'b0;
        if((state==`mul)&&!(ECX==32'b0)) nstate=`mul;
   else if((state==`mul)&& (ECX==32'b0)) nstate=`mul2;
   else if (state==`mul2)  nstate = `fetch;
   else if (state==`sml1)  nstate = `sml2;
   else if((state==`sml2)&&!(ECX==32'b0)) nstate=`sml2;
   else if((state==`sml2)&& (ECX==32'b0)) nstate=`sml3;
   else if (state==`sml1)  nstate = `sml3;
   else if (state==`jmp)   nstate = `jmp2;  else if (state==`jmp2)  nstate = `fetch;
   else if (state==`jne)   nstate = `jne2;  else if (state==`jne2)  nstate = `fetch;
   else if (state==`je )   nstate = `je2 ;  else if (state==`je2 )  nstate = `fetch;
   else if (state==`jge)   nstate = `jge2;  else if (state==`jge2)  nstate = `fetch;
   else if (state==`jg )   nstate = `jg2 ;  else if (state==`jg2 )  nstate = `fetch;
   else if (state==`jle)   nstate = `jle2;  else if (state==`jle2)  nstate = `fetch;
   else if (state==`jl )   nstate = `jl2 ;  else if (state==`jl2 )  nstate = `fetch;
   else if (state==`jae)   nstate = `jae2;  else if (state==`jae2)  nstate = `fetch;
   else if (state==`ja )   nstate = `ja2 ;  else if (state==`ja2 )  nstate = `fetch;
   else if (state==`jbe)   nstate = `jbe2;  else if (state==`jbe2)  nstate = `fetch;
   else if (state==`jb )   nstate = `jb2 ;  else if (state==`jb2 )  nstate = `fetch;
   else if (state==`imm)   nstate = `imm2;  else if (state==`imm2)  nstate = `fetch;
   else if (state==`lea)   nstate = `lea2;  else if (state==`lea2)  nstate = `fetch;
   else if (state==`call)  nstate = `call2; else if (state==`call2) nstate = `fetch;
   else if (state==`ret)   nstate = `ret2;  else if (state==`ret2)  nstate = `fetch;
   else if((state==`shift)&&!(EBX_shtr==5'b0)) nstate=`shift;
   else if((state==`shift)&& (EBX_shtr==5'b0)) nstate=`shft2;
   else                    nstate = `fetch;
   end
 end
assign ssregsrc = regsrc;
assign ssregdest= regdest;
assign  IA      = PC                ;
assign  A       = (state == `call2) ?  ESP          : EBX      ;
assign  Q       = (state == `call2) ?  incPC        : regsrc   ;
assign  WEN     = (ID[15:8]==8'h90) ?  1'b1         :
                  (state == `call2) ?  1'b0         :
                  (dest  == 3'b111) ?  1'b0         : 1'b1     ;
assign  Sregsrc =       ID[8]       ? { {16{regsrc[15]}} , regsrc[15:0] } :
                                      { {24{regsrc[7] }} , regsrc[7:0]  } ;
assign  Zregsrc =       ID[8]       ? {  16'b0           , regsrc[15:0] } :
                                      {  24'b0           , regsrc[7:0]  } ;
assign      BEN = (state == `call2 )  ? 1'b1 : { prefx   , ID[8]        } ;
assign     neqF = (regsrc == regdest) ? 1'b1 : 1'b0;
assign      nlF = (regsrc  > regdest) ? 1'b1 : 1'b0;
assign      ngF = ~(nlF | neqF );// (regsrc  < regdest) ? 1'b1 : 1'b0;
assign      nbF = (ssregsrc  > ssregdest) ? 1'b1 : 1'b0;
assign      naF = ~(nbF | neqF );// (regsrc  < regdest) ? 1'b1 : 1'b0;
assign    incPC = PC + 3'b010;
assign   pc_jge = (eqF|gF) ? pc_jp : incPC;
assign   pc_jle = (eqF|lF) ? pc_jp : incPC;
assign   pc_jg  = (gF    ) ? pc_jp : incPC;
assign   pc_jl  = (lF    ) ? pc_jp : incPC;
assign   pc_jae = (eqF|aF) ? pc_jp : incPC;
assign   pc_jbe = (eqF|bF) ? pc_jp : incPC;
assign   pc_ja  = (aF    ) ? pc_jp : incPC;
assign   pc_jb  = (bF    ) ? pc_jp : incPC;
assign   pc_eq  = (eqF   ) ? pc_jp : incPC;
assign   pc_neq = (eqF   ) ? incPC : pc_jp;
assign   pc_jp  = incPC+{ID,EBX[15:0]};
assign  sft_out = (src   == 3'b111) ? {regdest[31],regdest[31:1]} : //sar
                  (src   == 3'b101) ? {       1'b0,regdest[31:1]} : //shr
                                      {regdest[30:0],1'b0       } ; //shl
assign adder_out= nncry   + regsrc + regdest;
assign   sub_out= regdest - regsrc - nncry;
assign    nncry = (ID[12] ? cry : 1'b0);
assign EBX_shtr = EBX[4:0] - 1'b1;
assign smlEAX   = EAX[31] ? ((~EAX) + 1) : EAX;
assign smlECX   = ECX[31] ? ((~ECX) + 1) : ECX;
endmodule

Line No.	Rev	Author	Line
1	2	ultro	`module sub86( CLK, RSTN, IA, ID, A, D, Q, WEN,BEN );`
2	3	ultro	`input CLK,RSTN;`
3	2	ultro	`output [31:0] IA;`
4			`input [15:0] ID;`
5			`output [31:0] A;`
6			`input [31:0] D;`
7			`output [31:0] Q;`
8			`output WEN;`
9			`output [1:0] BEN;`
10	5	ultro	`wire nncry,neqF,ngF,nlF,naF,nbF;`
11	2	ultro	`reg [31:0] EAX,EBX,ECX,EDX,EBP,ESP,PC,regsrc,regdest,alu_out;`
12	5	ultro	`reg [5:0] state,nstate;`
13	2	ultro	`reg [2:0] src,dest;`
14	5	ultro	`reg cry,ncry,prefx,nprefx,cmpr,eqF,gF,lF,aF,bF;`
15			`wire [31:0] pc_ja,pc_jae,pc_jb,pc_jbe,pc_jg,pc_jge,pc_jl,pc_jle,pc_eq,pc_jp,pc_neq;`
16			`wire [31:0] Sregsrc,Zregsrc,incPC,sft_out,smlEAX,smlECX;`
17	3	ultro	`wire [32:0] adder_out,sub_out;`
18	5	ultro	`wire [4:0] EBX_shtr;`
19			`wire signed [31:0] ssregsrc, ssregdest;`
20			`define fetch 6'b111111
21			`define jmp 6'b000001
22			`define jmp2 6'b000010
23			`define jge 6'b000011
24			`define jge2 6'b000100
25			`define imm 6'b000101
26			`define imm2 6'b000110
27			`define lea 6'b000111
28			`define lea2 6'b001000
29			`define call 6'b001001
30			`define call2 6'b001010
31			`define ret 6'b001011
32			`define ret2 6'b001100
33			`define shift 6'b001110
34			`define jg 6'b001111
35			`define jg2 6'b010000
36			`define jl 6'b010001
37			`define jl2 6'b010010
38			`define jle 6'b010011
39			`define jle2 6'b010100
40			`define je 6'b010101
41			`define je2 6'b010110
42			`define jne 6'b010111
43			`define jne2 6'b011000
44			`define mul 6'b011001
45			`define mul2 6'b011010
46			`define shft2 6'b011011
47			`define jb 6'b011100
48			`define jb2 6'b011101
49			`define jbe 6'b011110
50			`define jbe2 6'b011111
51			`define ja 6'b100000
52			`define ja2 6'b100001
53			`define jae 6'b100010
54			`define jae2 6'b100011
55			`define sml1 6'b100100
56			`define sml2 6'b100101
57			`define sml3 6'b100110
58			`define sml4 6'b100111
59			`define init 6'b000000
60			`always @(posedge CLK)`
61			`begin`
62			`case (state) // cry control`
63			`sml1 : cry <= EAX[31] ^ ECX[31];
64			`default : cry <= ncry & RSTN;`
65			`endcase`
66			`prefx <= nprefx & RSTN;`
67			`state <= nstate & {6{RSTN}};`
68			`if (cmpr) begin eqF <= neqF & RSTN; lF <= nlF & RSTN; gF <= ngF & RSTN;`
69			`bF <= bF & RSTN; aF <= naF & RSTN; end`
70			`else begin eqF <= eqF & RSTN; lF <= lF & RSTN; gF <= gF & RSTN;`
71			`bF <= bF & RSTN; aF <= aF & RSTN; end`
72			`case(state) // EAX control`
73			`mul,`sml2 : EAX <= {EAX[30:0],1'b0};
74			`mul2 : EAX <= EBX;
75			`sml1 : EAX <= smlEAX;
76			`sml3 : if (cry==1'b0) EAX <= EBX; else EAX <= ((~EBX) + 1'b1);
77			`default: if (dest==3'b000) EAX <= alu_out; else EAX<=EAX;`
78			`endcase`
79			`case(state) // EBX control`
80			`jmp , `jg, `jge , `jl, `jle, `je, `jne, `imm, `call, `jb,`jbe,`ja,`jae,
81			`lea : EBX<={EBX[31:16],ID[7:0],ID[15:8]};
82			`imm2 : EBX<={ID[7:0],ID[15:8], EBX[15:0]};
83			`lea2 : EBX<={ID[7:0],ID[15:8], EBX[15:0]}+EBP;
84			`mul,`sml2 : if (ECX[0] == 1'b1) EBX <= EAX+EBX; else EBX <= EBX;
85			`shift : EBX<={EBX[31:5],EBX_shtr};
86			`default : if (dest==3'b011) EBX <= alu_out; else EBX <= EBX;`
87			`endcase`
88			`case(state) // ECX control`
89			`mul,`sml2 : ECX <= {1'b0,ECX[31:1]};
90			`sml1 : ECX <= smlECX;
91			`default : if (dest==3'b001) ECX <= alu_out; else ECX<=ECX;`
92			`endcase`
93			`if (dest==3'b010) EDX <= alu_out; else EDX<=EDX; // EDX control`
94			`case(state) // ESP control`
95			`init : ESP<=32'h00ff;
96			`call : ESP<=ESP - 4'b0100;
97			`ret2 : ESP<=ESP + 4'b0100;
98			`default: if (dest==3'b100) ESP <= alu_out; else ESP<=ESP;`
99			`endcase`
100			`if (dest==3'b101) EBP <= alu_out; else EBP<=EBP; // EBP control`
101			`case(state) // PC control`
102			`init : PC<=32'h00;
103			`jae2 : PC<=pc_jae;
104			`jbe2 : PC<=pc_jbe;
105			`ja2 : PC<=pc_ja ;
106			`jb2 : PC<=pc_jb ;
107			`jge2 : PC<=pc_jge;
108			`jle2 : PC<=pc_jle;
109			`jg2 : PC<=pc_jg ;
110			`jl2 : PC<=pc_jl ;
111			`je2 : PC<=pc_eq ;
112			`jne2 : PC<=pc_neq;
113			`jmp2,`call2 : PC<=pc_jp ;
114			`ret2 : PC<=D ;
115			`mul,`mul2,`sml1,`sml2,`sml3,`sml4,
116			`shift : PC<=PC ;
117			default : if (nstate == `shift) PC<=PC; else PC<=incPC ;
118			`endcase`
119			`end`
120	2	ultro	`// muxing for source selection, used in alu & moves`
121			`always@(src,EAX,ECX,EDX,EBX,ESP,EBP,D)`
122			`case(src)`
123			`3'b000 : regsrc = EAX;`
124			`3'b001 : regsrc = ECX;`
125			`3'b010 : regsrc = EDX;`
126			`3'b100 : regsrc = ESP;`
127			`3'b101 : regsrc = EBP;`
128			`3'b111 : regsrc = D;`
129			`default: regsrc = EBX;`
130			`endcase`
131			`// muxing for 2nd operand selection, used in alu only`
132			`always@(dest,EAX,ECX,EDX,EBX,ESP,EBP,D)`
133			`case(dest)`
134			`3'b000 : regdest = EAX;`
135			`3'b001 : regdest = ECX;`
136			`3'b010 : regdest = EDX;`
137			`3'b100 : regdest = ESP;`
138			`3'b101 : regdest = EBP;`
139			`3'b111 : regdest = D ;`
140			`default: regdest = EBX;`
141			`endcase`
142			`// alu`
143	4	ultro	`always@(state,regdest,regsrc,ID,cry,Zregsrc,Sregsrc,sft_out,adder_out,sub_out)`
144			if (state == `fetch )
145	2	ultro	`case (ID[15:10])`
146	4	ultro	`6'b000000 : {ncry,alu_out} = adder_out ; // ADD , carry generation`
147			`6'b000010 : {ncry,alu_out} = {cry,regdest \| regsrc}; // OR`
148			`6'b000100 : {ncry,alu_out} = adder_out ; // ADD , carry use`
149			`6'b000110 : {ncry,alu_out} = sub_out ; // SUB , carry use`
150			`6'b001000 : {ncry,alu_out} = {cry,regdest & regsrc}; // AND`
151			`6'b001010 : {ncry,alu_out} = sub_out ; // SUB , carry generation`
152			`6'b001100 : {ncry,alu_out} = {cry,regdest ^ regsrc}; // XOR`
153			`6'b100010 : {ncry,alu_out} = {cry, regsrc}; // MOVE`
154			`6'b101101 : {ncry,alu_out} = {cry, Zregsrc}; // MOVE`
155			`6'b101111 : {ncry,alu_out} = {cry, Sregsrc}; // MOVE`
156	5	ultro	`//6'b110000 : {ncry,alu_out} = {cry, sft_out[31:0]}; // SHIFT`
157			`//6'b110100 : {ncry,alu_out} = {cry, sft_out[31:0]}; // SHIFT`
158	4	ultro	`default : {ncry,alu_out} = {cry,regdest }; // DO NOTHING`
159	2	ultro	`endcase`
160	5	ultro	else if (state == `shift ) {ncry,alu_out} = {cry,sft_out };
161	4	ultro	`else {ncry,alu_out} = {cry,regdest };`
162	2	ultro	`// Main instruction decode`
163	5	ultro	`always @(ID,state,ECX,EBX_shtr)`
164	2	ultro	`begin`
165			`// One cycle instructions, operand selection`
166	5	ultro	if ((state == `fetch) \|\| (state ==`shift))
167	2	ultro	`case ({ID[15:14],ID[9],ID[7]})`
168			`4'b1000 : begin src=ID[5:3]; dest= 3'b111; end // store into ram (x89 x00)`
169			`4'b1010 : begin src= 3'b111; dest=ID[5:3]; end // load from ram (x8b x00)`
170	5	ultro	`//4'b1001 : begin src=ID[5:3]; dest=ID[2:0]; end // reg2reg xfer (x89 xC0)`
171	3	ultro	`4'b1011 : begin src=ID[2:0]; dest=ID[5:3]; end // reg2reg xfer (x8b xC0)`
172	5	ultro	`//4'b0001 : begin src=ID[5:3]; dest=ID[2:0]; end // alu op`
173	2	ultro	`4'b0011 : begin src=ID[2:0]; dest=ID[5:3]; end // alu op`
174			`default : begin src=ID[5:3]; dest=ID[2:0]; end // shift`
175			`endcase`
176			else if (state==`ret)
177			`begin src = 3'b011; dest = 3'b100; end`
178			`else begin src = 3'b000; dest = 3'b000; end`
179			`// instructions that require more than one cycle to execute`
180			if (state == `fetch)
181			`begin`
182			`casex(ID)`
183			16'h90e9: nstate = `jmp;
184	5	ultro	16'h0f87: nstate = `ja;
185			16'h0f86: nstate = `jbe;
186			16'h0f83: nstate = `jae;
187			16'h0f82: nstate = `jb;
188	2	ultro	16'h0f8f: nstate = `jg;
189			16'h0f8e: nstate = `jle;
190			16'h0f8d: nstate = `jge;
191			16'h0f8c: nstate = `jl;
192			16'h0f85: nstate = `jne;
193			16'h0f84: nstate = `je;
194			16'h90bb: nstate = `imm;
195			16'h8d9d: nstate = `lea;
196			16'h90e8: nstate = `call;
197			16'h90c3: nstate = `ret;
198	3	ultro	16'hc1xx: nstate = `shift;
199	5	ultro	16'hd3xx: nstate = `shift;
200			16'hf7e1: nstate = `mul;
201			16'hafc1: nstate = `sml1;
202	2	ultro	default : nstate = `fetch;
203			`endcase`
204			`if (ID == 16'h9066) nprefx = 1'b1; else nprefx = 1'b0;`
205			`if (ID[15:8] == 8'h39 ) cmpr = 1'b1; else cmpr = 1'b0;`
206			`end`
207			`else`
208			`begin`
209	3	ultro	`nprefx = 1'b0; cmpr = 1'b0;`
210	5	ultro	if((state==`mul)&&!(ECX==32'b0)) nstate=`mul;
211			else if((state==`mul)&& (ECX==32'b0)) nstate=`mul2;
212	3	ultro	else if (state==`mul2) nstate = `fetch;
213	5	ultro	else if (state==`sml1) nstate = `sml2;
214			else if((state==`sml2)&&!(ECX==32'b0)) nstate=`sml2;
215			else if((state==`sml2)&& (ECX==32'b0)) nstate=`sml3;
216			else if (state==`sml1) nstate = `sml3;
217	3	ultro	else if (state==`jmp) nstate = `jmp2; else if (state==`jmp2) nstate = `fetch;
218	2	ultro	else if (state==`jne) nstate = `jne2; else if (state==`jne2) nstate = `fetch;
219			else if (state==`je ) nstate = `je2 ; else if (state==`je2 ) nstate = `fetch;
220			else if (state==`jge) nstate = `jge2; else if (state==`jge2) nstate = `fetch;
221			else if (state==`jg ) nstate = `jg2 ; else if (state==`jg2 ) nstate = `fetch;
222			else if (state==`jle) nstate = `jle2; else if (state==`jle2) nstate = `fetch;
223			else if (state==`jl ) nstate = `jl2 ; else if (state==`jl2 ) nstate = `fetch;
224	5	ultro	else if (state==`jae) nstate = `jae2; else if (state==`jae2) nstate = `fetch;
225			else if (state==`ja ) nstate = `ja2 ; else if (state==`ja2 ) nstate = `fetch;
226			else if (state==`jbe) nstate = `jbe2; else if (state==`jbe2) nstate = `fetch;
227			else if (state==`jb ) nstate = `jb2 ; else if (state==`jb2 ) nstate = `fetch;
228	2	ultro	else if (state==`imm) nstate = `imm2; else if (state==`imm2) nstate = `fetch;
229			else if (state==`lea) nstate = `lea2; else if (state==`lea2) nstate = `fetch;
230			else if (state==`call) nstate = `call2; else if (state==`call2) nstate = `fetch;
231			else if (state==`ret) nstate = `ret2; else if (state==`ret2) nstate = `fetch;
232	5	ultro	else if((state==`shift)&&!(EBX_shtr==5'b0)) nstate=`shift;
233			else if((state==`shift)&& (EBX_shtr==5'b0)) nstate=`shft2;
234	2	ultro	else nstate = `fetch;
235			`end`
236			`end`
237	5	ultro	`assign ssregsrc = regsrc;`
238			`assign ssregdest= regdest;`
239	2	ultro	`assign IA = PC ;`
240	3	ultro	assign A = (state == `call2) ? ESP : EBX ;
241	2	ultro	assign Q = (state == `call2) ? incPC : regsrc ;
242			`assign WEN = (ID[15:8]==8'h90) ? 1'b1 :`
243			(state == `call2) ? 1'b0 :
244	4	ultro	`(dest == 3'b111) ? 1'b0 : 1'b1 ;`
245	2	ultro	`assign Sregsrc = ID[8] ? { {16{regsrc[15]}} , regsrc[15:0] } :`
246			`{ {24{regsrc[7] }} , regsrc[7:0] } ;`
247			`assign Zregsrc = ID[8] ? { 16'b0 , regsrc[15:0] } :`
248			`{ 24'b0 , regsrc[7:0] } ;`
249	5	ultro	assign BEN = (state == `call2 ) ? 1'b1 : { prefx , ID[8] } ;
250	2	ultro	`assign neqF = (regsrc == regdest) ? 1'b1 : 1'b0;`
251			`assign nlF = (regsrc > regdest) ? 1'b1 : 1'b0;`
252	5	ultro	`assign ngF = ~(nlF \| neqF );// (regsrc < regdest) ? 1'b1 : 1'b0;`
253			`assign nbF = (ssregsrc > ssregdest) ? 1'b1 : 1'b0;`
254			`assign naF = ~(nbF \| neqF );// (regsrc < regdest) ? 1'b1 : 1'b0;`
255	2	ultro	`assign incPC = PC + 3'b010;`
256	5	ultro	`assign pc_jge = (eqF\|gF) ? pc_jp : incPC;`
257			`assign pc_jle = (eqF\|lF) ? pc_jp : incPC;`
258			`assign pc_jg = (gF ) ? pc_jp : incPC;`
259			`assign pc_jl = (lF ) ? pc_jp : incPC;`
260			`assign pc_jae = (eqF\|aF) ? pc_jp : incPC;`
261			`assign pc_jbe = (eqF\|bF) ? pc_jp : incPC;`
262			`assign pc_ja = (aF ) ? pc_jp : incPC;`
263			`assign pc_jb = (bF ) ? pc_jp : incPC;`
264			`assign pc_eq = (eqF ) ? pc_jp : incPC;`
265			`assign pc_neq = (eqF ) ? incPC : pc_jp;`
266	2	ultro	`assign pc_jp = incPC+{ID,EBX[15:0]};`
267	5	ultro	`assign sft_out = (src == 3'b111) ? {regdest[31],regdest[31:1]} : //sar`
268			`(src == 3'b101) ? { 1'b0,regdest[31:1]} : //shr`
269			`{regdest[30:0],1'b0 } ; //shl`
270	2	ultro	`assign adder_out= nncry + regsrc + regdest;`
271			`assign sub_out= regdest - regsrc - nncry;`
272	4	ultro	`assign nncry = (ID[12] ? cry : 1'b0);`
273	5	ultro	`assign EBX_shtr = EBX[4:0] - 1'b1;`
274			`assign smlEAX = EAX[31] ? ((~EAX) + 1) : EAX;`
275			`assign smlECX = ECX[31] ? ((~ECX) + 1) : ECX;`
276	2	ultro	`endmodule`

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