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module sub86( CLK, RSTN, IA, ID, A, D, Q, WEN,BEN );
input         CLK,RSTN;
output [31:0] IA;
input  [15:0] ID;
output [31:0] A;
input  [31:0] D;
output [31:0] Q;
output        WEN;
output  [1:0] BEN;
wire          nncry,neqF,ngF,nlF,naF,nbF,divF1,divF2;
reg    [31:0] EAX,EBX,ECX,EDX,EBP,ESP,PC,regsrc,regdest,alu_out;
reg     [5:0] state,nstate;
reg     [2:0] src,dest;
reg           cry,ncry,prefx,nprefx,cmpr,eqF,gF,lF,aF,bF;
wire   [31:0] pc_ja,pc_jae,pc_jb,pc_jbe,pc_jg,pc_jge,pc_jl,pc_jle,pc_eq,pc_jp,pc_neq;
wire   [31:0] Sregsrc,Zregsrc,incPC,sft_out,smlEAX,smlECX;
wire   [32:0] adder_out,sub_out;
wire    [4:0] EBX_shtr;
wire signed [31:0] ssregsrc, ssregdest;
`define fetch 6'b111111
`define jmp   6'b000001
`define jmp2  6'b000010
`define jge   6'b000011
`define jge2  6'b000100
`define imm   6'b000101
`define imm2  6'b000110
`define lea   6'b000111
`define lea2  6'b001000
`define call  6'b001001
`define call2 6'b001010
`define ret   6'b001011
`define ret2  6'b001100
`define shift 6'b001110
`define jg    6'b001111
`define jg2   6'b010000
`define jl    6'b010001
`define jl2   6'b010010
`define jle   6'b010011
`define jle2  6'b010100
`define je    6'b010101
`define je2   6'b010110
`define jne   6'b010111
`define jne2  6'b011000
`define mul   6'b011001
`define mul2  6'b011010
`define shft2 6'b011011
`define jb    6'b011100
`define jb2   6'b011101
`define jbe   6'b011110
`define jbe2  6'b011111
`define ja    6'b100000
`define ja2   6'b100001
`define jae   6'b100010
`define jae2  6'b100011
`define sml1  6'b100100
`define sml2  6'b100101
`define sml3  6'b100110
`define sml4  6'b100111
`define sdv1  6'b101000
`define sdv2  6'b101001
`define sdv3  6'b101010
`define sdv4  6'b101011
`define div1  6'b101100
`define init  6'b000000
 always @(posedge CLK)
     begin
      case (state) // cry control
         `sml1,`sdv1: cry <= EAX[31] ^ ECX[31];
         `div1      : cry <= 1'b0;
         default    : cry <= ncry & RSTN;
      endcase
      prefx <= nprefx & RSTN;
      state <= nstate & {6{RSTN}};
      if (cmpr) begin eqF <= neqF & RSTN; lF <= nlF & RSTN; gF <= ngF & RSTN;
                      bF  <=   bF & RSTN; aF <= naF & RSTN; end
           else begin eqF <=  eqF & RSTN; lF <=  lF & RSTN; gF <=  gF & RSTN;
                      bF  <=   bF & RSTN; aF <=  aF & RSTN; end
      case(state)  // EAX control
        `mul,`sml2  : EAX <= {EAX[30:0],1'b0};
        `mul2       : EAX <= EBX;
        `sml1       : EAX <= smlEAX;
        `sml3       : if (cry==1'b0) EAX <= EBX; else EAX <= ((~EBX) + 1'b1);
        `sdv1,`div1 : EAX <= 32'b0;
        `sdv3       : if (nlF==1'b0) EAX <= EAX + ( 1 << EBX_shtr); else EAX <=EAX;
        `sdv4       : if (cry==1'b1) EAX <= ((~EAX) + 1'b1); else EAX <= EAX;
        default: if (dest==3'b000) EAX <= alu_out; else EAX<=EAX;
      endcase
      case(state)  // EBX control
        `jmp , `jg, `jge , `jl, `jle, `je, `jne, `imm, `call, `jb,`jbe,`ja,`jae,
        `lea        : EBX<={EBX[31:16],ID[7:0],ID[15:8]};
        `imm2       : EBX<={ID[7:0],ID[15:8], EBX[15:0]};
        `lea2       : EBX<={ID[7:0],ID[15:8], EBX[15:0]}+EBP;
        `mul,`sml2  : if (ECX[0] == 1'b1) EBX <= EAX+EBX; else EBX <= EBX;
        `shift      : EBX<={EBX[31:5],EBX_shtr};
        `sdv1       : EBX<={EAX[31],ECX[31],EBX[29:0]};
        `div1       : EBX<={          2'b00,EBX[29:0]};
        `sdv2       : if (divF1==1'b0 ) EBX <= {EBX[31:5],(EBX[4:0]+1'b1)}; else EBX <= EBX;
        `sdv3       : if (divF1==1'b1 ) EBX <= {EBX[31:5],EBX_shtr}; else EBX <= EBX;
        default     : if (dest==3'b011) EBX <= alu_out; else EBX <= EBX;
      endcase
      case(state)  // ECX control
        `mul,`sml2  : ECX <= {1'b0,ECX[31:1]};
        `sml1,`sdv1 : ECX <= smlECX;
        `div1       : ECX <= ECX;
        `sdv2       : if (divF1==1'b0 ) ECX <= {ECX[30:0],1'b0}; else ECX<=ECX;
        `sdv3       : if((divF1==1'b1 ) && (divF2==1'b0)) ECX <= {1'b0,ECX[31:1]}; else ECX<=ECX;
        `sdv4       : if (EBX[30] == 1'b1) ECX <= ((~ECX) + 1); else ECX<=ECX;
        default     : if (dest==3'b001) ECX <= alu_out; else ECX<=ECX;
      endcase
      case(state)  // EDX control
        `sdv1       : EDX <= smlEAX;
        `div1       : EDX <=    EAX;
        `sdv3       : if (nlF==1'b0) EDX <= EDX - ECX; else EDX <= EDX;
        `sdv4       : if (EBX[31] == 1'b1) EDX <= ((~EDX) + 1); else EDX<=EDX;
        default     : if (dest==3'b010) EDX <= alu_out; else EDX<=EDX;
      endcase
      case(state)  // ESP control
        `init       : ESP<=32'h00ff;
        `call       : ESP<=ESP - 4'b0100;
        `ret2       : ESP<=ESP + 4'b0100;
       default: if (dest==3'b100) ESP <= alu_out; else ESP<=ESP;
      endcase
      if (dest==3'b101) EBP <= alu_out; else EBP<=EBP;  // EBP control 
      case(state)  // PC control
       `init        : PC<=32'h00;
       `jae2        : PC<=pc_jae;
       `jbe2        : PC<=pc_jbe;
       `ja2         : PC<=pc_ja ;
       `jb2         : PC<=pc_jb ;
       `jge2        : PC<=pc_jge;
       `jle2        : PC<=pc_jle;
       `jg2         : PC<=pc_jg ;
       `jl2         : PC<=pc_jl ;
       `je2         : PC<=pc_eq ;
       `jne2        : PC<=pc_neq;
       `jmp2,`call2 : PC<=pc_jp ;
       `ret2        : PC<=D     ;
       `mul,`mul2,`sml1,`sml2,`sml3,`sml4,`sdv1,`sdv2,`sdv3,`sdv4,`div1,
       `shift       : PC<=PC    ;
       default      : if (nstate == `shift) PC<=PC; else PC<=incPC ;
      endcase
     end
// muxing for source selection, used in alu & moves
always@(src,EAX,ECX,EDX,EBX,ESP,EBP,D)
   case(src)
    3'b000 : regsrc = EAX;
    3'b001 : regsrc = ECX;
    3'b010 : regsrc = EDX;
    3'b100 : regsrc = ESP;
    3'b101 : regsrc = EBP;
    3'b111 : regsrc = D;
    default: regsrc = EBX;
   endcase
// muxing for 2nd operand selection, used in alu only
always@(dest,EAX,ECX,EDX,EBX,ESP,EBP,D)
   case(dest)
    3'b000 : regdest = EAX;
    3'b001 : regdest = ECX;
    3'b010 : regdest = EDX;
    3'b100 : regdest = ESP;
    3'b101 : regdest = EBP;
    3'b111 : regdest = D  ;
    default: regdest = EBX;
   endcase
// alu
always@(state,regdest,regsrc,ID,cry,Zregsrc,Sregsrc,sft_out,adder_out,sub_out)
  if (state == `fetch )
  case (ID[15:10])
   6'b000000 : {ncry,alu_out} =             adder_out ;  // ADD , carry generation
   6'b000010 : {ncry,alu_out} = {cry,regdest | regsrc};  // OR
   6'b000100 : {ncry,alu_out} =             adder_out ;  // ADD , carry use
   6'b000110 : {ncry,alu_out} =               sub_out ;  // SUB , carry use
   6'b001000 : {ncry,alu_out} = {cry,regdest & regsrc};  // AND
   6'b001010 : {ncry,alu_out} =               sub_out ;  // SUB , carry generation
   6'b001100 : {ncry,alu_out} = {cry,regdest ^ regsrc};  // XOR
   6'b100010 : {ncry,alu_out} = {cry,          regsrc};  // MOVE
   6'b101101 : {ncry,alu_out} = {cry,         Zregsrc};  // MOVE
   6'b101111 : {ncry,alu_out} = {cry,         Sregsrc};  // MOVE
   //6'b110000 : {ncry,alu_out} = {cry, sft_out[31:0]};  // SHIFT
   //6'b110100 : {ncry,alu_out} = {cry, sft_out[31:0]};  // SHIFT
   default   : {ncry,alu_out} = {cry,regdest         };  // DO NOTHING
  endcase
  else if (state == `shift ) {ncry,alu_out} = {cry,sft_out           };
  else {ncry,alu_out} = {cry,regdest         };
// Main instruction decode
always @(ID,state,ECX,EBX_shtr,EAX,divF1,divF2)
 begin
   // One cycle instructions, operand selection
   if ((state == `fetch) || (state ==`shift))
     case ({ID[15:14],ID[9],ID[7]})
      4'b1000  : begin src=ID[5:3]; dest= 3'b111; end  // store into ram (x89 x00)
      4'b1010  : begin src= 3'b111; dest=ID[5:3]; end  // load from ram  (x8b x00)
      //4'b1001  : begin src=ID[5:3]; dest=ID[2:0]; end  // reg2reg xfer   (x89 xC0)
      4'b1011  : begin src=ID[2:0]; dest=ID[5:3]; end  // reg2reg xfer   (x8b xC0)
      //4'b0001  : begin src=ID[5:3]; dest=ID[2:0]; end  // alu op
      4'b0011  : begin src=ID[2:0]; dest=ID[5:3]; end  // alu op
      default  : begin src=ID[5:3]; dest=ID[2:0]; end  // shift
     endcase
   else if (state==`ret)
        begin src = 3'b011; dest = 3'b100; end
   else if (state==`sdv3)
        begin src = 3'b001; dest = 3'b010; end
   else begin src = 3'b000; dest = 3'b000; end
   // instructions that require more than one cycle to execute
   if (state == `fetch)
   begin
    casex(ID)
     16'h90e9: nstate = `jmp;
     16'h0f87: nstate = `ja;
     16'h0f86: nstate = `jbe;
     16'h0f83: nstate = `jae;
     16'h0f82: nstate = `jb;
     16'h0f8f: nstate = `jg;
     16'h0f8e: nstate = `jle;
     16'h0f8d: nstate = `jge;
     16'h0f8c: nstate = `jl;
     16'h0f85: nstate = `jne;
     16'h0f84: nstate = `je;
     16'h90bb: nstate = `imm;
     16'h8d9d: nstate = `lea;
     16'h90e8: nstate = `call;
     16'h90c3: nstate = `ret;
     16'hc1xx: nstate = `shift;
     16'hd3xx: nstate = `shift;
     16'hf7e1: nstate = `mul;
     16'hf7f9: nstate = `sdv1;
     16'hf7f1: nstate = `div1;
     16'hafc1: nstate = `sml1;
     default : nstate = `fetch;
    endcase
    if (ID       == 16'h9066) nprefx = 1'b1; else nprefx = 1'b0;
    if (ID[15:8] ==  8'h39  ) cmpr   = 1'b1; else cmpr   = 1'b0;
   end
   else
   begin
        nprefx = 1'b0; cmpr   = 1'b0;
        if((state==`mul)&&!(ECX==32'b0)) nstate=`mul;
   else if((state==`mul)&& (ECX==32'b0)) nstate=`mul2;
   else if (state==`mul2)  nstate = `fetch;
   else if (state==`sml1)  nstate = `sml2;
   else if((state==`sml2)&&!(ECX==32'b0)) nstate=`sml2;
   else if((state==`sml2)&& (ECX==32'b0)) nstate=`sml3;
   else if (state==`div1)  nstate = `sdv2;
   else if (state==`sdv1)  nstate = `sdv2;
   else if((state==`sdv2) && (divF1 == 1'b0) ) nstate=`sdv2;
   else if((state==`sdv2) && (divF1 == 1'b1) ) nstate=`sdv3;
   else if((state==`sdv3) && (divF2 == 1'b0) ) nstate=`sdv3;
   else if((state==`sdv3) && (divF2 == 1'b1) ) nstate=`sdv4;
   else if (state==`jmp)   nstate = `jmp2;  else if (state==`jmp2)  nstate = `fetch;
   else if (state==`jne)   nstate = `jne2;  else if (state==`jne2)  nstate = `fetch;
   else if (state==`je )   nstate = `je2 ;  else if (state==`je2 )  nstate = `fetch;
   else if (state==`jge)   nstate = `jge2;  else if (state==`jge2)  nstate = `fetch;
   else if (state==`jg )   nstate = `jg2 ;  else if (state==`jg2 )  nstate = `fetch;
   else if (state==`jle)   nstate = `jle2;  else if (state==`jle2)  nstate = `fetch;
   else if (state==`jl )   nstate = `jl2 ;  else if (state==`jl2 )  nstate = `fetch;
   else if (state==`jae)   nstate = `jae2;  else if (state==`jae2)  nstate = `fetch;
   else if (state==`ja )   nstate = `ja2 ;  else if (state==`ja2 )  nstate = `fetch;
   else if (state==`jbe)   nstate = `jbe2;  else if (state==`jbe2)  nstate = `fetch;
   else if (state==`jb )   nstate = `jb2 ;  else if (state==`jb2 )  nstate = `fetch;
   else if (state==`imm)   nstate = `imm2;  else if (state==`imm2)  nstate = `fetch;
   else if (state==`lea)   nstate = `lea2;  else if (state==`lea2)  nstate = `fetch;
   else if (state==`call)  nstate = `call2; else if (state==`call2) nstate = `fetch;
   else if (state==`ret)   nstate = `ret2;  else if (state==`ret2)  nstate = `fetch;
   else if((state==`shift)&&!(EBX_shtr==5'b0)) nstate=`shift;
   else if((state==`shift)&& (EBX_shtr==5'b0)) nstate=`shft2;
   else                    nstate = `fetch;
   end
 end
assign ssregsrc = regsrc;
assign ssregdest= regdest;
assign  IA      = PC                ;
assign  A       = (state == `call2) ?  ESP          : EBX      ;
assign  Q       = (state == `call2) ?  incPC        : regsrc   ;
assign  WEN     = (ID[15:8]==8'h90) ?  1'b1         :
                  (state == `call2) ?  1'b0         :
                  (dest  == 3'b111) ?  1'b0         : 1'b1     ;
assign  Sregsrc =       ID[8]       ? { {16{regsrc[15]}} , regsrc[15:0] } :
                                      { {24{regsrc[7] }} , regsrc[7:0]  } ;
assign  Zregsrc =       ID[8]       ? {  16'b0           , regsrc[15:0] } :
                                      {  24'b0           , regsrc[7:0]  } ;
assign      BEN = (state == `call2 )  ? 1'b1 : { prefx   , ID[8]        } ;
assign     neqF = (regsrc == regdest) ? 1'b1 : 1'b0;
assign      nlF = (regsrc  > regdest) ? 1'b1 : 1'b0;
assign      ngF = ~(nlF | neqF );// (regsrc  < regdest) ? 1'b1 : 1'b0;
assign      nbF = (ssregsrc  > ssregdest) ? 1'b1 : 1'b0;
assign      naF = ~(nbF | neqF );// (regsrc  < regdest) ? 1'b1 : 1'b0;
assign    incPC = PC + 3'b010;
assign   pc_jge = (eqF|gF) ? pc_jp : incPC;
assign   pc_jle = (eqF|lF) ? pc_jp : incPC;
assign   pc_jg  = (gF    ) ? pc_jp : incPC;
assign   pc_jl  = (lF    ) ? pc_jp : incPC;
assign   pc_jae = (eqF|aF) ? pc_jp : incPC;
assign   pc_jbe = (eqF|bF) ? pc_jp : incPC;
assign   pc_ja  = (aF    ) ? pc_jp : incPC;
assign   pc_jb  = (bF    ) ? pc_jp : incPC;
assign   pc_eq  = (eqF   ) ? pc_jp : incPC;
assign   pc_neq = (eqF   ) ? incPC : pc_jp;
assign   pc_jp  = incPC+{ID,EBX[15:0]};
assign  sft_out = (src   == 3'b111) ? {regdest[31],regdest[31:1]} : //sar
                  (src   == 3'b101) ? {       1'b0,regdest[31:1]} : //shr
                                      {regdest[30:0],1'b0       } ; //shl
assign adder_out= nncry   + regsrc + regdest;
assign   sub_out= regdest - regsrc - nncry;
assign    nncry = (ID[12] ? cry : 1'b0);
assign EBX_shtr = EBX[4:0] - 1'b1;
assign   smlEAX = EAX[31] ? ((~EAX) + 1) : EAX;
assign   smlECX = ECX[31] ? ((~ECX) + 1) : ECX;
assign    divF1 = ({ECX[30:0],1'b0}  > EDX) ? 1'b1 : 1'b0;
assign    divF2 = (EBX_shtr == 5'b00000) ? 1'b1 : 1'b0;
endmodule

Line No.	Rev	Author	Line
1	2	ultro	`module sub86( CLK, RSTN, IA, ID, A, D, Q, WEN,BEN );`
2	3	ultro	`input CLK,RSTN;`
3	2	ultro	`output [31:0] IA;`
4			`input [15:0] ID;`
5			`output [31:0] A;`
6			`input [31:0] D;`
7			`output [31:0] Q;`
8			`output WEN;`
9			`output [1:0] BEN;`
10	6	ultro	`wire nncry,neqF,ngF,nlF,naF,nbF,divF1,divF2;`
11	2	ultro	`reg [31:0] EAX,EBX,ECX,EDX,EBP,ESP,PC,regsrc,regdest,alu_out;`
12	5	ultro	`reg [5:0] state,nstate;`
13	2	ultro	`reg [2:0] src,dest;`
14	5	ultro	`reg cry,ncry,prefx,nprefx,cmpr,eqF,gF,lF,aF,bF;`
15			`wire [31:0] pc_ja,pc_jae,pc_jb,pc_jbe,pc_jg,pc_jge,pc_jl,pc_jle,pc_eq,pc_jp,pc_neq;`
16			`wire [31:0] Sregsrc,Zregsrc,incPC,sft_out,smlEAX,smlECX;`
17	3	ultro	`wire [32:0] adder_out,sub_out;`
18	5	ultro	`wire [4:0] EBX_shtr;`
19			`wire signed [31:0] ssregsrc, ssregdest;`
20			`define fetch 6'b111111
21			`define jmp 6'b000001
22			`define jmp2 6'b000010
23			`define jge 6'b000011
24			`define jge2 6'b000100
25			`define imm 6'b000101
26			`define imm2 6'b000110
27			`define lea 6'b000111
28			`define lea2 6'b001000
29			`define call 6'b001001
30			`define call2 6'b001010
31			`define ret 6'b001011
32			`define ret2 6'b001100
33			`define shift 6'b001110
34			`define jg 6'b001111
35			`define jg2 6'b010000
36			`define jl 6'b010001
37			`define jl2 6'b010010
38			`define jle 6'b010011
39			`define jle2 6'b010100
40			`define je 6'b010101
41			`define je2 6'b010110
42			`define jne 6'b010111
43			`define jne2 6'b011000
44			`define mul 6'b011001
45			`define mul2 6'b011010
46			`define shft2 6'b011011
47			`define jb 6'b011100
48			`define jb2 6'b011101
49			`define jbe 6'b011110
50			`define jbe2 6'b011111
51			`define ja 6'b100000
52			`define ja2 6'b100001
53			`define jae 6'b100010
54			`define jae2 6'b100011
55			`define sml1 6'b100100
56			`define sml2 6'b100101
57			`define sml3 6'b100110
58			`define sml4 6'b100111
59	6	ultro	`define sdv1 6'b101000
60			`define sdv2 6'b101001
61			`define sdv3 6'b101010
62			`define sdv4 6'b101011
63			`define div1 6'b101100
64	5	ultro	`define init 6'b000000
65			`always @(posedge CLK)`
66			`begin`
67			`case (state) // cry control`
68	6	ultro	`sml1,`sdv1: cry <= EAX[31] ^ ECX[31];
69			`div1 : cry <= 1'b0;
70			`default : cry <= ncry & RSTN;`
71	5	ultro	`endcase`
72			`prefx <= nprefx & RSTN;`
73			`state <= nstate & {6{RSTN}};`
74			`if (cmpr) begin eqF <= neqF & RSTN; lF <= nlF & RSTN; gF <= ngF & RSTN;`
75			`bF <= bF & RSTN; aF <= naF & RSTN; end`
76			`else begin eqF <= eqF & RSTN; lF <= lF & RSTN; gF <= gF & RSTN;`
77			`bF <= bF & RSTN; aF <= aF & RSTN; end`
78			`case(state) // EAX control`
79			`mul,`sml2 : EAX <= {EAX[30:0],1'b0};
80			`mul2 : EAX <= EBX;
81			`sml1 : EAX <= smlEAX;
82			`sml3 : if (cry==1'b0) EAX <= EBX; else EAX <= ((~EBX) + 1'b1);
83	6	ultro	`sdv1,`div1 : EAX <= 32'b0;
84			`sdv3 : if (nlF==1'b0) EAX <= EAX + ( 1 << EBX_shtr); else EAX <=EAX;
85			`sdv4 : if (cry==1'b1) EAX <= ((~EAX) + 1'b1); else EAX <= EAX;
86	5	ultro	`default: if (dest==3'b000) EAX <= alu_out; else EAX<=EAX;`
87			`endcase`
88			`case(state) // EBX control`
89			`jmp , `jg, `jge , `jl, `jle, `je, `jne, `imm, `call, `jb,`jbe,`ja,`jae,
90			`lea : EBX<={EBX[31:16],ID[7:0],ID[15:8]};
91			`imm2 : EBX<={ID[7:0],ID[15:8], EBX[15:0]};
92			`lea2 : EBX<={ID[7:0],ID[15:8], EBX[15:0]}+EBP;
93			`mul,`sml2 : if (ECX[0] == 1'b1) EBX <= EAX+EBX; else EBX <= EBX;
94			`shift : EBX<={EBX[31:5],EBX_shtr};
95	6	ultro	`sdv1 : EBX<={EAX[31],ECX[31],EBX[29:0]};
96			`div1 : EBX<={ 2'b00,EBX[29:0]};
97			`sdv2 : if (divF1==1'b0 ) EBX <= {EBX[31:5],(EBX[4:0]+1'b1)}; else EBX <= EBX;
98			`sdv3 : if (divF1==1'b1 ) EBX <= {EBX[31:5],EBX_shtr}; else EBX <= EBX;
99	5	ultro	`default : if (dest==3'b011) EBX <= alu_out; else EBX <= EBX;`
100			`endcase`
101			`case(state) // ECX control`
102			`mul,`sml2 : ECX <= {1'b0,ECX[31:1]};
103	6	ultro	`sml1,`sdv1 : ECX <= smlECX;
104			`div1 : ECX <= ECX;
105			`sdv2 : if (divF1==1'b0 ) ECX <= {ECX[30:0],1'b0}; else ECX<=ECX;
106			`sdv3 : if((divF1==1'b1 ) && (divF2==1'b0)) ECX <= {1'b0,ECX[31:1]}; else ECX<=ECX;
107			`sdv4 : if (EBX[30] == 1'b1) ECX <= ((~ECX) + 1); else ECX<=ECX;
108	5	ultro	`default : if (dest==3'b001) ECX <= alu_out; else ECX<=ECX;`
109			`endcase`
110	6	ultro	`case(state) // EDX control`
111			`sdv1 : EDX <= smlEAX;
112			`div1 : EDX <= EAX;
113			`sdv3 : if (nlF==1'b0) EDX <= EDX - ECX; else EDX <= EDX;
114			`sdv4 : if (EBX[31] == 1'b1) EDX <= ((~EDX) + 1); else EDX<=EDX;
115			`default : if (dest==3'b010) EDX <= alu_out; else EDX<=EDX;`
116			`endcase`
117	5	ultro	`case(state) // ESP control`
118			`init : ESP<=32'h00ff;
119			`call : ESP<=ESP - 4'b0100;
120			`ret2 : ESP<=ESP + 4'b0100;
121			`default: if (dest==3'b100) ESP <= alu_out; else ESP<=ESP;`
122			`endcase`
123			`if (dest==3'b101) EBP <= alu_out; else EBP<=EBP; // EBP control`
124			`case(state) // PC control`
125			`init : PC<=32'h00;
126			`jae2 : PC<=pc_jae;
127			`jbe2 : PC<=pc_jbe;
128			`ja2 : PC<=pc_ja ;
129			`jb2 : PC<=pc_jb ;
130			`jge2 : PC<=pc_jge;
131			`jle2 : PC<=pc_jle;
132			`jg2 : PC<=pc_jg ;
133			`jl2 : PC<=pc_jl ;
134			`je2 : PC<=pc_eq ;
135			`jne2 : PC<=pc_neq;
136			`jmp2,`call2 : PC<=pc_jp ;
137			`ret2 : PC<=D ;
138	6	ultro	`mul,`mul2,`sml1,`sml2,`sml3,`sml4,`sdv1,`sdv2,`sdv3,`sdv4,`div1,
139	5	ultro	`shift : PC<=PC ;
140			default : if (nstate == `shift) PC<=PC; else PC<=incPC ;
141			`endcase`
142			`end`
143	2	ultro	`// muxing for source selection, used in alu & moves`
144			`always@(src,EAX,ECX,EDX,EBX,ESP,EBP,D)`
145			`case(src)`
146			`3'b000 : regsrc = EAX;`
147			`3'b001 : regsrc = ECX;`
148			`3'b010 : regsrc = EDX;`
149			`3'b100 : regsrc = ESP;`
150			`3'b101 : regsrc = EBP;`
151			`3'b111 : regsrc = D;`
152			`default: regsrc = EBX;`
153			`endcase`
154			`// muxing for 2nd operand selection, used in alu only`
155			`always@(dest,EAX,ECX,EDX,EBX,ESP,EBP,D)`
156			`case(dest)`
157			`3'b000 : regdest = EAX;`
158			`3'b001 : regdest = ECX;`
159			`3'b010 : regdest = EDX;`
160			`3'b100 : regdest = ESP;`
161			`3'b101 : regdest = EBP;`
162			`3'b111 : regdest = D ;`
163			`default: regdest = EBX;`
164			`endcase`
165			`// alu`
166	4	ultro	`always@(state,regdest,regsrc,ID,cry,Zregsrc,Sregsrc,sft_out,adder_out,sub_out)`
167			if (state == `fetch )
168	2	ultro	`case (ID[15:10])`
169	4	ultro	`6'b000000 : {ncry,alu_out} = adder_out ; // ADD , carry generation`
170			`6'b000010 : {ncry,alu_out} = {cry,regdest \| regsrc}; // OR`
171			`6'b000100 : {ncry,alu_out} = adder_out ; // ADD , carry use`
172			`6'b000110 : {ncry,alu_out} = sub_out ; // SUB , carry use`
173			`6'b001000 : {ncry,alu_out} = {cry,regdest & regsrc}; // AND`
174			`6'b001010 : {ncry,alu_out} = sub_out ; // SUB , carry generation`
175			`6'b001100 : {ncry,alu_out} = {cry,regdest ^ regsrc}; // XOR`
176			`6'b100010 : {ncry,alu_out} = {cry, regsrc}; // MOVE`
177			`6'b101101 : {ncry,alu_out} = {cry, Zregsrc}; // MOVE`
178			`6'b101111 : {ncry,alu_out} = {cry, Sregsrc}; // MOVE`
179	5	ultro	`//6'b110000 : {ncry,alu_out} = {cry, sft_out[31:0]}; // SHIFT`
180			`//6'b110100 : {ncry,alu_out} = {cry, sft_out[31:0]}; // SHIFT`
181	4	ultro	`default : {ncry,alu_out} = {cry,regdest }; // DO NOTHING`
182	2	ultro	`endcase`
183	5	ultro	else if (state == `shift ) {ncry,alu_out} = {cry,sft_out };
184	4	ultro	`else {ncry,alu_out} = {cry,regdest };`
185	2	ultro	`// Main instruction decode`
186	6	ultro	`always @(ID,state,ECX,EBX_shtr,EAX,divF1,divF2)`
187	2	ultro	`begin`
188			`// One cycle instructions, operand selection`
189	5	ultro	if ((state == `fetch) \|\| (state ==`shift))
190	2	ultro	`case ({ID[15:14],ID[9],ID[7]})`
191			`4'b1000 : begin src=ID[5:3]; dest= 3'b111; end // store into ram (x89 x00)`
192			`4'b1010 : begin src= 3'b111; dest=ID[5:3]; end // load from ram (x8b x00)`
193	5	ultro	`//4'b1001 : begin src=ID[5:3]; dest=ID[2:0]; end // reg2reg xfer (x89 xC0)`
194	3	ultro	`4'b1011 : begin src=ID[2:0]; dest=ID[5:3]; end // reg2reg xfer (x8b xC0)`
195	5	ultro	`//4'b0001 : begin src=ID[5:3]; dest=ID[2:0]; end // alu op`
196	2	ultro	`4'b0011 : begin src=ID[2:0]; dest=ID[5:3]; end // alu op`
197			`default : begin src=ID[5:3]; dest=ID[2:0]; end // shift`
198			`endcase`
199			else if (state==`ret)
200			`begin src = 3'b011; dest = 3'b100; end`
201	6	ultro	else if (state==`sdv3)
202			`begin src = 3'b001; dest = 3'b010; end`
203	2	ultro	`else begin src = 3'b000; dest = 3'b000; end`
204			`// instructions that require more than one cycle to execute`
205			if (state == `fetch)
206			`begin`
207			`casex(ID)`
208			16'h90e9: nstate = `jmp;
209	5	ultro	16'h0f87: nstate = `ja;
210			16'h0f86: nstate = `jbe;
211			16'h0f83: nstate = `jae;
212			16'h0f82: nstate = `jb;
213	2	ultro	16'h0f8f: nstate = `jg;
214			16'h0f8e: nstate = `jle;
215			16'h0f8d: nstate = `jge;
216			16'h0f8c: nstate = `jl;
217			16'h0f85: nstate = `jne;
218			16'h0f84: nstate = `je;
219			16'h90bb: nstate = `imm;
220			16'h8d9d: nstate = `lea;
221			16'h90e8: nstate = `call;
222			16'h90c3: nstate = `ret;
223	3	ultro	16'hc1xx: nstate = `shift;
224	5	ultro	16'hd3xx: nstate = `shift;
225	6	ultro	16'hf7e1: nstate = `mul;
226			16'hf7f9: nstate = `sdv1;
227			16'hf7f1: nstate = `div1;
228	5	ultro	16'hafc1: nstate = `sml1;
229	2	ultro	default : nstate = `fetch;
230			`endcase`
231			`if (ID == 16'h9066) nprefx = 1'b1; else nprefx = 1'b0;`
232			`if (ID[15:8] == 8'h39 ) cmpr = 1'b1; else cmpr = 1'b0;`
233			`end`
234			`else`
235			`begin`
236	3	ultro	`nprefx = 1'b0; cmpr = 1'b0;`
237	5	ultro	if((state==`mul)&&!(ECX==32'b0)) nstate=`mul;
238			else if((state==`mul)&& (ECX==32'b0)) nstate=`mul2;
239	3	ultro	else if (state==`mul2) nstate = `fetch;
240	5	ultro	else if (state==`sml1) nstate = `sml2;
241			else if((state==`sml2)&&!(ECX==32'b0)) nstate=`sml2;
242			else if((state==`sml2)&& (ECX==32'b0)) nstate=`sml3;
243	6	ultro	else if (state==`div1) nstate = `sdv2;
244			else if (state==`sdv1) nstate = `sdv2;
245			else if((state==`sdv2) && (divF1 == 1'b0) ) nstate=`sdv2;
246			else if((state==`sdv2) && (divF1 == 1'b1) ) nstate=`sdv3;
247			else if((state==`sdv3) && (divF2 == 1'b0) ) nstate=`sdv3;
248			else if((state==`sdv3) && (divF2 == 1'b1) ) nstate=`sdv4;
249	3	ultro	else if (state==`jmp) nstate = `jmp2; else if (state==`jmp2) nstate = `fetch;
250	2	ultro	else if (state==`jne) nstate = `jne2; else if (state==`jne2) nstate = `fetch;
251			else if (state==`je ) nstate = `je2 ; else if (state==`je2 ) nstate = `fetch;
252			else if (state==`jge) nstate = `jge2; else if (state==`jge2) nstate = `fetch;
253			else if (state==`jg ) nstate = `jg2 ; else if (state==`jg2 ) nstate = `fetch;
254			else if (state==`jle) nstate = `jle2; else if (state==`jle2) nstate = `fetch;
255			else if (state==`jl ) nstate = `jl2 ; else if (state==`jl2 ) nstate = `fetch;
256	5	ultro	else if (state==`jae) nstate = `jae2; else if (state==`jae2) nstate = `fetch;
257			else if (state==`ja ) nstate = `ja2 ; else if (state==`ja2 ) nstate = `fetch;
258			else if (state==`jbe) nstate = `jbe2; else if (state==`jbe2) nstate = `fetch;
259			else if (state==`jb ) nstate = `jb2 ; else if (state==`jb2 ) nstate = `fetch;
260	2	ultro	else if (state==`imm) nstate = `imm2; else if (state==`imm2) nstate = `fetch;
261			else if (state==`lea) nstate = `lea2; else if (state==`lea2) nstate = `fetch;
262			else if (state==`call) nstate = `call2; else if (state==`call2) nstate = `fetch;
263			else if (state==`ret) nstate = `ret2; else if (state==`ret2) nstate = `fetch;
264	5	ultro	else if((state==`shift)&&!(EBX_shtr==5'b0)) nstate=`shift;
265			else if((state==`shift)&& (EBX_shtr==5'b0)) nstate=`shft2;
266	2	ultro	else nstate = `fetch;
267			`end`
268			`end`
269	5	ultro	`assign ssregsrc = regsrc;`
270			`assign ssregdest= regdest;`
271	2	ultro	`assign IA = PC ;`
272	3	ultro	assign A = (state == `call2) ? ESP : EBX ;
273	2	ultro	assign Q = (state == `call2) ? incPC : regsrc ;
274			`assign WEN = (ID[15:8]==8'h90) ? 1'b1 :`
275			(state == `call2) ? 1'b0 :
276	4	ultro	`(dest == 3'b111) ? 1'b0 : 1'b1 ;`
277	2	ultro	`assign Sregsrc = ID[8] ? { {16{regsrc[15]}} , regsrc[15:0] } :`
278			`{ {24{regsrc[7] }} , regsrc[7:0] } ;`
279			`assign Zregsrc = ID[8] ? { 16'b0 , regsrc[15:0] } :`
280			`{ 24'b0 , regsrc[7:0] } ;`
281	5	ultro	assign BEN = (state == `call2 ) ? 1'b1 : { prefx , ID[8] } ;
282	2	ultro	`assign neqF = (regsrc == regdest) ? 1'b1 : 1'b0;`
283			`assign nlF = (regsrc > regdest) ? 1'b1 : 1'b0;`
284	5	ultro	`assign ngF = ~(nlF \| neqF );// (regsrc < regdest) ? 1'b1 : 1'b0;`
285			`assign nbF = (ssregsrc > ssregdest) ? 1'b1 : 1'b0;`
286			`assign naF = ~(nbF \| neqF );// (regsrc < regdest) ? 1'b1 : 1'b0;`
287	2	ultro	`assign incPC = PC + 3'b010;`
288	5	ultro	`assign pc_jge = (eqF\|gF) ? pc_jp : incPC;`
289			`assign pc_jle = (eqF\|lF) ? pc_jp : incPC;`
290			`assign pc_jg = (gF ) ? pc_jp : incPC;`
291			`assign pc_jl = (lF ) ? pc_jp : incPC;`
292			`assign pc_jae = (eqF\|aF) ? pc_jp : incPC;`
293			`assign pc_jbe = (eqF\|bF) ? pc_jp : incPC;`
294			`assign pc_ja = (aF ) ? pc_jp : incPC;`
295			`assign pc_jb = (bF ) ? pc_jp : incPC;`
296			`assign pc_eq = (eqF ) ? pc_jp : incPC;`
297			`assign pc_neq = (eqF ) ? incPC : pc_jp;`
298	2	ultro	`assign pc_jp = incPC+{ID,EBX[15:0]};`
299	5	ultro	`assign sft_out = (src == 3'b111) ? {regdest[31],regdest[31:1]} : //sar`
300			`(src == 3'b101) ? { 1'b0,regdest[31:1]} : //shr`
301			`{regdest[30:0],1'b0 } ; //shl`
302	2	ultro	`assign adder_out= nncry + regsrc + regdest;`
303			`assign sub_out= regdest - regsrc - nncry;`
304	4	ultro	`assign nncry = (ID[12] ? cry : 1'b0);`
305	5	ultro	`assign EBX_shtr = EBX[4:0] - 1'b1;`
306	6	ultro	`assign smlEAX = EAX[31] ? ((~EAX) + 1) : EAX;`
307			`assign smlECX = ECX[31] ? ((~ECX) + 1) : ECX;`
308			`assign divF1 = ({ECX[30:0],1'b0} > EDX) ? 1'b1 : 1'b0;`
309			`assign divF2 = (EBX_shtr == 5'b00000) ? 1'b1 : 1'b0;`
310	2	ultro	`endmodule`

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