| 1 |
7 |
ultro |
module sub86( CLK, RSTN, IA, ID, A, D, Q, WEN,BEN,CE,RD );
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| 2 |
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input CLK,RSTN,CE;
|
| 3 |
2 |
ultro |
output [31:0] IA;
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| 4 |
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input [15:0] ID;
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| 5 |
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output [31:0] A;
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| 6 |
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input [31:0] D;
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| 7 |
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output [31:0] Q;
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| 8 |
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output WEN;
|
| 9 |
7 |
ultro |
output RD;
|
| 10 |
2 |
ultro |
output [1:0] BEN;
|
| 11 |
6 |
ultro |
wire nncry,neqF,ngF,nlF,naF,nbF,divF1,divF2;
|
| 12 |
2 |
ultro |
reg [31:0] EAX,EBX,ECX,EDX,EBP,ESP,PC,regsrc,regdest,alu_out;
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| 13 |
5 |
ultro |
reg [5:0] state,nstate;
|
| 14 |
2 |
ultro |
reg [2:0] src,dest;
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| 15 |
7 |
ultro |
reg RD,cry,ncry,prefx,nprefx,cmpr,eqF,gF,lF,aF,bF;
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| 16 |
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wire [31:0] pc_ja,pc_jae,pc_jb,pc_jbe,pc_jg,pc_jge,pc_jl,pc_jle,pc_eq,pc_jp,pc_neq,pc_sh;
|
| 17 |
5 |
ultro |
wire [31:0] Sregsrc,Zregsrc,incPC,sft_out,smlEAX,smlECX;
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| 18 |
3 |
ultro |
wire [32:0] adder_out,sub_out;
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| 19 |
5 |
ultro |
wire [4:0] EBX_shtr;
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| 20 |
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wire signed [31:0] ssregsrc, ssregdest;
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| 21 |
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`define fetch 6'b111111
|
| 22 |
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`define jmp 6'b000001
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| 23 |
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`define jmp2 6'b000010
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| 24 |
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`define jge 6'b000011
|
| 25 |
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`define jge2 6'b000100
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| 26 |
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`define imm 6'b000101
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| 27 |
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`define imm2 6'b000110
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| 28 |
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`define lea 6'b000111
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| 29 |
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`define lea2 6'b001000
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| 30 |
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`define call 6'b001001
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| 31 |
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`define call2 6'b001010
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| 32 |
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`define ret 6'b001011
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| 33 |
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`define ret2 6'b001100
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| 34 |
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`define shift 6'b001110
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| 35 |
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`define jg 6'b001111
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| 36 |
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`define jg2 6'b010000
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| 37 |
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`define jl 6'b010001
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| 38 |
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`define jl2 6'b010010
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| 39 |
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`define jle 6'b010011
|
| 40 |
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`define jle2 6'b010100
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| 41 |
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`define je 6'b010101
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| 42 |
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`define je2 6'b010110
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| 43 |
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`define jne 6'b010111
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| 44 |
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`define jne2 6'b011000
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| 45 |
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`define mul 6'b011001
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| 46 |
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`define mul2 6'b011010
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| 47 |
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`define shft2 6'b011011
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| 48 |
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`define jb 6'b011100
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| 49 |
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`define jb2 6'b011101
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| 50 |
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`define jbe 6'b011110
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| 51 |
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`define jbe2 6'b011111
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| 52 |
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`define ja 6'b100000
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| 53 |
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`define ja2 6'b100001
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| 54 |
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`define jae 6'b100010
|
| 55 |
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`define jae2 6'b100011
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| 56 |
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`define sml1 6'b100100
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| 57 |
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`define sml2 6'b100101
|
| 58 |
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`define sml3 6'b100110
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| 59 |
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`define sml4 6'b100111
|
| 60 |
6 |
ultro |
`define sdv1 6'b101000
|
| 61 |
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`define sdv2 6'b101001
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| 62 |
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`define sdv3 6'b101010
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| 63 |
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`define sdv4 6'b101011
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| 64 |
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`define div1 6'b101100
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| 65 |
7 |
ultro |
`define leas 6'b101101
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| 66 |
8 |
ultro |
`define calla 6'b101110
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| 67 |
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`define calla2 6'b101111
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| 68 |
5 |
ultro |
`define init 6'b000000
|
| 69 |
8 |
ultro |
|
| 70 |
5 |
ultro |
always @(posedge CLK)
|
| 71 |
7 |
ultro |
if ((CE ==1'b1) || (RSTN ==1'b0))
|
| 72 |
5 |
ultro |
begin
|
| 73 |
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case (state) // cry control
|
| 74 |
6 |
ultro |
`sml1,`sdv1: cry <= EAX[31] ^ ECX[31];
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| 75 |
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`div1 : cry <= 1'b0;
|
| 76 |
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default : cry <= ncry & RSTN;
|
| 77 |
5 |
ultro |
endcase
|
| 78 |
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prefx <= nprefx & RSTN;
|
| 79 |
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state <= nstate & {6{RSTN}};
|
| 80 |
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if (cmpr) begin eqF <= neqF & RSTN; lF <= nlF & RSTN; gF <= ngF & RSTN;
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| 81 |
7 |
ultro |
bF <= nbF & RSTN; aF <= naF & RSTN; end
|
| 82 |
5 |
ultro |
else begin eqF <= eqF & RSTN; lF <= lF & RSTN; gF <= gF & RSTN;
|
| 83 |
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bF <= bF & RSTN; aF <= aF & RSTN; end
|
| 84 |
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case(state) // EAX control
|
| 85 |
7 |
ultro |
`init : EAX <= 32'b0;
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| 86 |
5 |
ultro |
`mul,`sml2 : EAX <= {EAX[30:0],1'b0};
|
| 87 |
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`mul2 : EAX <= EBX;
|
| 88 |
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`sml1 : EAX <= smlEAX;
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| 89 |
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`sml3 : if (cry==1'b0) EAX <= EBX; else EAX <= ((~EBX) + 1'b1);
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| 90 |
6 |
ultro |
`sdv1,`div1 : EAX <= 32'b0;
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| 91 |
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`sdv3 : if (nlF==1'b0) EAX <= EAX + ( 1 << EBX_shtr); else EAX <=EAX;
|
| 92 |
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`sdv4 : if (cry==1'b1) EAX <= ((~EAX) + 1'b1); else EAX <= EAX;
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| 93 |
5 |
ultro |
default: if (dest==3'b000) EAX <= alu_out; else EAX<=EAX;
|
| 94 |
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endcase
|
| 95 |
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case(state) // EBX control
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| 96 |
7 |
ultro |
`init : EBX <= 32'b0;
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| 97 |
5 |
ultro |
`jmp , `jg, `jge , `jl, `jle, `je, `jne, `imm, `call, `jb,`jbe,`ja,`jae,
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| 98 |
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`lea : EBX<={EBX[31:16],ID[7:0],ID[15:8]};
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| 99 |
7 |
ultro |
`leas : EBX<={ {24{ID[15]}} , ID[15:8]}+EBP;
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| 100 |
5 |
ultro |
`imm2 : EBX<={ID[7:0],ID[15:8], EBX[15:0]};
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| 101 |
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`lea2 : EBX<={ID[7:0],ID[15:8], EBX[15:0]}+EBP;
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| 102 |
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`mul,`sml2 : if (ECX[0] == 1'b1) EBX <= EAX+EBX; else EBX <= EBX;
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| 103 |
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`shift : EBX<={EBX[31:5],EBX_shtr};
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| 104 |
6 |
ultro |
`sdv1 : EBX<={EAX[31],ECX[31],EBX[29:0]};
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| 105 |
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`div1 : EBX<={ 2'b00,EBX[29:0]};
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| 106 |
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`sdv2 : if (divF1==1'b0 ) EBX <= {EBX[31:5],(EBX[4:0]+1'b1)}; else EBX <= EBX;
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| 107 |
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`sdv3 : if (divF1==1'b1 ) EBX <= {EBX[31:5],EBX_shtr}; else EBX <= EBX;
|
| 108 |
7 |
ultro |
default : if (ID[15:8] == 8'hb3) EBX<= {EBX[31:24],ID[7:0]};
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| 109 |
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else if (dest==3'b011) EBX <= alu_out; else EBX <= EBX;
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| 110 |
5 |
ultro |
endcase
|
| 111 |
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case(state) // ECX control
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| 112 |
7 |
ultro |
`init : ECX <= 32'b0;
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| 113 |
5 |
ultro |
`mul,`sml2 : ECX <= {1'b0,ECX[31:1]};
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| 114 |
6 |
ultro |
`sml1,`sdv1 : ECX <= smlECX;
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| 115 |
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`div1 : ECX <= ECX;
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| 116 |
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`sdv2 : if (divF1==1'b0 ) ECX <= {ECX[30:0],1'b0}; else ECX<=ECX;
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| 117 |
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`sdv3 : if((divF1==1'b1 ) && (divF2==1'b0)) ECX <= {1'b0,ECX[31:1]}; else ECX<=ECX;
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| 118 |
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`sdv4 : if (EBX[30] == 1'b1) ECX <= ((~ECX) + 1); else ECX<=ECX;
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| 119 |
5 |
ultro |
default : if (dest==3'b001) ECX <= alu_out; else ECX<=ECX;
|
| 120 |
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endcase
|
| 121 |
6 |
ultro |
case(state) // EDX control
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| 122 |
7 |
ultro |
`init : EDX <= 32'b0;
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| 123 |
6 |
ultro |
`sdv1 : EDX <= smlEAX;
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| 124 |
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`div1 : EDX <= EAX;
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| 125 |
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`sdv3 : if (nlF==1'b0) EDX <= EDX - ECX; else EDX <= EDX;
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| 126 |
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`sdv4 : if (EBX[31] == 1'b1) EDX <= ((~EDX) + 1); else EDX<=EDX;
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| 127 |
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default : if (dest==3'b010) EDX <= alu_out; else EDX<=EDX;
|
| 128 |
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endcase
|
| 129 |
5 |
ultro |
case(state) // ESP control
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| 130 |
8 |
ultro |
`init : ESP <= 32'h01ff00;
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| 131 |
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`call,`calla: ESP <= ESP - 4'b0100;
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| 132 |
7 |
ultro |
`ret2 : ESP <= ESP + 4'b0100;
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| 133 |
5 |
ultro |
default: if (dest==3'b100) ESP <= alu_out; else ESP<=ESP;
|
| 134 |
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endcase
|
| 135 |
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if (dest==3'b101) EBP <= alu_out; else EBP<=EBP; // EBP control
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| 136 |
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case(state) // PC control
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| 137 |
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`init : PC<=32'h00;
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| 138 |
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`jae2 : PC<=pc_jae;
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| 139 |
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`jbe2 : PC<=pc_jbe;
|
| 140 |
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`ja2 : PC<=pc_ja ;
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| 141 |
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`jb2 : PC<=pc_jb ;
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| 142 |
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`jge2 : PC<=pc_jge;
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| 143 |
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`jle2 : PC<=pc_jle;
|
| 144 |
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`jg2 : PC<=pc_jg ;
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| 145 |
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`jl2 : PC<=pc_jl ;
|
| 146 |
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`je2 : PC<=pc_eq ;
|
| 147 |
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`jne2 : PC<=pc_neq;
|
| 148 |
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`jmp2,`call2 : PC<=pc_jp ;
|
| 149 |
8 |
ultro |
`calla2 : PC<=EBX;
|
| 150 |
5 |
ultro |
`ret2 : PC<=D ;
|
| 151 |
6 |
ultro |
`mul,`mul2,`sml1,`sml2,`sml3,`sml4,`sdv1,`sdv2,`sdv3,`sdv4,`div1,
|
| 152 |
5 |
ultro |
`shift : PC<=PC ;
|
| 153 |
7 |
ultro |
default : if (nstate == `shift) PC<=PC;
|
| 154 |
|
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else if (ID[15:8]==8'heb) PC <= pc_sh;
|
| 155 |
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else if((ID[15:8]==8'h75) && (eqF==1'b0)) PC <= pc_sh;
|
| 156 |
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else if((ID[15:8]==8'h74) && (eqF==1'b1)) PC <= pc_sh;
|
| 157 |
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else PC<=incPC ;
|
| 158 |
5 |
ultro |
endcase
|
| 159 |
|
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end
|
| 160 |
2 |
ultro |
// muxing for source selection, used in alu & moves
|
| 161 |
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|
always@(src,EAX,ECX,EDX,EBX,ESP,EBP,D)
|
| 162 |
|
|
case(src)
|
| 163 |
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3'b000 : regsrc = EAX;
|
| 164 |
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3'b001 : regsrc = ECX;
|
| 165 |
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3'b010 : regsrc = EDX;
|
| 166 |
|
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3'b100 : regsrc = ESP;
|
| 167 |
|
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3'b101 : regsrc = EBP;
|
| 168 |
7 |
ultro |
3'b110 : regsrc = 32'h04;
|
| 169 |
2 |
ultro |
3'b111 : regsrc = D;
|
| 170 |
|
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default: regsrc = EBX;
|
| 171 |
|
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endcase
|
| 172 |
|
|
// muxing for 2nd operand selection, used in alu only
|
| 173 |
|
|
always@(dest,EAX,ECX,EDX,EBX,ESP,EBP,D)
|
| 174 |
|
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case(dest)
|
| 175 |
|
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3'b000 : regdest = EAX;
|
| 176 |
|
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3'b001 : regdest = ECX;
|
| 177 |
|
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3'b010 : regdest = EDX;
|
| 178 |
|
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3'b100 : regdest = ESP;
|
| 179 |
|
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3'b101 : regdest = EBP;
|
| 180 |
7 |
ultro |
3'b110 : regdest = 32'h04;
|
| 181 |
2 |
ultro |
3'b111 : regdest = D ;
|
| 182 |
|
|
default: regdest = EBX;
|
| 183 |
|
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endcase
|
| 184 |
|
|
// alu
|
| 185 |
4 |
ultro |
always@(state,regdest,regsrc,ID,cry,Zregsrc,Sregsrc,sft_out,adder_out,sub_out)
|
| 186 |
|
|
if (state == `fetch )
|
| 187 |
2 |
ultro |
case (ID[15:10])
|
| 188 |
4 |
ultro |
6'b000000 : {ncry,alu_out} = adder_out ; // ADD , carry generation
|
| 189 |
|
|
6'b000010 : {ncry,alu_out} = {cry,regdest | regsrc}; // OR
|
| 190 |
|
|
6'b000100 : {ncry,alu_out} = adder_out ; // ADD , carry use
|
| 191 |
|
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6'b000110 : {ncry,alu_out} = sub_out ; // SUB , carry use
|
| 192 |
|
|
6'b001000 : {ncry,alu_out} = {cry,regdest & regsrc}; // AND
|
| 193 |
|
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6'b001010 : {ncry,alu_out} = sub_out ; // SUB , carry generation
|
| 194 |
|
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6'b001100 : {ncry,alu_out} = {cry,regdest ^ regsrc}; // XOR
|
| 195 |
|
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6'b100010 : {ncry,alu_out} = {cry, regsrc}; // MOVE
|
| 196 |
|
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6'b101101 : {ncry,alu_out} = {cry, Zregsrc}; // MOVE
|
| 197 |
|
|
6'b101111 : {ncry,alu_out} = {cry, Sregsrc}; // MOVE
|
| 198 |
5 |
ultro |
//6'b110000 : {ncry,alu_out} = {cry, sft_out[31:0]}; // SHIFT
|
| 199 |
|
|
//6'b110100 : {ncry,alu_out} = {cry, sft_out[31:0]}; // SHIFT
|
| 200 |
4 |
ultro |
default : {ncry,alu_out} = {cry,regdest }; // DO NOTHING
|
| 201 |
2 |
ultro |
endcase
|
| 202 |
5 |
ultro |
else if (state == `shift ) {ncry,alu_out} = {cry,sft_out };
|
| 203 |
4 |
ultro |
else {ncry,alu_out} = {cry,regdest };
|
| 204 |
2 |
ultro |
// Main instruction decode
|
| 205 |
6 |
ultro |
always @(ID,state,ECX,EBX_shtr,EAX,divF1,divF2)
|
| 206 |
2 |
ultro |
begin
|
| 207 |
|
|
// One cycle instructions, operand selection
|
| 208 |
5 |
ultro |
if ((state == `fetch) || (state ==`shift))
|
| 209 |
7 |
ultro |
casex ({ID[15:14],ID[13],ID[9],ID[7]})
|
| 210 |
|
|
5'b10x00 : begin RD=0; src=ID[5:3]; dest= 3'b111; end // store into ram (x89 x00)
|
| 211 |
|
|
5'b10010 : begin RD=1; src= 3'b111; dest=ID[5:3]; end // load from ram (x8b x00)
|
| 212 |
|
|
5'b10110 : begin RD=0; src= 3'b111; dest=ID[5:3]; end // load bl with immediate
|
| 213 |
|
|
5'b10x11 : begin RD=0; src=ID[2:0]; dest=ID[5:3]; end // reg2reg xfer (x8b xC0)
|
| 214 |
|
|
5'b00x11 : begin RD=0; src=ID[2:0]; dest=ID[5:3]; end // alu op
|
| 215 |
|
|
default : begin RD=0; src=ID[5:3]; dest=ID[2:0]; end // shift
|
| 216 |
2 |
ultro |
endcase
|
| 217 |
|
|
else if (state==`ret)
|
| 218 |
7 |
ultro |
begin src = 3'b011; dest = 3'b100; RD=0; end
|
| 219 |
6 |
ultro |
else if (state==`sdv3)
|
| 220 |
7 |
ultro |
begin src = 3'b001; dest = 3'b010; RD=0; end
|
| 221 |
|
|
else begin src = 3'b000; dest = 3'b000; RD=0; end
|
| 222 |
2 |
ultro |
// instructions that require more than one cycle to execute
|
| 223 |
|
|
if (state == `fetch)
|
| 224 |
|
|
begin
|
| 225 |
|
|
casex(ID)
|
| 226 |
|
|
16'h90e9: nstate = `jmp;
|
| 227 |
5 |
ultro |
16'h0f87: nstate = `ja;
|
| 228 |
|
|
16'h0f86: nstate = `jbe;
|
| 229 |
|
|
16'h0f83: nstate = `jae;
|
| 230 |
|
|
16'h0f82: nstate = `jb;
|
| 231 |
2 |
ultro |
16'h0f8f: nstate = `jg;
|
| 232 |
|
|
16'h0f8e: nstate = `jle;
|
| 233 |
|
|
16'h0f8d: nstate = `jge;
|
| 234 |
|
|
16'h0f8c: nstate = `jl;
|
| 235 |
|
|
16'h0f85: nstate = `jne;
|
| 236 |
|
|
16'h0f84: nstate = `je;
|
| 237 |
|
|
16'h90bb: nstate = `imm;
|
| 238 |
|
|
16'h8d9d: nstate = `lea;
|
| 239 |
7 |
ultro |
16'h8d5d: nstate = `leas;
|
| 240 |
2 |
ultro |
16'h90e8: nstate = `call;
|
| 241 |
|
|
16'h90c3: nstate = `ret;
|
| 242 |
3 |
ultro |
16'hc1xx: nstate = `shift;
|
| 243 |
5 |
ultro |
16'hd3xx: nstate = `shift;
|
| 244 |
6 |
ultro |
16'hf7e1: nstate = `mul;
|
| 245 |
|
|
16'hf7f9: nstate = `sdv1;
|
| 246 |
|
|
16'hf7f1: nstate = `div1;
|
| 247 |
5 |
ultro |
16'hafc1: nstate = `sml1;
|
| 248 |
8 |
ultro |
16'hffd3: nstate = `calla;
|
| 249 |
2 |
ultro |
default : nstate = `fetch;
|
| 250 |
|
|
endcase
|
| 251 |
|
|
if (ID == 16'h9066) nprefx = 1'b1; else nprefx = 1'b0;
|
| 252 |
|
|
if (ID[15:8] == 8'h39 ) cmpr = 1'b1; else cmpr = 1'b0;
|
| 253 |
|
|
end
|
| 254 |
|
|
else
|
| 255 |
|
|
begin
|
| 256 |
3 |
ultro |
nprefx = 1'b0; cmpr = 1'b0;
|
| 257 |
5 |
ultro |
if((state==`mul)&&!(ECX==32'b0)) nstate=`mul;
|
| 258 |
|
|
else if((state==`mul)&& (ECX==32'b0)) nstate=`mul2;
|
| 259 |
3 |
ultro |
else if (state==`mul2) nstate = `fetch;
|
| 260 |
5 |
ultro |
else if (state==`sml1) nstate = `sml2;
|
| 261 |
|
|
else if((state==`sml2)&&!(ECX==32'b0)) nstate=`sml2;
|
| 262 |
|
|
else if((state==`sml2)&& (ECX==32'b0)) nstate=`sml3;
|
| 263 |
6 |
ultro |
else if (state==`div1) nstate = `sdv2;
|
| 264 |
|
|
else if (state==`sdv1) nstate = `sdv2;
|
| 265 |
|
|
else if((state==`sdv2) && (divF1 == 1'b0) ) nstate=`sdv2;
|
| 266 |
|
|
else if((state==`sdv2) && (divF1 == 1'b1) ) nstate=`sdv3;
|
| 267 |
|
|
else if((state==`sdv3) && (divF2 == 1'b0) ) nstate=`sdv3;
|
| 268 |
|
|
else if((state==`sdv3) && (divF2 == 1'b1) ) nstate=`sdv4;
|
| 269 |
3 |
ultro |
else if (state==`jmp) nstate = `jmp2; else if (state==`jmp2) nstate = `fetch;
|
| 270 |
2 |
ultro |
else if (state==`jne) nstate = `jne2; else if (state==`jne2) nstate = `fetch;
|
| 271 |
|
|
else if (state==`je ) nstate = `je2 ; else if (state==`je2 ) nstate = `fetch;
|
| 272 |
|
|
else if (state==`jge) nstate = `jge2; else if (state==`jge2) nstate = `fetch;
|
| 273 |
|
|
else if (state==`jg ) nstate = `jg2 ; else if (state==`jg2 ) nstate = `fetch;
|
| 274 |
|
|
else if (state==`jle) nstate = `jle2; else if (state==`jle2) nstate = `fetch;
|
| 275 |
|
|
else if (state==`jl ) nstate = `jl2 ; else if (state==`jl2 ) nstate = `fetch;
|
| 276 |
5 |
ultro |
else if (state==`jae) nstate = `jae2; else if (state==`jae2) nstate = `fetch;
|
| 277 |
|
|
else if (state==`ja ) nstate = `ja2 ; else if (state==`ja2 ) nstate = `fetch;
|
| 278 |
|
|
else if (state==`jbe) nstate = `jbe2; else if (state==`jbe2) nstate = `fetch;
|
| 279 |
|
|
else if (state==`jb ) nstate = `jb2 ; else if (state==`jb2 ) nstate = `fetch;
|
| 280 |
2 |
ultro |
else if (state==`imm) nstate = `imm2; else if (state==`imm2) nstate = `fetch;
|
| 281 |
|
|
else if (state==`lea) nstate = `lea2; else if (state==`lea2) nstate = `fetch;
|
| 282 |
|
|
else if (state==`call) nstate = `call2; else if (state==`call2) nstate = `fetch;
|
| 283 |
8 |
ultro |
else if (state==`calla) nstate = `calla2;else if (state==`calla2)nstate = `fetch;
|
| 284 |
2 |
ultro |
else if (state==`ret) nstate = `ret2; else if (state==`ret2) nstate = `fetch;
|
| 285 |
5 |
ultro |
else if((state==`shift)&&!(EBX_shtr==5'b0)) nstate=`shift;
|
| 286 |
|
|
else if((state==`shift)&& (EBX_shtr==5'b0)) nstate=`shft2;
|
| 287 |
2 |
ultro |
else nstate = `fetch;
|
| 288 |
|
|
end
|
| 289 |
|
|
end
|
| 290 |
5 |
ultro |
assign ssregsrc = regsrc;
|
| 291 |
|
|
assign ssregdest= regdest;
|
| 292 |
2 |
ultro |
assign IA = PC ;
|
| 293 |
8 |
ultro |
assign A =((state == `call2)|(state == `calla2)) ? ESP : EBX ;
|
| 294 |
|
|
assign Q =((state == `call2)|(state == `calla2)) ? incPC : regsrc ;
|
| 295 |
7 |
ultro |
assign WEN = (CE == 1'b0) ? 1'b1 :
|
| 296 |
|
|
({ID[15:9],ID[7]}==8'h88)? 1'b0 :
|
| 297 |
8 |
ultro |
(state == `call2) ? 1'b0 :
|
| 298 |
|
|
(state == `calla2)? 1'b0 : 1'b1 ;
|
| 299 |
2 |
ultro |
assign Sregsrc = ID[8] ? { {16{regsrc[15]}} , regsrc[15:0] } :
|
| 300 |
|
|
{ {24{regsrc[7] }} , regsrc[7:0] } ;
|
| 301 |
|
|
assign Zregsrc = ID[8] ? { 16'b0 , regsrc[15:0] } :
|
| 302 |
|
|
{ 24'b0 , regsrc[7:0] } ;
|
| 303 |
5 |
ultro |
assign BEN = (state == `call2 ) ? 1'b1 : { prefx , ID[8] } ;
|
| 304 |
2 |
ultro |
assign neqF = (regsrc == regdest) ? 1'b1 : 1'b0;
|
| 305 |
8 |
ultro |
assign nbF = (regsrc > regdest) ? 1'b1 : 1'b0;
|
| 306 |
|
|
assign naF = ~(nlF | neqF );// (regsrc < regdest) ? 1'b1 : 1'b0;
|
| 307 |
|
|
assign nlF = (ssregsrc > ssregdest) ? 1'b1 : 1'b0;
|
| 308 |
|
|
assign ngF = ~(nbF | neqF );// (regsrc < regdest) ? 1'b1 : 1'b0;
|
| 309 |
2 |
ultro |
assign incPC = PC + 3'b010;
|
| 310 |
5 |
ultro |
assign pc_jge = (eqF|gF) ? pc_jp : incPC;
|
| 311 |
|
|
assign pc_jle = (eqF|lF) ? pc_jp : incPC;
|
| 312 |
|
|
assign pc_jg = (gF ) ? pc_jp : incPC;
|
| 313 |
|
|
assign pc_jl = (lF ) ? pc_jp : incPC;
|
| 314 |
|
|
assign pc_jae = (eqF|aF) ? pc_jp : incPC;
|
| 315 |
|
|
assign pc_jbe = (eqF|bF) ? pc_jp : incPC;
|
| 316 |
|
|
assign pc_ja = (aF ) ? pc_jp : incPC;
|
| 317 |
|
|
assign pc_jb = (bF ) ? pc_jp : incPC;
|
| 318 |
|
|
assign pc_eq = (eqF ) ? pc_jp : incPC;
|
| 319 |
|
|
assign pc_neq = (eqF ) ? incPC : pc_jp;
|
| 320 |
2 |
ultro |
assign pc_jp = incPC+{ID,EBX[15:0]};
|
| 321 |
7 |
ultro |
assign pc_sh = incPC + { {24{ID[7]}} , ID[7:0] };
|
| 322 |
5 |
ultro |
assign sft_out = (src == 3'b111) ? {regdest[31],regdest[31:1]} : //sar
|
| 323 |
|
|
(src == 3'b101) ? { 1'b0,regdest[31:1]} : //shr
|
| 324 |
|
|
{regdest[30:0],1'b0 } ; //shl
|
| 325 |
2 |
ultro |
assign adder_out= nncry + regsrc + regdest;
|
| 326 |
|
|
assign sub_out= regdest - regsrc - nncry;
|
| 327 |
4 |
ultro |
assign nncry = (ID[12] ? cry : 1'b0);
|
| 328 |
5 |
ultro |
assign EBX_shtr = EBX[4:0] - 1'b1;
|
| 329 |
6 |
ultro |
assign smlEAX = EAX[31] ? ((~EAX) + 1) : EAX;
|
| 330 |
|
|
assign smlECX = ECX[31] ? ((~ECX) + 1) : ECX;
|
| 331 |
|
|
assign divF1 = ({ECX[30:0],1'b0} > EDX) ? 1'b1 : 1'b0;
|
| 332 |
|
|
assign divF2 = (EBX_shtr == 5'b00000) ? 1'b1 : 1'b0;
|
| 333 |
2 |
ultro |
endmodule
|
