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module piece(/*AUTOARG*/
   // Outputs
   changed, done, curr_value, error,
   // Inputs
   clk, rst, start, clr, start_value, my_row, my_col, my_square
   );
   input clk;
   input rst;
   input start;
   input clr;
 
   output changed;
   output done;
   output error;
 
   input [8:0] start_value;
   output [8:0] curr_value;
 
   input [71:0] my_row;
   input [71:0] my_col;
   input [71:0] my_square;
 
   wire [8:0]    row2d [7:0];
   wire [8:0]    col2d [7:0];
   wire [8:0]    sqr2d [7:0];
 
   wire [8:0]    row2d_solv [7:0];
   wire [8:0]    col2d_solv [7:0];
   wire [8:0]    sqr2d_solv [7:0];
 
   reg [8:0]     r_curr_value;
   reg [8:0]     t_next_value;
   assign curr_value = r_curr_value;
 
   reg [2:0]     r_state, n_state;
   reg          r_solved, t_solved;
   reg          t_changed,r_changed;
   reg          t_error,r_error;
 
   assign done = r_solved;
   assign changed = r_changed;
   assign error = r_error;
 
   wire [8:0]    w_solved;
   wire         w_piece_solved = (w_solved != 9'd0);
   one_set s0 (r_curr_value, w_solved);
 
 
   always@(posedge clk)
     begin
        if(rst)
          begin
             r_curr_value <= 9'd0;
             r_state <= 3'd0;
             r_solved <= 1'b0;
             r_changed <= 1'b0;
             r_error <= 1'b0;
          end
        else
          begin
             r_curr_value <= clr ? 9'd0 : t_next_value;
             r_state <= clr ? 3'd0 : n_state;
             r_solved <= clr ? 1'b0 : t_solved;
             r_changed <= clr ? 1'b0 : t_changed;
             r_error <= clr ? 1'b0 : t_error;
          end
     end // always@ (posedge clk)
 
 
 
   genvar       i;
   generate
      for(i=0;i<8;i=i+1)
        begin: unflatten
           assign row2d[i] = my_row[(9*(i+1))-1:9*i];
           assign col2d[i] = my_col[(9*(i+1))-1:9*i];
           assign sqr2d[i] = my_square[(9*(i+1))-1:9*i];
        end
   endgenerate
 
   generate
      for(i=0;i<8;i=i+1)
        begin: unique_rows
           one_set rs (row2d[i], row2d_solv[i]);
           one_set cs (col2d[i], col2d_solv[i]);
           one_set ss (sqr2d[i], sqr2d_solv[i]);
        end
   endgenerate
 
   /* OR output of one_set to find cells
    * that are already set in col, grid, row */
 
 
   wire [8:0] set_row =
              row2d_solv[0] | row2d_solv[1] | row2d_solv[2] |
              row2d_solv[3] | row2d_solv[4] | row2d_solv[5] |
              row2d_solv[6] | row2d_solv[7];
 
   wire [8:0] set_col =
              col2d_solv[0] | col2d_solv[1] | col2d_solv[2] |
              col2d_solv[3] | col2d_solv[4] | col2d_solv[5] |
              col2d_solv[6] | col2d_solv[7];
 
   wire [8:0] set_sqr =
              sqr2d_solv[0] | sqr2d_solv[1] | sqr2d_solv[2] |
              sqr2d_solv[3] | sqr2d_solv[4] | sqr2d_solv[5] |
              sqr2d_solv[6] | sqr2d_solv[7];
 
 
   integer    ii;
 
   always@(posedge clk)
     begin
        if(rst==1'b0)
          begin
             for(ii=0;ii<8;ii=ii+1)
               begin
                  if(row2d_solv[ii] === 9'dx)
                    begin
                       $display("row %d", ii);
                       $stop();
                    end
               end
          end
        //$display("row2d_solv[0] = %x", row2d_solv[0]);
     end
 
 
 
   /* finding unique */
   wire [8:0] row_or =
              row2d[0] | row2d[1] | row2d[2] |
              row2d[3] | row2d[4] | row2d[5] |
              row2d[6] | row2d[7] ;
 
   wire [8:0] col_or =
              col2d[0] | col2d[1] | col2d[2] |
              col2d[3] | col2d[4] | col2d[5] |
              col2d[6] | col2d[7] ;
 
   wire [8:0] sqr_or =
              sqr2d[0] | sqr2d[1] | sqr2d[2] |
              sqr2d[3] | sqr2d[4] | sqr2d[5] |
              sqr2d[6] | sqr2d[7] ;
 
 
 
   wire [8:0] row_nor = ~row_or;
   wire [8:0] col_nor = ~col_or;
   wire [8:0] sqr_nor = ~sqr_or;
 
   wire [8:0] row_singleton;
   wire [8:0] col_singleton;
   wire [8:0] sqr_singleton;
 
   one_set s1 (r_curr_value & row_nor, row_singleton);
   one_set s2 (r_curr_value & col_nor, col_singleton);
   one_set s3 (r_curr_value & sqr_nor, sqr_singleton);
 
   /* these are the values of the set rows, columns, and
    * squares */
 
   wire [8:0] not_poss = set_row | set_col | set_sqr;
 
   wire [8:0] new_poss = r_curr_value & (~not_poss);
   wire       w_piece_zero = (r_curr_value == 9'd0);
 
   always@(*)
     begin
        t_next_value = r_curr_value;
        n_state = r_state;
        t_solved = r_solved;
        t_changed = 1'b0;
        t_error = r_error;
 
        case(r_state)
          3'd0:
            begin
               if(start)
                 begin
                    t_next_value = start_value;
                    n_state = 3'd1;
                    t_changed = 1'b1;
                    t_error = 1'b0;
                 end
            end
          3'd1:
            begin
               if(w_piece_solved | w_piece_zero)
                 begin
                    t_solved = 1'b1;
                    n_state = 3'd7;
                    t_changed = 1'b1;
                    t_error = w_piece_zero;
                 end
               else
                 begin
                    t_changed = (new_poss != r_curr_value);
                    t_next_value = new_poss;
                    n_state = 3'd2;
                 end
            end // case: 3'd1
          3'd2:
            begin
               if(w_piece_solved | w_piece_zero)
                 begin
                    t_solved = 1'b1;
                    n_state = 3'd7;
                    t_error = w_piece_zero;
                 end
               else
                 begin
                    if(row_singleton != 9'd0)
                      begin
                         //$display("used row singleton");
                         t_next_value = row_singleton;
                         t_changed = 1'b1;
                         t_solved = 1'b1;
                         n_state = 3'd7;
                      end
                    else if(col_singleton != 9'd0)
                      begin
                         //$display("used col singleton");
                         t_next_value = col_singleton;
                         t_changed = 1'b1;
                         t_solved = 1'b1;
                         n_state = 3'd7;
                      end
                    else if(sqr_singleton != 9'd0)
                      begin
                         //$display("used sqr singleton");
                         t_next_value = sqr_singleton;
                         t_changed = 1'b1;
                         t_solved = 1'b1;
                         n_state = 3'd7;
                      end
                    else
                      begin
                         n_state = 3'd1;
                      end
                 end
            end
          3'd7:
            begin
               t_solved = 1'b1;
               n_state = 3'd7;
            end
 
        endcase // case (r_state)
     end
 
 
 
endmodule // piece
 
module one_set(input [8:0] in, output [8:0] out);
   wire is_pow2 =
        (in == 9'd1) | (in == 9'd2) | (in == 9'd4) |
        (in == 9'd8) | (in == 9'd16)  | (in == 9'd32) |
        (in == 9'd64) | (in == 9'd128) | (in == 9'd256);
 
   assign out = {9{is_pow2}} & in;
endmodule // one_set
 
module two_set(input [8:0] in, output [8:0] out);
   wire [3:0] c;
   one_count9 oc (.in(in), .out(c));
   assign out = (c==4'd2) ? in : 9'd0;
endmodule
 
module ones_count81(input [80:0] in, output [6:0] out);
   wire [83:0] w_in = {3'd0, in};
   wire [2:0]  ps [20:0];
 
   integer     x;
   reg [6:0]   t_sum;
   genvar      i;
   generate
      for(i=0;i<21;i=i+1)
        begin : builders
           one_count4 os (w_in[(4*(i+1)) - 1 : 4*i], ps[i]);
        end
   endgenerate
   always@(*)
                       begin
                          t_sum = 7'd0;
                          for(x = 0; x < 21; x=x+1)
                            begin
                               t_sum = t_sum + {3'd0, ps[x]};
                            end
                       end
   assign out = t_sum;
 
endmodule // ones_count81
 
module one_count4(input [3:0] in, output [2:0] out);
   assign out =
                (in == 4'b0000) ? 3'd0 :
                (in == 4'b0001) ? 3'd1 :
                (in == 4'b0010) ? 3'd1 :
                (in == 4'b0011) ? 3'd2 :
                (in == 4'b0100) ? 3'd1 :
                (in == 4'b0101) ? 3'd2 :
                (in == 4'b0110) ? 3'd2 :
                (in == 4'b0111) ? 3'd3 :
                (in == 4'b1000) ? 3'd1 :
                (in == 4'b1001) ? 3'd2 :
                (in == 4'b1010) ? 3'd2 :
                (in == 4'b1011) ? 3'd3 :
                (in == 4'b1100) ? 3'd2 :
                (in == 4'b1101) ? 3'd3 :
                (in == 4'b1110) ? 3'd3 :
                3'd4;
endmodule // one_count4
 
module one_count9(input [8:0] in, output [3:0] out);
 
   wire [2:0] o0, o1;
 
   one_count4 m0 (in[3:0], o0);
   one_count4 m1 (in[7:4], o1);
 
   assign out = {3'd0,in[8]} + {1'd0,o1} + {1'd0,o0};
 
endmodule

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[/] [sudoku/] [branches/] [zynq/] [rtl/] [piece.v] - Blame information for rev 6

Line No.	Rev	Author	Line
1	6	dsheffie	`module piece(/AUTOARG/`
2			`// Outputs`
3			`changed, done, curr_value, error,`
4			`// Inputs`
5			`clk, rst, start, clr, start_value, my_row, my_col, my_square`
6			`);`
7			`input clk;`
8			`input rst;`
9			`input start;`
10			`input clr;`
11
12			`output changed;`
13			`output done;`
14			`output error;`
15
16			`input [8:0] start_value;`
17			`output [8:0] curr_value;`
18
19			`input [71:0] my_row;`
20			`input [71:0] my_col;`
21			`input [71:0] my_square;`
22
23			`wire [8:0] row2d [7:0];`
24			`wire [8:0] col2d [7:0];`
25			`wire [8:0] sqr2d [7:0];`
26
27			`wire [8:0] row2d_solv [7:0];`
28			`wire [8:0] col2d_solv [7:0];`
29			`wire [8:0] sqr2d_solv [7:0];`
30
31			`reg [8:0] r_curr_value;`
32			`reg [8:0] t_next_value;`
33			`assign curr_value = r_curr_value;`
34
35			`reg [2:0] r_state, n_state;`
36			`reg r_solved, t_solved;`
37			`reg t_changed,r_changed;`
38			`reg t_error,r_error;`
39
40			`assign done = r_solved;`
41			`assign changed = r_changed;`
42			`assign error = r_error;`
43
44			`wire [8:0] w_solved;`
45			`wire w_piece_solved = (w_solved != 9'd0);`
46			`one_set s0 (r_curr_value, w_solved);`
47
48
49			`always@(posedge clk)`
50			`begin`
51			`if(rst)`
52			`begin`
53			`r_curr_value <= 9'd0;`
54			`r_state <= 3'd0;`
55			`r_solved <= 1'b0;`
56			`r_changed <= 1'b0;`
57			`r_error <= 1'b0;`
58			`end`
59			`else`
60			`begin`
61			`r_curr_value <= clr ? 9'd0 : t_next_value;`
62			`r_state <= clr ? 3'd0 : n_state;`
63			`r_solved <= clr ? 1'b0 : t_solved;`
64			`r_changed <= clr ? 1'b0 : t_changed;`
65			`r_error <= clr ? 1'b0 : t_error;`
66			`end`
67			`end // always@ (posedge clk)`
68
69
70
71			`genvar i;`
72			`generate`
73			`for(i=0;i<8;i=i+1)`
74			`begin: unflatten`
75			`assign row2d[i] = my_row[(9(i+1))-1:9i];`
76			`assign col2d[i] = my_col[(9(i+1))-1:9i];`
77			`assign sqr2d[i] = my_square[(9(i+1))-1:9i];`
78			`end`
79			`endgenerate`
80
81			`generate`
82			`for(i=0;i<8;i=i+1)`
83			`begin: unique_rows`
84			`one_set rs (row2d[i], row2d_solv[i]);`
85			`one_set cs (col2d[i], col2d_solv[i]);`
86			`one_set ss (sqr2d[i], sqr2d_solv[i]);`
87			`end`
88			`endgenerate`
89
90			`/* OR output of one_set to find cells`
91			`* that are already set in col, grid, row */`
92
93
94			`wire [8:0] set_row =`
95			`row2d_solv[0] \| row2d_solv[1] \| row2d_solv[2] \|`
96			`row2d_solv[3] \| row2d_solv[4] \| row2d_solv[5] \|`
97			`row2d_solv[6] \| row2d_solv[7];`
98
99			`wire [8:0] set_col =`
100			`col2d_solv[0] \| col2d_solv[1] \| col2d_solv[2] \|`
101			`col2d_solv[3] \| col2d_solv[4] \| col2d_solv[5] \|`
102			`col2d_solv[6] \| col2d_solv[7];`
103
104			`wire [8:0] set_sqr =`
105			`sqr2d_solv[0] \| sqr2d_solv[1] \| sqr2d_solv[2] \|`
106			`sqr2d_solv[3] \| sqr2d_solv[4] \| sqr2d_solv[5] \|`
107			`sqr2d_solv[6] \| sqr2d_solv[7];`
108
109
110			`integer ii;`
111
112			`always@(posedge clk)`
113			`begin`
114			`if(rst==1'b0)`
115			`begin`
116			`for(ii=0;ii<8;ii=ii+1)`
117			`begin`
118			`if(row2d_solv[ii] === 9'dx)`
119			`begin`
120			`$display("row %d", ii);`
121			`$stop();`
122			`end`
123			`end`
124			`end`
125			`//$display("row2d_solv[0] = %x", row2d_solv[0]);`
126			`end`
127
128
129
130			`/* finding unique */`
131			`wire [8:0] row_or =`
132			`row2d[0] \| row2d[1] \| row2d[2] \|`
133			`row2d[3] \| row2d[4] \| row2d[5] \|`
134			`row2d[6] \| row2d[7] ;`
135
136			`wire [8:0] col_or =`
137			`col2d[0] \| col2d[1] \| col2d[2] \|`
138			`col2d[3] \| col2d[4] \| col2d[5] \|`
139			`col2d[6] \| col2d[7] ;`
140
141			`wire [8:0] sqr_or =`
142			`sqr2d[0] \| sqr2d[1] \| sqr2d[2] \|`
143			`sqr2d[3] \| sqr2d[4] \| sqr2d[5] \|`
144			`sqr2d[6] \| sqr2d[7] ;`
145
146
147
148			`wire [8:0] row_nor = ~row_or;`
149			`wire [8:0] col_nor = ~col_or;`
150			`wire [8:0] sqr_nor = ~sqr_or;`
151
152			`wire [8:0] row_singleton;`
153			`wire [8:0] col_singleton;`
154			`wire [8:0] sqr_singleton;`
155
156			`one_set s1 (r_curr_value & row_nor, row_singleton);`
157			`one_set s2 (r_curr_value & col_nor, col_singleton);`
158			`one_set s3 (r_curr_value & sqr_nor, sqr_singleton);`
159
160			`/* these are the values of the set rows, columns, and`
161			`* squares */`
162
163			`wire [8:0] not_poss = set_row \| set_col \| set_sqr;`
164
165			`wire [8:0] new_poss = r_curr_value & (~not_poss);`
166			`wire w_piece_zero = (r_curr_value == 9'd0);`
167
168			`always@(*)`
169			`begin`
170			`t_next_value = r_curr_value;`
171			`n_state = r_state;`
172			`t_solved = r_solved;`
173			`t_changed = 1'b0;`
174			`t_error = r_error;`
175
176			`case(r_state)`
177			`3'd0:`
178			`begin`
179			`if(start)`
180			`begin`
181			`t_next_value = start_value;`
182			`n_state = 3'd1;`
183			`t_changed = 1'b1;`
184			`t_error = 1'b0;`
185			`end`
186			`end`
187			`3'd1:`
188			`begin`
189			`if(w_piece_solved \| w_piece_zero)`
190			`begin`
191			`t_solved = 1'b1;`
192			`n_state = 3'd7;`
193			`t_changed = 1'b1;`
194			`t_error = w_piece_zero;`
195			`end`
196			`else`
197			`begin`
198			`t_changed = (new_poss != r_curr_value);`
199			`t_next_value = new_poss;`
200			`n_state = 3'd2;`
201			`end`
202			`end // case: 3'd1`
203			`3'd2:`
204			`begin`
205			`if(w_piece_solved \| w_piece_zero)`
206			`begin`
207			`t_solved = 1'b1;`
208			`n_state = 3'd7;`
209			`t_error = w_piece_zero;`
210			`end`
211			`else`
212			`begin`
213			`if(row_singleton != 9'd0)`
214			`begin`
215			`//$display("used row singleton");`
216			`t_next_value = row_singleton;`
217			`t_changed = 1'b1;`
218			`t_solved = 1'b1;`
219			`n_state = 3'd7;`
220			`end`
221			`else if(col_singleton != 9'd0)`
222			`begin`
223			`//$display("used col singleton");`
224			`t_next_value = col_singleton;`
225			`t_changed = 1'b1;`
226			`t_solved = 1'b1;`
227			`n_state = 3'd7;`
228			`end`
229			`else if(sqr_singleton != 9'd0)`
230			`begin`
231			`//$display("used sqr singleton");`
232			`t_next_value = sqr_singleton;`
233			`t_changed = 1'b1;`
234			`t_solved = 1'b1;`
235			`n_state = 3'd7;`
236			`end`
237			`else`
238			`begin`
239			`n_state = 3'd1;`
240			`end`
241			`end`
242			`end`
243			`3'd7:`
244			`begin`
245			`t_solved = 1'b1;`
246			`n_state = 3'd7;`
247			`end`
248
249			`endcase // case (r_state)`
250			`end`
251
252
253
254			`endmodule // piece`
255
256			`module one_set(input [8:0] in, output [8:0] out);`
257			`wire is_pow2 =`
258			`(in == 9'd1) \| (in == 9'd2) \| (in == 9'd4) \|`
259			`(in == 9'd8) \| (in == 9'd16) \| (in == 9'd32) \|`
260			`(in == 9'd64) \| (in == 9'd128) \| (in == 9'd256);`
261
262			`assign out = {9{is_pow2}} & in;`
263			`endmodule // one_set`
264
265			`module two_set(input [8:0] in, output [8:0] out);`
266			`wire [3:0] c;`
267			`one_count9 oc (.in(in), .out(c));`
268			`assign out = (c==4'd2) ? in : 9'd0;`
269			`endmodule`
270
271			`module ones_count81(input [80:0] in, output [6:0] out);`
272			`wire [83:0] w_in = {3'd0, in};`
273			`wire [2:0] ps [20:0];`
274
275			`integer x;`
276			`reg [6:0] t_sum;`
277			`genvar i;`
278			`generate`
279			`for(i=0;i<21;i=i+1)`
280			`begin : builders`
281			`one_count4 os (w_in[(4(i+1)) - 1 : 4i], ps[i]);`
282			`end`
283			`endgenerate`
284			`always@(*)`
285			`begin`
286			`t_sum = 7'd0;`
287			`for(x = 0; x < 21; x=x+1)`
288			`begin`
289			`t_sum = t_sum + {3'd0, ps[x]};`
290			`end`
291			`end`
292			`assign out = t_sum;`
293
294			`endmodule // ones_count81`
295
296			`module one_count4(input [3:0] in, output [2:0] out);`
297			`assign out =`
298			`(in == 4'b0000) ? 3'd0 :`
299			`(in == 4'b0001) ? 3'd1 :`
300			`(in == 4'b0010) ? 3'd1 :`
301			`(in == 4'b0011) ? 3'd2 :`
302			`(in == 4'b0100) ? 3'd1 :`
303			`(in == 4'b0101) ? 3'd2 :`
304			`(in == 4'b0110) ? 3'd2 :`
305			`(in == 4'b0111) ? 3'd3 :`
306			`(in == 4'b1000) ? 3'd1 :`
307			`(in == 4'b1001) ? 3'd2 :`
308			`(in == 4'b1010) ? 3'd2 :`
309			`(in == 4'b1011) ? 3'd3 :`
310			`(in == 4'b1100) ? 3'd2 :`
311			`(in == 4'b1101) ? 3'd3 :`
312			`(in == 4'b1110) ? 3'd3 :`
313			`3'd4;`
314			`endmodule // one_count4`
315
316			`module one_count9(input [8:0] in, output [3:0] out);`
317
318			`wire [2:0] o0, o1;`
319
320			`one_count4 m0 (in[3:0], o0);`
321			`one_count4 m1 (in[7:4], o1);`
322
323			`assign out = {3'd0,in[8]} + {1'd0,o1} + {1'd0,o0};`
324
325			`endmodule`