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//----------------------------------------------------------------------------

// user_logic.v - module

//----------------------------------------------------------------------------

//

// ***************************************************************************

// ** Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.            **

// **                                                                       **

// ** Xilinx, Inc.                                                          **

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// ** SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,        **

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// ***************************************************************************

//

//----------------------------------------------------------------------------

// Filename:          user_logic.v

// Version:           1.00.a

// Description:       User logic module.

// Date:              Wed Dec 12 22:58:12 2012 (by Create and Import Peripheral Wizard)

// Verilog Standard:  Verilog-2001

//----------------------------------------------------------------------------

// Naming Conventions:

//   active low signals:                    "*_n"

//   clock signals:                         "clk", "clk_div#", "clk_#x"

//   reset signals:                         "rst", "rst_n"

//   generics:                              "C_*"

//   user defined types:                    "*_TYPE"

//   state machine next state:              "*_ns"

//   state machine current state:           "*_cs"

//   combinatorial signals:                 "*_com"

//   pipelined or register delay signals:   "*_d#"

//   counter signals:                       "*cnt*"

//   clock enable signals:                  "*_ce"

//   internal version of output port:       "*_i"

//   device pins:                           "*_pin"

//   ports:                                 "- Names begin with Uppercase"

//   processes:                             "*_PROCESS"

//   component instantiations:              "<ENTITY_>I_<#|FUNC>"

//----------------------------------------------------------------------------

`uselib lib=unisims_ver

`uselib lib=proc_common_v3_00_a

module user_logic

(

  // -- ADD USER PORTS BELOW THIS LINE ---------------

  // --USER ports added here 

  // -- ADD USER PORTS ABOVE THIS LINE ---------------

  // -- DO NOT EDIT BELOW THIS LINE ------------------

  // -- Bus protocol ports, do not add to or delete 

  Bus2IP_Clk,                     // Bus to IP clock

  Bus2IP_Resetn,                  // Bus to IP reset

  Bus2IP_Data,                    // Bus to IP data bus

  Bus2IP_BE,                      // Bus to IP byte enables

  Bus2IP_RdCE,                    // Bus to IP read chip enable

  Bus2IP_WrCE,                    // Bus to IP write chip enable

  IP2Bus_Data,                    // IP to Bus data bus

  IP2Bus_RdAck,                   // IP to Bus read transfer acknowledgement

  IP2Bus_WrAck,                   // IP to Bus write transfer acknowledgement

  IP2Bus_Error                    // IP to Bus error response

  // -- DO NOT EDIT ABOVE THIS LINE ------------------

); // user_logic

// -- ADD USER PARAMETERS BELOW THIS LINE ------------

// --USER parameters added here 

// -- ADD USER PARAMETERS ABOVE THIS LINE ------------

// -- DO NOT EDIT BELOW THIS LINE --------------------

// -- Bus protocol parameters, do not add to or delete

parameter C_NUM_REG                      = 8;

parameter C_SLV_DWIDTH                   = 32;

// -- DO NOT EDIT ABOVE THIS LINE --------------------

// -- ADD USER PORTS BELOW THIS LINE -----------------

// --USER ports added here 

// -- ADD USER PORTS ABOVE THIS LINE -----------------

// -- DO NOT EDIT BELOW THIS LINE --------------------

// -- Bus protocol ports, do not add to or delete

input                                     Bus2IP_Clk;

input                                     Bus2IP_Resetn;

input      [C_SLV_DWIDTH-1 : 0]           Bus2IP_Data;

input      [C_SLV_DWIDTH/8-1 : 0]         Bus2IP_BE;

input      [C_NUM_REG-1 : 0]              Bus2IP_RdCE;

input      [C_NUM_REG-1 : 0]              Bus2IP_WrCE;

output     [C_SLV_DWIDTH-1 : 0]           IP2Bus_Data;

output                                    IP2Bus_RdAck;

output                                    IP2Bus_WrAck;

output                                    IP2Bus_Error;

// -- DO NOT EDIT ABOVE THIS LINE --------------------

  wire write_ready;

  wire read_ready;

  assign IP2Bus_WrAck = write_ready && Bus2IP_WrCE != 0;

  assign IP2Bus_RdAck = read_ready && Bus2IP_RdCE != 0;

  assign IP2Bus_Error = 0;

  Slave s

  (

    .clk(Bus2IP_Clk),

    .reset(!Bus2IP_Resetn),

    .io_write_valid(Bus2IP_WrCE),

    .io_write_ready(write_ready),

    .io_write_data(Bus2IP_Data),

    .io_write_byteEnable(Bus2IP_BE),

    .io_read_valid(Bus2IP_RdCE),

    .io_read_ready(read_ready),

    .io_read_data(IP2Bus_Data)

  );

endmodule

`include "Slave.v"