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[/] [sudoku/] [trunk/] [parameterized_rtl/] [minPiece.v] - Blame information for rev 7

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1 7 dsheffie 
module minPiece(/*AUTOARG*/
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   // Outputs
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   minPoss, minIdx,
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   // Inputs
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   clk, rst, inGrid
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   );
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   function integer my_clog2;
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   input integer value;
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   begin
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      value = value-1;
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      for (my_clog2=0; value>0; my_clog2=my_clog2+1)
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        value = value>>1;
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   end
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   endfunction
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   parameter DIM = 3;
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   localparam DIM_S = DIM*DIM;
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   localparam DIM_Q = DIM_S*DIM_S;
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   localparam LG_DIM_S = my_clog2(DIM_S);
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   localparam LG_DIM_Q = my_clog2(DIM_Q);
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   localparam PAD_WIDTH = (1<<LG_DIM_Q);
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   localparam PAD = PAD_WIDTH - DIM_Q;
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   input clk;
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   input rst;
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   input [(DIM_S*DIM_S*DIM_S -1):0] inGrid;
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   output [(LG_DIM_S-1):0]           minPoss;
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   output [(LG_DIM_Q-1):0]           minIdx;
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   reg [(LG_DIM_S-1):0]      r_minPoss;
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   reg [(LG_DIM_Q-1):0]      r_minIdx;
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   assign minPoss = r_minPoss;
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   assign minIdx = r_minIdx;
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   wire [(DIM_S-1):0] grid2d [(DIM_Q-1):0];
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   wire [(LG_DIM_S-1):0] w_reduce_poss [(LG_DIM_Q):0][(PAD_WIDTH-1):0];
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   wire [(LG_DIM_Q-1):0] w_reduce_indices [(LG_DIM_Q):0][(PAD_WIDTH-1):0];
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   genvar        i,j;
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   /* unflatten */
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   generate
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      for(i=0;i<PAD_WIDTH;i=i+1)
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        begin: unflatten
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           if(i < DIM_Q)
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             begin
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                assign grid2d[i] = inGrid[(DIM_S*(i+1))-1:DIM_S*i];
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                countPoss #(.DIM(DIM)) cP1 (.clk(clk), .rst(rst), .in(grid2d[i]), .out(w_reduce_poss[0][i]));
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                assign w_reduce_indices[0][i] = i;
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             end
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           else
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             begin
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                assign w_reduce_poss[0][i] = ~0;
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                assign w_reduce_indices[0][i] = i;
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             end // else: !if(i < DIM_Q)
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           //assign w_reduce_indices[0][i] = i;
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        end
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   endgenerate
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   localparam RIDX=LG_DIM_Q;
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   generate
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      for(i=1;i<(LG_DIM_Q+1);i=i+1)
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        begin: level_reduce
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           for(j=0;j<(1<<(LG_DIM_Q-i));j=j+1)
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             begin: elem_reduce
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                cmpPiece #(.DIM(DIM)) cmpr
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                 (
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                  .outPoss(w_reduce_poss[i][j]),
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                  .outIdx(w_reduce_indices[i][j]),
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                  .inPoss_0(w_reduce_poss[i-1][2*j]),
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                  .inIdx_0(w_reduce_indices[i-1][2*j]),
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                  .inPoss_1(w_reduce_poss[i-1][2*j+1]),
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                  .inIdx_1(w_reduce_indices[i-1][2*j+1])
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                  );
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             end
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        end
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   endgenerate
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   always@(posedge clk)
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     begin
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        if(rst)
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          begin
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             r_minIdx <= 0;
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             r_minPoss <= (~0);
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          end
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        else
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          begin
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             r_minIdx <= w_reduce_indices[RIDX][0];
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             r_minPoss <= w_reduce_poss[RIDX][0];
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          end
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     end // always@ (posedge clk)
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endmodule // minPiece
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module cmpPiece(/*AUTOARG*/
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   // Outputs
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   outPoss, outIdx,
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   // Inputs
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   inPoss_0, inIdx_0, inPoss_1, inIdx_1
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   );
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   function integer my_clog2;
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      input integer value;
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      begin
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         value = value-1;
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         for (my_clog2=0; value>0; my_clog2=my_clog2+1)
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           value = value>>1;
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      end
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   endfunction // for
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   parameter DIM=3;
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   localparam DIM_S = DIM*DIM;
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   localparam DIM_Q = DIM_S*DIM_S;
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   localparam LG_DIM_S = my_clog2(DIM_S);
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   localparam LG_DIM_Q = my_clog2(DIM_Q);
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   input [(LG_DIM_S-1):0] inPoss_0;
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   input [(LG_DIM_Q-1):0] inIdx_0;
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   input [(LG_DIM_S-1):0] inPoss_1;
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   input [(LG_DIM_Q-1):0] inIdx_1;
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   output [(LG_DIM_S-1):0] outPoss;
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   output [(LG_DIM_Q-1):0] outIdx;
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   wire         w_cmp = (inPoss_0 < inPoss_1);
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   assign outPoss = w_cmp ? inPoss_0 : inPoss_1;
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   assign outIdx = w_cmp ? inIdx_0 : inIdx_1;
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endmodule // cmpPiece
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module countPoss(clk,rst,in,out);
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   function integer my_clog2;
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      input integer value;
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      begin
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         value = value-1;
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         for (my_clog2=0; value>0; my_clog2=my_clog2+1)
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           value = value>>1;
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      end
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   endfunction // for
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   parameter DIM=3;
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   localparam DIM_S = DIM*DIM;
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   localparam DIM_Q = DIM_S*DIM_S;
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   localparam LG_DIM_S = my_clog2(DIM_S);
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   localparam LG_DIM_Q = my_clog2(DIM_Q);
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   localparam PAD = (1<<LG_DIM_S) - DIM_S;
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   localparam PAD_WIDTH = (1<<LG_DIM_S);
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162 
   input [(DIM_S-1):0] in;
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   input               clk;
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   input               rst;
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166 
   output [(LG_DIM_S-1):0] out;
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   reg [(LG_DIM_S-1):0]    r_out;
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   assign out = r_out;
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170 
 
171 
   wire [(PAD_WIDTH-1):0]  w_pad_in;
172 
   generate
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      begin: padding
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         if(PAD > 0)
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           begin
176 
              assign w_pad_in = { {PAD{1'b0}}, in};
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           end
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         else
179 
           begin
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              assign w_pad_in = in;
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           end
182 
      end
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   endgenerate
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185 
   wire [(LG_DIM_S-1):0]   w_cnt;
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187 
   ones_count #(.LG_IN_WIDTH(LG_DIM_S)) c0 (.in(w_pad_in), .out(w_cnt));
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   wire [(LG_DIM_S-1):0]   w_out = (w_cnt == 'd1) ? ~0 : w_cnt;
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191 
   always@(posedge clk)
192 
     begin
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        r_out <= rst ? ~0 : w_out;
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     end
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endmodule // countPoss
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