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[/] [suslik/] [trunk/] [native asm/] [testmem6.s] - Blame information for rev 4

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lc 0,r0 ;always zero
lc 0,r2 ;$monitor-ed register; small numbers=pass test, numbers>0x1000=error
 
; test #9 - write back test
 
lc cl3,r3       ; adress
lc 10,r4        ; loop counter
lc 1000,r5      ; value to store
loop9_w:
stl r3,0,r5
addi r5,11,r5
addi r3,0x1000,r3
subi r4,1,r4
cjuge r4,r0,loop9_w
lc cl3,r3       ; adress
lc 10,r4        ; loop counter
lc 1000,r5      ; value to compare
                ; r6 - load value
loop9_r:
ldl r3,0,r6
cjne r6,r5,error9_1
addi r5,11,r5
addi r3,0x1000,r3
subi r4,1,r4
cjuge r4,r0,loop9_r
cjeq r0,r0,skiperr9
error9_1:
lc 0x9000,r2
cjeq r0,r0,error9_1
skiperr9:
 
lc 9,r2
 
; test #10 - more complete write back test
 
lc cl3,r3       ; adress
lc 10,r4        ; loop counter
lc 1000,r5      ; value to store
loop10_w_32:
lc 32,r7        ; inner loop counter
and r3,r3,r8    ; inner loop pointer
loop10_w_1:
stw r8,0,r5
addi r5,11,r5
addi r8,2,r8
subi r7,1,r7
cjuge r7,r0,loop10_w_1
addi r3,0x1000,r3
subi r4,1,r4
cjuge r4,r0,loop10_w_32
 
lc cl3,r3       ; adress
lc 10,r4        ; loop counter
lc 1000,r5      ; value to compare
                ; r6 - load value
loop10_r_32:
lc 32,r7        ; inner loop counter
and r3,r3,r8    ; inner loop pointer
loop10_r_1:
ldw r8,0,r6
cjne r6,r5,error10_1
addi r5,11,r5
addi r8,2,r8
subi r7,1,r7
cjuge r7,r0,loop10_r_1
addi r3,0x1000,r3
subi r4,1,r4
cjuge r4,r0,loop10_r_32
cjeq r0,r0,skiperr10
error10_1:
lc 0xa000,r2
cjeq r0,r0,error10_1
skiperr10:
 
lc 10,r2
 
 
; test #1
lc cl1,r3 ;data base register
lc 0,r4 ;effective address
lc 0x1, r5 ; value to compare
; load data into r6
lc 8,r7 ; x1 loop counter
lc 8,r8 ; x8 loop counter
 
and r3,r3,r4
 
loop1_8:
lc 8,r7
loop1_1:
ldb r4,0,r6
cjne r6,r5,error1_1
addi r4,1,r4
addi r5,1,r5
subi r7,1,r7
cjuge r7,r0,loop1_1
addi r5,8,r5
subi r8,1,r8
cjuge r8,r0,loop1_8
cjeq r0,r0,skiperr1
error1_1:
lc 0x1000,r1 ;error code
or r1,r5,r2
cjeq r0,r0, error1_1
skiperr1: ;test 1 passed
lc 1,r2
 
; test #2
lc cl1,r3 ;data base register
lc 0,r4 ;effective address
lc 0x0201, r5 ; value to compare
; load data into r6
lc 4,r7 ; x2 loop counter
lc 8,r8 ; x8 loop counter
 
and r3,r3,r4
 
loop2_8:
lc 4,r7
loop2_2:
ldw r4,0,r6
cjne r6,r5,error2_1
addi r4,2,r4
addi r5,0x0202,r5
subi r7,1,r7
cjuge r7,r0,loop2_2
addi r5,0x0808,r5
subi r8,1,r8
cjuge r8,r0,loop2_8
cjeq r0,r0,skiperr2
error2_1:
lc 0x2000,r1 ;error code
andi r5,0xff,r5
or r1,r5,r2
cjeq r0,r0, error2_1
skiperr2: ;test 2 passed
 
lc 2,r2
 
; test #3 read long
lc cl1,r3 ;data base register
lc 0,r4 ;effective address
lc 0x0201, r5 ; value to compare
lch r5,0x0403,r5
; load data into r6
lc 2,r7 ; x4 loop counter
lc 8,r8 ; x8 loop counter
lc 0x0404,r9 ; value to add to r5
lch r9,0x0404,r9
lc 0x0808,r10 ; add to r5 on loop3_8
lch r10,0x0808,r10
 
and r3,r3,r4
 
loop3_8:
lc 2,r7
loop3_4:
ldl r4,0,r6
cjne r6,r5,error3_1
addi r4,4,r4
add r5,r9,r5
subi r7,1,r7
cjuge r7,r0,loop3_4
add r5,r10,r5
subi r8,1,r8
cjuge r8,r0,loop3_8
cjeq r0,r0,skiperr3
error3_1:
lc 0x3000,r1 ;error code
andi r5,0xff,r5
or r1,r5,r2
cjeq r0,r0, error3_1
skiperr3: ;test 3 passed
 
lc 3,r2
 
;test #4 - write byte
 
lc cl1,r3 ; base of data
lc cl1,r4 ;adress of write
lc 64,r5 ; write loop counter
;r6 save data
lc 0xff,r7 ; value to store
loop4_w:
ldb r4,0,r6
stb r4,0,r7
and r3,r3,r8 ; adress for read loop
lc 64,r9 ; counter which gets =r5 for the written item
lc 0x01, r10 ; compare value
lc 8, r11 ; x8 loop counter
;r12 - read data
 
loop4_chk_8:
lc 8,r13 ; chk loop x1 counter
loop4_chk_1:
ldb r8,0,r12
cjeq r9,r5,test4_stored_val
cjne r12,r10,error4_1
test4_good:
addi r10,1,r10
subi r13,1,r13
addi r8,1,r8
subi r9,1,r9
cjuge r13,r0,loop4_chk_1
addi r10,8,r10
subi r11,1,r11
cjuge r11,r0,loop4_chk_8
stb r4,0,r6
addi r4,1,r4
subi r5,1,r5
cjuge r5,r0,loop4_w
cjeq r0,r0,test4_end
 
error4_1:
andi r10,0xff,r12
ori r12,0x4000,r2
cjeq r0,r0,error4_1
 
test4_stored_val:
cjne r12,r7,error4_1
cjeq r0,r0,test4_good
 
test4_end:
 
lc 4,r2
 
 
;test #5 - write word
 
lc cl1,r3 ; base of data
lc cl1,r4 ;adress of write
lc 64,r5 ; write loop counter
;r6 save data
lc 0xffff,r7 ; value to store
loop5_w:
ldw r4,0,r6
stw r4,0,r7
and r3,r3,r8 ; adress for read loop
lc 64,r9 ; counter which gets =r5 for the written item
lc 0x0201, r10 ; compare value
lc 8, r11 ; x8 loop counter
;r12 - read data
 
loop5_chk_8:
lc 4,r13 ; chk loop x2 counter
loop5_chk_2:
ldw r8,0,r12
cjeq r9,r5,test5_stored_val
cjne r12,r10,error5_1
test5_good:
addi r10,0x0202,r10
subi r13,1,r13
addi r8,2,r8
subi r9,2,r9
cjuge r13,r0,loop5_chk_2
addi r10,0x0808,r10
subi r11,1,r11
cjuge r11,r0,loop5_chk_8
stw r4,0,r6
addi r4,2,r4
subi r5,2,r5
cjuge r5,r0,loop5_w
cjeq r0,r0,test5_end
 
error5_1:
andi r10,0xff,r12
ori r12,0x5000,r2
cjeq r0,r0,error5_1
 
test5_stored_val:
cjne r12,r7,error5_1
cjeq r0,r0,test5_good
 
test5_end:
 
lc 5,r2
 
 
;test #6 - write longword
 
lc cl1,r3 ; base of data
lc cl1,r4 ;adress of write
lc 64,r5 ; write loop counter
;r6 save data
lc 0xffff,r7 ; value to store
lch r7,0xffff,r7
loop6_w:
ldl r4,0,r6
stl r4,0,r7
and r3,r3,r8 ; adress for read loop
lc 64,r9 ; counter which gets =r5 for the written item
lc 0x0201, r10 ; compare value
lch r10,0x0403,r10
lc 8, r11 ; x8 loop counter
;r12 - read data
lc 0x0404,r14 ; add value to r10
lch r14,0x0404,r14
lc 0x0808,r15 ; add value r10 - x8 loop
lch r15,0x0808,r15
 
loop6_chk_8:
lc 2,r13 ; chk loop x4 counter
loop6_chk_4:
ldl r8,0,r12
cjeq r9,r5,test6_stored_val
cjne r12,r10,error6_1
test6_good:
add r10,r14,r10
subi r13,1,r13
addi r8,4,r8
subi r9,4,r9
cjuge r13,r0,loop6_chk_4
add r10,r15,r10
subi r11,1,r11
cjuge r11,r0,loop6_chk_8
stl r4,0,r6
addi r4,4,r4
subi r5,4,r5
cjuge r5,r0,loop6_w
cjeq r0,r0,test6_end
 
error6_1:
andi r10,0xff,r12
ori r12,0x6000,r2
cjeq r0,r0,error6_1
 
test6_stored_val:
cjne r12,r7,error6_1
cjeq r0,r0,test6_good
 
test6_end:
 
lc 6,r2
 
;test #7 - cacheline register forwarding
lc cl2,r3
lc 5,r4
lc cl2_6,r5
lc 0,r7
lc 15,r8
loop7:
ldl r3,0,r6
stl r5,0,r6
ldl r5,0,r6
add r7,r6,r7
addi r3,4,r3
subi r4,1,r4
cjuge r4,r0,loop7
cjeq r8,r7,skiperr7
error7_1:
lc 0x7000,r2
cjeq r0,r0,error7_1
skiperr7:
 
lc 7,r2
 
; test #8 - cache tag register forwarding
lc cl2,r3
lc 5,r4
;lc cl2_6,r5
lc 0,r7
lc 15,r8
lc 0,r9
loop8:
ldl r3,0,r6
stl r3,64,r6
ldl r3,64,r6
ldl r3,0,r5
add r7,r6,r7
add r9,r5,r9
addi r3,4,r3
subi r4,1,r4
cjuge r4,r0,loop8
cjne r9,r8,error8_1
cjeq r8,r7,skiperr8
error7_1:
lc 0x8000,r2
cjeq r0,r0,error8_1
skiperr8:
 
lc 8,r2
 
 
test_end_all:
cjeq r0,r0,test_end_all
 
 
section data
align 64
cl1:
DB 0x1  0x2  0x3  0x4  0x5  0x6  0x7  0x8
DB 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18
DB 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28
DB 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38
DB 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48
DB 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58
DB 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68
DB 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78
cl2:
DL 1 2 3 4 5
cl2_6:
DL 0
section bss
align 64
cl3:
 
 

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[/] [suslik/] [trunk/] [native asm/] [testmem6.s] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	gorand2	`lc 0,r0 ;always zero`
2			`lc 0,r2 ;$monitor-ed register; small numbers=pass test, numbers>0x1000=error`
3
4			`; test #9 - write back test`
5
6			`lc cl3,r3 ; adress`
7			`lc 10,r4 ; loop counter`
8			`lc 1000,r5 ; value to store`
9			`loop9_w:`
10			`stl r3,0,r5`
11			`addi r5,11,r5`
12			`addi r3,0x1000,r3`
13			`subi r4,1,r4`
14			`cjuge r4,r0,loop9_w`
15			`lc cl3,r3 ; adress`
16			`lc 10,r4 ; loop counter`
17			`lc 1000,r5 ; value to compare`
18			`; r6 - load value`
19			`loop9_r:`
20			`ldl r3,0,r6`
21			`cjne r6,r5,error9_1`
22			`addi r5,11,r5`
23			`addi r3,0x1000,r3`
24			`subi r4,1,r4`
25			`cjuge r4,r0,loop9_r`
26			`cjeq r0,r0,skiperr9`
27			`error9_1:`
28			`lc 0x9000,r2`
29			`cjeq r0,r0,error9_1`
30			`skiperr9:`
31
32			`lc 9,r2`
33
34			`; test #10 - more complete write back test`
35
36			`lc cl3,r3 ; adress`
37			`lc 10,r4 ; loop counter`
38			`lc 1000,r5 ; value to store`
39			`loop10_w_32:`
40			`lc 32,r7 ; inner loop counter`
41			`and r3,r3,r8 ; inner loop pointer`
42			`loop10_w_1:`
43			`stw r8,0,r5`
44			`addi r5,11,r5`
45			`addi r8,2,r8`
46			`subi r7,1,r7`
47			`cjuge r7,r0,loop10_w_1`
48			`addi r3,0x1000,r3`
49			`subi r4,1,r4`
50			`cjuge r4,r0,loop10_w_32`
51
52			`lc cl3,r3 ; adress`
53			`lc 10,r4 ; loop counter`
54			`lc 1000,r5 ; value to compare`
55			`; r6 - load value`
56			`loop10_r_32:`
57			`lc 32,r7 ; inner loop counter`
58			`and r3,r3,r8 ; inner loop pointer`
59			`loop10_r_1:`
60			`ldw r8,0,r6`
61			`cjne r6,r5,error10_1`
62			`addi r5,11,r5`
63			`addi r8,2,r8`
64			`subi r7,1,r7`
65			`cjuge r7,r0,loop10_r_1`
66			`addi r3,0x1000,r3`
67			`subi r4,1,r4`
68			`cjuge r4,r0,loop10_r_32`
69			`cjeq r0,r0,skiperr10`
70			`error10_1:`
71			`lc 0xa000,r2`
72			`cjeq r0,r0,error10_1`
73			`skiperr10:`
74
75			`lc 10,r2`
76
77
78			`; test #1`
79			`lc cl1,r3 ;data base register`
80			`lc 0,r4 ;effective address`
81			`lc 0x1, r5 ; value to compare`
82			`; load data into r6`
83			`lc 8,r7 ; x1 loop counter`
84			`lc 8,r8 ; x8 loop counter`
85
86			`and r3,r3,r4`
87
88			`loop1_8:`
89			`lc 8,r7`
90			`loop1_1:`
91			`ldb r4,0,r6`
92			`cjne r6,r5,error1_1`
93			`addi r4,1,r4`
94			`addi r5,1,r5`
95			`subi r7,1,r7`
96			`cjuge r7,r0,loop1_1`
97			`addi r5,8,r5`
98			`subi r8,1,r8`
99			`cjuge r8,r0,loop1_8`
100			`cjeq r0,r0,skiperr1`
101			`error1_1:`
102			`lc 0x1000,r1 ;error code`
103			`or r1,r5,r2`
104			`cjeq r0,r0, error1_1`
105			`skiperr1: ;test 1 passed`
106			`lc 1,r2`
107
108			`; test #2`
109			`lc cl1,r3 ;data base register`
110			`lc 0,r4 ;effective address`
111			`lc 0x0201, r5 ; value to compare`
112			`; load data into r6`
113			`lc 4,r7 ; x2 loop counter`
114			`lc 8,r8 ; x8 loop counter`
115
116			`and r3,r3,r4`
117
118			`loop2_8:`
119			`lc 4,r7`
120			`loop2_2:`
121			`ldw r4,0,r6`
122			`cjne r6,r5,error2_1`
123			`addi r4,2,r4`
124			`addi r5,0x0202,r5`
125			`subi r7,1,r7`
126			`cjuge r7,r0,loop2_2`
127			`addi r5,0x0808,r5`
128			`subi r8,1,r8`
129			`cjuge r8,r0,loop2_8`
130			`cjeq r0,r0,skiperr2`
131			`error2_1:`
132			`lc 0x2000,r1 ;error code`
133			`andi r5,0xff,r5`
134			`or r1,r5,r2`
135			`cjeq r0,r0, error2_1`
136			`skiperr2: ;test 2 passed`
137
138			`lc 2,r2`
139
140			`; test #3 read long`
141			`lc cl1,r3 ;data base register`
142			`lc 0,r4 ;effective address`
143			`lc 0x0201, r5 ; value to compare`
144			`lch r5,0x0403,r5`
145			`; load data into r6`
146			`lc 2,r7 ; x4 loop counter`
147			`lc 8,r8 ; x8 loop counter`
148			`lc 0x0404,r9 ; value to add to r5`
149			`lch r9,0x0404,r9`
150			`lc 0x0808,r10 ; add to r5 on loop3_8`
151			`lch r10,0x0808,r10`
152
153			`and r3,r3,r4`
154
155			`loop3_8:`
156			`lc 2,r7`
157			`loop3_4:`
158			`ldl r4,0,r6`
159			`cjne r6,r5,error3_1`
160			`addi r4,4,r4`
161			`add r5,r9,r5`
162			`subi r7,1,r7`
163			`cjuge r7,r0,loop3_4`
164			`add r5,r10,r5`
165			`subi r8,1,r8`
166			`cjuge r8,r0,loop3_8`
167			`cjeq r0,r0,skiperr3`
168			`error3_1:`
169			`lc 0x3000,r1 ;error code`
170			`andi r5,0xff,r5`
171			`or r1,r5,r2`
172			`cjeq r0,r0, error3_1`
173			`skiperr3: ;test 3 passed`
174
175			`lc 3,r2`
176
177			`;test #4 - write byte`
178
179			`lc cl1,r3 ; base of data`
180			`lc cl1,r4 ;adress of write`
181			`lc 64,r5 ; write loop counter`
182			`;r6 save data`
183			`lc 0xff,r7 ; value to store`
184			`loop4_w:`
185			`ldb r4,0,r6`
186			`stb r4,0,r7`
187			`and r3,r3,r8 ; adress for read loop`
188			`lc 64,r9 ; counter which gets =r5 for the written item`
189			`lc 0x01, r10 ; compare value`
190			`lc 8, r11 ; x8 loop counter`
191			`;r12 - read data`
192
193			`loop4_chk_8:`
194			`lc 8,r13 ; chk loop x1 counter`
195			`loop4_chk_1:`
196			`ldb r8,0,r12`
197			`cjeq r9,r5,test4_stored_val`
198			`cjne r12,r10,error4_1`
199			`test4_good:`
200			`addi r10,1,r10`
201			`subi r13,1,r13`
202			`addi r8,1,r8`
203			`subi r9,1,r9`
204			`cjuge r13,r0,loop4_chk_1`
205			`addi r10,8,r10`
206			`subi r11,1,r11`
207			`cjuge r11,r0,loop4_chk_8`
208			`stb r4,0,r6`
209			`addi r4,1,r4`
210			`subi r5,1,r5`
211			`cjuge r5,r0,loop4_w`
212			`cjeq r0,r0,test4_end`
213
214			`error4_1:`
215			`andi r10,0xff,r12`
216			`ori r12,0x4000,r2`
217			`cjeq r0,r0,error4_1`
218
219			`test4_stored_val:`
220			`cjne r12,r7,error4_1`
221			`cjeq r0,r0,test4_good`
222
223			`test4_end:`
224
225			`lc 4,r2`
226
227
228			`;test #5 - write word`
229
230			`lc cl1,r3 ; base of data`
231			`lc cl1,r4 ;adress of write`
232			`lc 64,r5 ; write loop counter`
233			`;r6 save data`
234			`lc 0xffff,r7 ; value to store`
235			`loop5_w:`
236			`ldw r4,0,r6`
237			`stw r4,0,r7`
238			`and r3,r3,r8 ; adress for read loop`
239			`lc 64,r9 ; counter which gets =r5 for the written item`
240			`lc 0x0201, r10 ; compare value`
241			`lc 8, r11 ; x8 loop counter`
242			`;r12 - read data`
243
244			`loop5_chk_8:`
245			`lc 4,r13 ; chk loop x2 counter`
246			`loop5_chk_2:`
247			`ldw r8,0,r12`
248			`cjeq r9,r5,test5_stored_val`
249			`cjne r12,r10,error5_1`
250			`test5_good:`
251			`addi r10,0x0202,r10`
252			`subi r13,1,r13`
253			`addi r8,2,r8`
254			`subi r9,2,r9`
255			`cjuge r13,r0,loop5_chk_2`
256			`addi r10,0x0808,r10`
257			`subi r11,1,r11`
258			`cjuge r11,r0,loop5_chk_8`
259			`stw r4,0,r6`
260			`addi r4,2,r4`
261			`subi r5,2,r5`
262			`cjuge r5,r0,loop5_w`
263			`cjeq r0,r0,test5_end`
264
265			`error5_1:`
266			`andi r10,0xff,r12`
267			`ori r12,0x5000,r2`
268			`cjeq r0,r0,error5_1`
269
270			`test5_stored_val:`
271			`cjne r12,r7,error5_1`
272			`cjeq r0,r0,test5_good`
273
274			`test5_end:`
275
276			`lc 5,r2`
277
278
279			`;test #6 - write longword`
280
281			`lc cl1,r3 ; base of data`
282			`lc cl1,r4 ;adress of write`
283			`lc 64,r5 ; write loop counter`
284			`;r6 save data`
285			`lc 0xffff,r7 ; value to store`
286			`lch r7,0xffff,r7`
287			`loop6_w:`
288			`ldl r4,0,r6`
289			`stl r4,0,r7`
290			`and r3,r3,r8 ; adress for read loop`
291			`lc 64,r9 ; counter which gets =r5 for the written item`
292			`lc 0x0201, r10 ; compare value`
293			`lch r10,0x0403,r10`
294			`lc 8, r11 ; x8 loop counter`
295			`;r12 - read data`
296			`lc 0x0404,r14 ; add value to r10`
297			`lch r14,0x0404,r14`
298			`lc 0x0808,r15 ; add value r10 - x8 loop`
299			`lch r15,0x0808,r15`
300
301			`loop6_chk_8:`
302			`lc 2,r13 ; chk loop x4 counter`
303			`loop6_chk_4:`
304			`ldl r8,0,r12`
305			`cjeq r9,r5,test6_stored_val`
306			`cjne r12,r10,error6_1`
307			`test6_good:`
308			`add r10,r14,r10`
309			`subi r13,1,r13`
310			`addi r8,4,r8`
311			`subi r9,4,r9`
312			`cjuge r13,r0,loop6_chk_4`
313			`add r10,r15,r10`
314			`subi r11,1,r11`
315			`cjuge r11,r0,loop6_chk_8`
316			`stl r4,0,r6`
317			`addi r4,4,r4`
318			`subi r5,4,r5`
319			`cjuge r5,r0,loop6_w`
320			`cjeq r0,r0,test6_end`
321
322			`error6_1:`
323			`andi r10,0xff,r12`
324			`ori r12,0x6000,r2`
325			`cjeq r0,r0,error6_1`
326
327			`test6_stored_val:`
328			`cjne r12,r7,error6_1`
329			`cjeq r0,r0,test6_good`
330
331			`test6_end:`
332
333			`lc 6,r2`
334
335			`;test #7 - cacheline register forwarding`
336			`lc cl2,r3`
337			`lc 5,r4`
338			`lc cl2_6,r5`
339			`lc 0,r7`
340			`lc 15,r8`
341			`loop7:`
342			`ldl r3,0,r6`
343			`stl r5,0,r6`
344			`ldl r5,0,r6`
345			`add r7,r6,r7`
346			`addi r3,4,r3`
347			`subi r4,1,r4`
348			`cjuge r4,r0,loop7`
349			`cjeq r8,r7,skiperr7`
350			`error7_1:`
351			`lc 0x7000,r2`
352			`cjeq r0,r0,error7_1`
353			`skiperr7:`
354
355			`lc 7,r2`
356
357			`; test #8 - cache tag register forwarding`
358			`lc cl2,r3`
359			`lc 5,r4`
360			`;lc cl2_6,r5`
361			`lc 0,r7`
362			`lc 15,r8`
363			`lc 0,r9`
364			`loop8:`
365			`ldl r3,0,r6`
366			`stl r3,64,r6`
367			`ldl r3,64,r6`
368			`ldl r3,0,r5`
369			`add r7,r6,r7`
370			`add r9,r5,r9`
371			`addi r3,4,r3`
372			`subi r4,1,r4`
373			`cjuge r4,r0,loop8`
374			`cjne r9,r8,error8_1`
375			`cjeq r8,r7,skiperr8`
376			`error7_1:`
377			`lc 0x8000,r2`
378			`cjeq r0,r0,error8_1`
379			`skiperr8:`
380
381			`lc 8,r2`
382
383
384			`test_end_all:`
385			`cjeq r0,r0,test_end_all`
386
387
388			`section data`
389			`align 64`
390			`cl1:`
391			`DB 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8`
392			`DB 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18`
393			`DB 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28`
394			`DB 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38`
395			`DB 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48`
396			`DB 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58`
397			`DB 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68`
398			`DB 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78`
399			`cl2:`
400			`DL 1 2 3 4 5`
401			`cl2_6:`
402			`DL 0`
403			`section bss`
404			`align 64`
405			`cl3:`
406
407