OpenCores
URL https://opencores.org/ocsvn/sv_dir_tb/sv_dir_tb/trunk

Subversion Repositories sv_dir_tb

[/] [sv_dir_tb/] [trunk/] [examples/] [internal/] [sv/] [tb_mod.sv] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 sckoarn
 
2
module tb_prg (dut_if.tb_conn tif);
3
 
4
  import tb_pkg::*;
5
 
6
  //  package and container
7
  cmd_lst  cmds;
8
  tb_trans r;
9
 
10
  integer  in_fh;
11
  integer  stat;
12
  integer  fi;
13
  logic    clock;
14
  lst_item  ti;
15
 
16
  string STM_FILE = "../stm/stimulus_file.stm";
17
  string tmp_fn;
18
 
19
  //  Handle plus args
20
  initial begin : file_select
21
    if($value$plusargs("STM_FILE=%s", tmp_fn)) begin
22
      STM_FILE = tmp_fn;
23
    end
24
  end
25
 
26
  //////////////////////////////////////////////
27
  //   DUT signals
28
  logic ack;
29
  logic [31:0] datai;
30
  logic [31:0] datao;
31
  logic [31:0] addr;
32
  logic w_n  =  1'b1;
33
  logic clk;
34
  logic rst_n;
35
  logic [31:0] tdut_out;
36
  logic [31:0] tdut_in = 0;
37
 
38
  ////////////////////////////////////////////////////////
39
  //  drive / read DUT  signals by hierarchy connection
40
  assign tif.rst_n = rst_n;
41
  assign tif.clk = clock;
42
  assign tb_top.U1.cpu.w_n = w_n;
43
  assign tb_top.U1.cpu.addr = addr;
44
  assign tb_top.U1.cpu.datao = datao;
45
  assign datai = tb_top.U1.cpu.datai;
46
  assign tb_top.U1.in1 = tdut_in;
47
  assign tdut_out = tb_top.U1.out1;
48
  assign ack = tb_top.U1.cpu.ack;
49
 
50
  ////////////////////////////////////////////////////
51
  //  instruction variables
52
  integer  was_def     = 0;
53
  string   cmd_string;
54
  logic  [31:0]  tmp_vec;
55
 
56
  ////////////////////////////////////////////////////////////////////
57
  //   clock driver
58
  initial begin
59
    clock = 1;
60
    while(1) begin
61
      #10 clock = 0;
62
      #10 clock = 1;
63
    end
64
  end
65
 
66
  //////////////////////////////////////////////////////////
67
  //  stimulus_file processing
68
  initial begin : Process_STM
69
    cmds = new();
70
    r    = new();
71
    //  define the default instructions
72
    cmds.define_defaults();
73
    //  User instructions
74
    cmds.define_instruction("RESET", 0);
75
    cmds.define_instruction("READ", 1);
76
    cmds.define_instruction("WRITE", 2);
77
    cmds.define_instruction("VERIFY", 1);
78
    cmds.define_instruction("SET_I", 1);
79
    cmds.define_instruction("READ_O", 1);
80
 
81
    //  load the stimulus file
82
    cmds.load_stm(STM_FILE);
83
 
84
    r.cmd = cmds;
85
    /////////////////////////////////////////////////////
86
    //  the main loop.
87
    while (r.cmd != null) begin
88
      r      = r.cmd.get(r);
89
      r.next++;
90
 
91
      //  process default instructions
92
      was_def  =  r.cmd.exec_defaults(r);
93
      if(was_def) begin
94
        continue;
95
      end
96
 
97
      ///////////////////////////////////////////////////////
98
      //   Process User  instructions.
99
      // get the command string
100
      cmd_string = r.cmd.lst_cmds.cmd;
101
      //  output the dynamic text if there is some. (Note:  before command runs.)
102
      r.cmd.print_str_wvar();
103
 
104
      ///////////////////////////////////////////////////////////////////////////
105
      //  RESET
106
      if (cmd_string == "RESET") begin
107
        rst_n  =  1'b1;
108
        @(posedge clock);
109
        rst_n  =  1'b0;
110
        @(posedge clock);
111
        @(posedge clock);
112
        @(posedge clock);
113
        rst_n  =  1'b1;
114
        @(posedge clock);
115
      ///////////////////////////////////////////////////////////////////////////
116
      //  READ
117
      end else if (cmd_string == "READ") begin
118
        @(posedge clock);
119
        addr = r.rtn_val.par1;
120
        @(posedge clock);
121
        @(posedge clock);
122
        addr = 0;
123
        tmp_vec = datai;
124
      ///////////////////////////////////////////////////////////////////////////
125
      //  WRITE
126
      end else if (cmd_string == "WRITE") begin
127
        @(posedge clock);
128
        addr = r.rtn_val.par1;
129
        datao = r.rtn_val.par2;
130
        @(posedge clock)
131
        w_n  =  1'b0;
132
        @(posedge clock);
133
        w_n  =  1'b1;
134
        addr = 0;
135
        #1;
136
      ///////////////////////////////////////////////////////////////////////////
137
      //  VERIFY
138
      end else if (cmd_string == "VERIFY") begin
139
        verify_command : assert (tmp_vec == r.rtn_val.par1) else begin
140
          fi = r.cmd.lst_cmds.file_idx;
141
          ti = r.cmd.file_lst.get(fi);
142
          $fatal(0,"VERIFY failed expected: %x  Got: %x\nOn line number %3d of file %s",
143
                 r.rtn_val.par1, tmp_vec, r.cmd.lst_cmds.line_num, ti.txt);
144
        end
145
      ///////////////////////////////////////////////////////////////////////////
146
      //  SET_I
147
      end else if (cmd_string == "SET_I") begin
148
        tdut_in  =  r.rtn_val.par1;
149
        #0;
150
      end else if (cmd_string == "READ_O") begin
151
        tmp_vec = tdut_out;
152
        #0;
153
      end else begin
154
        $display("ERROR:  Command not found in the else if chain. Is it spelled correctly in the else if?");
155
      end //  end of else if chain
156
    end  //  end main while loop
157
    //  should never end up outside the while loop.
158
    $display("ERROR:  Some how, a run off the beginning or end of the instruction sequence, has not been caught!!");
159
  end   //  end Process_STM
160
 
161
endmodule // tb_prg
162
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.