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How to understand the SXP architecture.
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A graphic showing the architecture diagram will
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be supplied very soon.
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The processor is a pipelined processor which means
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that instructions are processed like an assembly line.
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The pipeline is broken into stages that do specific
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things with each instruction.
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The stages for the SXP are as such.
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Fetch - Get instructions from memory and control program counter
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Reg File - local register storage and look up
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ALU - Arithmetic logic unit / data munging
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WB - Determine where the data from the ALU/MEM READ/EXT BUS gets written back to.
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Please see the instr.txt document to see how instructions are built but
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basically an instruction is broken up into control fragments for each
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one of these mentioned stages. That is why is was mentioned
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that the instructions are non conventional and we get the added
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bonus of no Decoder stage and thus a faster pipeline. Each stage
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is responsible for reading a small section of the instruction and
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figuring out what to do with the rest of the data in the instruction or
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in the pipeline from the previous stage.
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A conventional processor with standard instructions needs a decoder to
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turn the instructions into microcode (possibly) the then a controller
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to turn the microcode into fragments that control each pipeline when
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necessary.
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This is a very simple processor. Right now it is not intended to
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be a processor with diferent modes and other high level functions.
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(Although those features can be added at a later time or in another
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version.)
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There is a need for both low level microcontrollers and the feature
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filled microprocessors. It is just a question of scope and intended
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design goals.
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Sections of the SXP code
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Verilog simulation of the SXP:
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The SXP processor was written in Verilog code and tested with the
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GPL'ed Icarus verilog simulator. If you want to follow this path
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then please get the latest development snapshot. I have tested
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the current realease on Icaurus and everything works as
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expected.
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SXP C++ Model
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The C++ model is an attempt to simulate the operation of the
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SXP in C++ code. It is not perfect but the current implementation
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will simulate ok.
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Visual Instruction Development tool - coder.tcl
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coder.tcl is a TK/TCL tool that help to develop
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small assembly language programs.
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Assembly language verilog files.
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All assembly language files are in verilog memory format.
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This is done for easy simulation in verilog. Tools can later
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be written to translate verilog memory files into binary
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files. (This will be useful if the SXP is synthesized into
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an FPGA.)
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Directory structure
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-------------------
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- /doc
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instr.txt - Assembly Instruction Documentation
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int_cont.txt - Interupt documentation
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README.txt - This file
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- /sim
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test_sxp.v - Testbench for SXP processor
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test.sxp - Assembly language instructions file
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(Written in verilog memory format. Loaded into instruction RAM)
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- /src
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sxp.v - SXP processor top level verilog
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- /fetch
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/src
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fetch.v - fetch module code
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/sim
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test_fetch.v - testbench for fetch module
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- /dpmem
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/src
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dpmem.v - behavioral dual port memory
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/sim
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test_mem.v - Testbench for behavioral dual port memory
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- /tcl
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coder.tcl - TCL/TK Visual Instruction Development Tool
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- /int_cont
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/src
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int_cont.v - interupt controller module verilog code
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/sim
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test_int_cont.v - testbench for interupt controller
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- /regf
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/src
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mem_regf.v - memory based reg file
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sync_regf.v - syncronous reg file
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regf_status.v - scoreboard module for reg file
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/sim
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test_regf.v - testbench for reg file
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- /timer_cont
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/src
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timer_cont.v - timer controller module verilog source
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/sim
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test_timer.v - testbench for timer controller
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- /csim - C++ model of SXP processor
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- /csim/alu/alu.cc - alu c++ model
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- /csim/ext/ext.cc - ext bus c++ model
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- /csim/fetch/fetch.cc - fetch module c++ model
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- /csim/memory/memory.cc - memory c++ model
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- /csim/reg_file/reg_file.cc - register file c++ model
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- /csim/sxp/sxp.cc - SXP processor main class for processor
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run_sxp - executable script to run the c++ model
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sxp_sim.cc - c++ simulation file (instantiates the processor and runs code)
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test.sxp - Assembly language code (Verilog based memory file)
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