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samg |
SXP Processor
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1st version.
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Decoderless Stage Pipeline
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This style does not make for a set number of instructions.
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Instrucions are built from the configuration of the pre decoded
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setup bits.
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Issues:
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1. How to organize a ext bus read and write
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----------------------------------------------------------------------------------------------------
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Destination for write back data
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00 Register (Aritmetic, Logical and Memory Loads)
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01 PC (Flow control)
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10 Memory (Store)
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11 Extension Interface
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---------------------------------------------------------------------------------------------------
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Source (Register or immediate)
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1st Source for the ALU must be a register , PC or Ext Data Bus 1 (Ext Reg A)
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2nd Source for the ALU must be a register, immediate or Ext Data Bus 2 (Ext Reg B)
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A B
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000 (Reg, Reg)
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001 (Reg, Imm) Dest Reg and Src Reg are same
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010 (PC , Reg)
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011 (PC , Imm)
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100 (Reg, Ext)
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101 (Ext, Reg)
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110 (Ext, Imm)
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111 (Ext, Ext)
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--------------------------------------------------------------------------------------------------
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ALU Instruction
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ALU Output YA YB
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|----------|-----------|
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000 PASS | A | B |
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001 ADD | A + B | A + B (SE)|
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010 SUB | A - B | A - B (SE)|
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011 MULT | A*B(MSW) | A*B(LSW)|
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100 AND/OR | A & B | A | B |
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101 XOR | A ^ B | ~(A ^ B) |
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110 | RESERVED | RESERVED |
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111 PASS_SW | Al:Ah | Bl:Bh |
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|-----------------------
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Note: (SE) means sign extended from 16th bit up to 32nd bit.
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(MSW) means most significant word result
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(LSW) means least significant word result
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The ALU instructions are condensed by using both YA and YB outputs for multiple functions.
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example:
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The add result that comes out of result YA is a A(32 bits) + B(32 bits) add.
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YB result is be a A(32 bits) + B(16 sign extended bits)
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*** This takes care of worrying about an instruction to sign extend bits for relative jumps.
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ALU Development Note:
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The best way to catagorize the ALU instructions is by number of inputs and number of outputs.
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Single Input -> Single Output (NOT and etc..)
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Single Input -> Double Output (I don't know of any)
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Double Input -> Single Output (ADD, SUB, AND, OR, XOR)
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Double Input -> Double Output (MULT)
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The double input single output instructions can be combined.
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I am tempted to say that there will not be any single input commands
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to simpluify the ALU module and instructions.
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---------------------------------------------------------------------------------------------
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Write Back Data Source
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Code Data Source
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---- ---------------------------
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0000 ALU output A
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0001 ALU output B
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0010 From Memory (Load)
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0011 From Extension Interface
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0100 ALU A FLag Z (zero extended)
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0101 ALU A Flag N (zero extended)
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0110 ALU A Flag V (zero extended)
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0111 ALU A Flag C (zero extended)
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1000 ALU B FLag Z (zero extended)
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1001 ALU B Flag N (zero extended)
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1010 ALU B Flag V (zero extended)
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1011 ALU B Flag C (zero extended)
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1100 EXT ALU FLag Z (zero extended)
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1101 EXT ALU Flag N (zero extended)
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1110 EXT ALU Flag V (zero extended)
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1111 EXT ALU Flag C (zero extended)
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Note:
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Flag Z = Zero flag (1 if result all zeros)
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Flag N = Negative flag (1 if MSB is a one)
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FLag C = Carry flag (1 if carry with sub or add)
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Flag V = Overflow flag (1 if overflow with sub or add)
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-----------------------------------------------------------------------------------------------
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Conditional jump instructions
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Dest = PC
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Source = Reg, Reg
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ALU = PASS
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WB_SRC = YA
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(The msb of YB will be used to determine if the jump should be taken)
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JNZ R1 (Address) , R2 (lsb condition value)
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JZ R1 (Address) , R2 (lsb condition value)
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The (bits that control this are only used when PC is the target)
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The lsb of the instruction is used to determine if this is a conditional (1) or uncond jump(0).
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The next to lsb is used to determine if the jump is a JZ or JNZ for conditional jumps.
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(NEW)
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The third bit is used to detmermine if this is a jump and link as well.
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The register for the link is held in the destination address.
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This field was unused in pc dest operations and is perfect for all sort of
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jump and link options. It also greatly simplified the architecture.
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(Link address was tied to addrb which caused huge limitations.)
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This conditional jump will happen if the lsb of the instruction is a 1
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--------------------------------------------------------------------------------------------------
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ALU Extension instructions
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ALU input words A and B are always broadcasted to the ext interface.
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If an extension ALU instruction is to be used then the write back source is
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set to the extention inteface. This bypasses the base ALU completely and allow the
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results to be written back to the destination.
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-------------------------------------------------------------------------------------------------
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Ext read instructions.
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In Ext Bus reads, the Ext circuit should use the ALU Op + WB src fields to determine what
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type of Ext operation is required.
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Ex. ALU instruction 0 is used to make a call to the read the Ext bus.
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If ALU instruction is 1 - 7 then it could be an ext ALU instruction.
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----------------------------------------------------------------------------------------------------
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The interupt is internal controlled by an interupt module inside the sxp.
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Even though you cannot issue a [pc] dest, [pc,imm] src JAL type instruction, the interupt module
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can control and insert the JAL signal.
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I have not figured out how the user can generate an interupt that causes a JAL to happen.
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One way is write the vector address in one reg and enter a JAL type instruction. This should
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work OK, it is just not as clean as the internal interupt generated signal.
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By using the immediate field, there are a total of 65535 possible interupts. This should
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surfice.
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